Assignment no:1

Digital System Design

EE 417

Muhammad Abdullah Bin Faisal

201390012
Submitted to: Dr Aqeel Aslam

4*1 MUX

Schematic Diagram
 Truth Table

S0 S1 D1 D2 D3 D4 Y

0 0 1 X X X 1

0 1 X 1 X X 1

1 0 X X 1 X 1

1 1 X X X 1 1

Logical Truth Table

S0 S1 Y

0 0 D1

0 1 D2

1 0 D3

1 1 D4
 4x1 MUX (Structural Style)

Verilog Code
module task(
input d1,d2,d3,d4,s0,s1,
output l
);

wire not_s0, not_s1, not_c, not_d, wire1, wire2, wire3 ,wire4;

not (not_s0,s0);
not (not_s1,s1);

and(wire1,not_s0,not_s1,d1);

and(wire2,not_s0,s1,d2);

and(wire3,s0,not_s1,d3);

and(wire4,s0,s1,d4);

or (l,wire1,wire2,wire3,wire4);

endmodule

Test Bench
module tb;

// Inputs
reg d1;
reg d2;
reg d3;
reg d4;
reg s0;
reg s1;

// Outputs
wire l;

// Instantiate the Unit Under Test (UUT)

lab uut (
.d1(d1),
.d2(d2),
 .d3(d3),
.d4(d4),
.s0(s0),
.s1(s1),
.l(l)
);

initial begin
// Initialize Inputs
d1 = 1;
d2 = 0;
d3 = 0;
d4 = 0;
s0 = 0;
s1 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

d1 = 0;
d2 = 1;
d3 = 0;
d4 = 0;
s0 = 0;
s1 = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Add stimulus here

d1 = 0;
d2 = 0;
d3 = 1;
d4 = 0;
s0 = 1;
s1 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Add stimulus here

d1 = 0;
 d2 = 0;
d3 = 0;
d4 = 1;
s0 = 1;
s1 = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

Waveform
RTL Schematic
Technology Schematic
Summary
 4x1 MUX (RTL Logic Gate Method)
Verilog Code

module task(
input d1, d2, d3, d4, // Data inputs
input s0, s1, // Select inputs
output l // Output
);

assign x1=d1&(~s0)&(~s1);

assign x2=d2&(~s0)&(s1);

assign x3=d3&(s0)&(~s1);

assign x4=d4&(s0)&(s1);

assign l=x1|x2|x3|x4;

endmodule

Test Bench
module tb;

// Inputs
reg d1;
reg d2;
reg d3;
reg d4;
reg s0;
reg s1;

// Outputs
wire l;

// Instantiate the Unit Under Test (UUT)

lab uut (
.d1(d1),
.d2(d2),
.d3(d3),
 .d4(d4),
.s0(s0),
.s1(s1),
.l(l)
);

initial begin
// Initialize Inputs
// Initialize Inputs
d1 = 1;
d2 = 0;
d3 = 0;
d4 = 0;
s0 = 0;
s1 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

d1 = 0;
d2 = 1;
d3 = 0;
d4 = 0;
s0 = 0;
s1 = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Add stimulus here

d1 = 0;
d2 = 0;
d3 = 1;
d4 = 0;
s0 = 1;
s1 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Add stimulus here

d1 = 0;
 d2 = 0;
d3 = 0;
d4 = 1;
s0 = 1;
s1 = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

Waveform
RTL Schematic
Technology Schematic
Summary
 4x1 MUX (Behavioral Style)
Verilog Code
module lab (in0, in1, in2, in3, sel, out);
input in0, in1, in2, in3;
input [1:0] sel;
output reg out;

always @(in0, in1, in2, in3, sel) begin

case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
default: out = 1'b0; // Default case to handle unexpected sel values
endcase
end
endmodule

Test Bench
module tb;

// Inputs
reg in0;
reg in1;
reg in2;
reg in3;
reg [1:0] sel;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

lab uut (
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.sel(sel),
.out(out)
);

initial begin
// Initialize Inputs
 in0 = 1;
in1 = 0;
in2 = 0;
in3 = 0;
sel = 0;

// Wait 100 ns for global reset to finish

#100;

in0 = 0;
in1 = 1;
in2 = 0;
in3 = 0;
sel = 1;

// Wait 100 ns for global reset to finish

#100;

in0 = 0;
in1 = 0;
in2 = 1;
in3 = 0;
sel = 2
;

// Wait 100 ns for global reset to finish

#100;

in0 = 0;
in1 = 0;
in2 = 0;
in3 = 1;
sel = 3;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
 Waveform

RTL Schematic
Technology Schematic

Summary
3x8 Decoder Using Two (2x4) Decoder
Schematic Diagram
 Truth Table

A0 A1 A2 d0 d1 d2 ed3 d4 d5 d6 d7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Logical Truth Table

A0 A1 A2 Y

0 0 0 d0

0 0 1 d1

0 1 0 d2
 0 1 1 d3

1 0 0 d4

1 0 1 d5

1 1 0 d6

1 1 1 d7

3x8 Decoder (Structural Style)

Verilog Code
module task(d0,d1,d2,d3,d4,d5,d6,d7,a,b,e
);
input a,b,e;
output d0,d1,d2,d3,d4,d5,d6,d7;
wire a_not,b_not,e_not;

not (a_not,a);

not (b_not,b);

not (e_not,e);

and(d0,e_not,a_not,b_not);

and(d1,e_not,a_not,b);

and(d2,e_not,a,b_not);

and(d3,e_not,a,b);

and(d4,e,a_not,b_not);
and(d5,e,a_not,b);

and(d6,e,a,b_not);

and(d7,e,a,b);

endmodule

Test Bench
module tb;

// Inputs
reg a;
reg b;
reg e;

// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

// Instantiate the Unit Under Test (UUT)

decoder uut (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7),
.a(a),
.b(b),
.e(e)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
e = 0;
 // Wait 100 ns for global reset to finish
#100;

// Add stimulus here

// Add stimulus here
// Initialize Inputs
a = 0;
b =1;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 0;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 1;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 0;
b = 0;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 0;
b = 1;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 0;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 1;
e = 1;

// Wait 100 ns for global reset to finish

#100;
end

endmodule

Waveform
RTL Schematic
Technology Schematic
 Summary

3x8 Decoder (RTL Logic Gate Method)

Verilog Code

module task(d,a,b,e );
input a,b ,e;
output [7:0]d;

assign d[0] = ~a & ~b & ~e;

assign d[1] = ~a & ~b & e;
assign d[2] = ~a & b & ~e;
assign d[3] = ~a & b & e;
assign d[4] = a & ~b & ~e;
assign d[5] = a & ~b & e;
assign d[6] = a & b & ~e;
assign d[7] = a & b & e;

endmodule
Test Bench

module decodertext;

// Inputs
reg a;
reg b;
reg e;

// Outputs
wire [7:0] d;

// Instantiate the Unit Under Test (UUT)

decoder uut (
.d(d),
.a(a),
.b(b),
.e(e)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
e = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a = 0;
b =0;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 0;
b = 1;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 0;
b = 1;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 0;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 0;
e = 1;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 1;
e = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;
b = 1;
e = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule
 Waveform

RTL Schematic
Technology Schematic
 Summary

3x8 Decoder (Behavioral Style)

Verilog Code
module decoder(d, a);
input [2:0] a;
output reg [7:0] d;

always @(a) begin

case (a)
3'b000: d = 8'b00000001;
3'b001: d = 8'b00000010;
3'b010: d = 8'b00000100;
3'b011: d = 8'b00001000;
3'b100: d = 8'b00010000;
3'b101: d = 8'b00100000;
3'b110: d = 8'b01000000;
3'b111: d = 8'b10000000;
 default: d = 8'bxxxxxxxx;
endcase
end
endmodule

Test Bench
module tb;

// Inputs
reg [2:0] a;

// Outputs
wire [7:0] d;

// Instantiate the Unit Under Test (UUT)

decoder uut (
.d(d),
.a(a)
);

initial begin
// Initialize Inputs
a = 0;

// Wait 100 ns for global reset to finish

#100;
// Initialize Inputs
a = 1;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 2;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 3;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 4;
 // Wait 100 ns for global reset to finish
#100;

// Initialize Inputs
a = 5;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 6;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

// Initialize Inputs
a = 7;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

Waveform
 RTL Schematic

Technology Schematic
Summary