October 08, 2018

W65C02S
8–bit Microprocessor

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Copyright ©1981-2018 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction, in whole, or in part, in any form.
 TABLE OF CONTENTS
1 INTRODUCTION....................................................................................................... 5
1.1 FEATURES OF THE W65C02S ...........................................................................................................5
2 FUNCTIONAL DESCRIPTION ................................................................................. 6
2.1 INSTRUCTION REGISTER (IR) AND DECODE ........................................................................................6 2.2
TIMING CONTROL UNIT (TCU)...........................................................................................................6 2.3
ARITHMETIC AND LOGIC UNIT (ALU) .................................................................................................6 2.4
ACCUMULATOR REGISTER (A)...........................................................................................................6 2.5 I NDEX
REGISTERS (X AND Y).............................................................................................................6 2.6 P ROCESSOR
STATUS REGISTER (P) ..................................................................................................6 2.7 P ROGRAM
COUNTER REGISTER (PC) ................................................................................................7 2.8 S TACK POINTER
REGISTER (S)..........................................................................................................7

3 PIN FUNCTION DESCRIPTION ............................................................................... 9

3.1 ADDRESS BUS (A0-A15) ..................................................................................................................9 3.2
BUS ENABLE (BE)............................................................................................................................9 3.3 D ATA
BUS (D0-D7) ..........................................................................................................................9 3.4 I NTERRUPT
REQUEST (IRQB)............................................................................................................9 3.5 M EMORY LOCK
(MLB)......................................................................................................................9 3.6 N ON-MASKABLE
INTERRUPT (NMIB).................................................................................................9 3.7 N O CONNECT
(NC)...........................................................................................................................9 3.8 P HASE 2 IN (PHI2),
PHASE 2 OUT (PHI2O) AND PHASE 1 OUT (PHI1O)..........................................10 3.9 R EAD/WRITE
(RWB) ......................................................................................................................10 3.10 R EADY
(RDY) ................................................................................................................................10 3.11 R ESET
(RESB) ..............................................................................................................................10 3.12 S ET
OVERFLOW (SOB)...................................................................................................................11 3.13
SYNCHRONIZE WITH OPCODE FETCH (SYNC) ................................................................................11 3.14
POWER (VDD) AND GROUND (VSS)................................................................................................11 3.15
VECTOR PULL (VPB)......................................................................................................................11

4 ADDRESSING MODES .......................................................................................... 15

4.1 ABSOLUTE A...................................................................................................................................15 4.2
ABSOLUTE INDEXED INDIRECT (A,X).................................................................................................15 4.3
ABSOLUTE INDEXED WITH X A,X ......................................................................................................15 4.4
ABSOLUTE INDEXED WITH Y A, Y......................................................................................................16 4.5
ABSOLUTE INDIRECT (A) .................................................................................................................16 4.6
ACCUMULATOR A ...........................................................................................................................16 4.7
IMMEDIATE ADDRESSING #..............................................................................................................16 4.8
IMPLIED I ........................................................................................................................................17 4.9
PROGRAM COUNTER RELATIVE R ....................................................................................................17 4.10
STACK S.........................................................................................................................................17 4.11 Z ERO
PAGE ZP ...............................................................................................................................17 4.12 Z ERO PAGE
INDEXED INDIRECT (ZP,X) .............................................................................................18 4.13 Z ERO PAGE
INDEXED WITH X ZP,X ...................................................................................................18 4.14 Z ERO PAGE
INDEXED WITH Y ZP, Y ..................................................................................................18 4.15 Z ERO PAGE
INDIRECT (ZP) ..............................................................................................................18 4.16 Z ERO PAGE
INDIRECT INDEXED WITH Y (ZP), Y .................................................................................19

5 OPERATION TABLES............................................................................................ 21
2
 6 DC, AC AND TIMING CHARACTERISTICS .......................................................... 23
6.2 DC CHARACTERISTICS TA = -40°C TO +85°C (PLCC, QFP) TA= 0°C TO 70°C (DIP)...................24 6.3

AC CHARACTERISTICS TA = -40°C TO +85°C (PLCC, QFP) TA= 0°C TO 70°C (DIP)...................25

7 CAVEATS............................................................................................................... 30 8
HARD CORE MODEL............................................................................................. 31 8.1

FEATURES OF THE W65C02S HARD CORE MODEL..........................................................................31 9 SOFT

CORE RTL MODEL ..................................................................................... 31 9.1 W65C02

SYNTHESIZABLE RTL-CODE IN VERILOG HDL ..................................................................31 10 ORDERING

INFORMATION................................................................................... 32
 3

TABLE OF TABLES
TABLE 3-1 VECTOR LOCATIONS............................................................................................................12
TABLE 3-2 PIN FUNCTION TABLE ..........................................................................................................12
TABLE 4-1 ADDRESSING MODE TABLE ................................................................................................20
TABLE 5-1 INSTRUCTION SET TABLE ...................................................................................................21
TABLE 5-2 W65C02S OPCODE MATRIX.................................................................................................22
TABLE 6-1 ABSOLUTE MAXIMUM RATINGS..........................................................................................23
TABLE 6-2 DC CHARACTERISTICS ........................................................................................................24
TABLE 6-3 AC CHARACTERISTICS .......................................................................................................25
TABLE 6-4 OPERATION, OPERATION CODES AND STATUS REGISTER...........................................27
TABLE 7-1 MICROPROCESSOR OPERATIONAL ENHANCEMENTS ...................................................30

TABLE OF FIGURES
FIGURE 2-1 W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM ...........................7
FIGURE 2-2 W65C02S MICROPROCESSOR PROGRAMMING MODEL.................................................8
FIGURE 3-1 W65C02S 40 PIN PDIP PINOUT..........................................................................................13
FIGURE 3-2 W65C02S 44 PIN PLCC PINOUT.........................................................................................13
FIGURE 3-3 W65C02S 44 PIN QFP PINOUT...........................................................................................14
FIGURE 6-1 IDD VS VDD.........................................................................................................................24
FIGURE 6-2 F MAX VS VDD....................................................................................................................24
FIGURE 6-3 GENERAL TIMING DIAGRAM..............................................................................................26

4
 1 INTRODUCTION
The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the
PHI2 clock can be stopped when it is in the high (logic 1) or low (logic 0) state. The variable length instruction
set and manually optimized core size makes the W65C02S an excellent choice for low power System-on-Chip
(SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor
Company, provides packaged chips for evaluation or volume production. To aid in system development, WDC
provides a software development suite (WDCTools).

You can find out more about our development hardware tools here:
http://wdc65xx.com/boards/w65c02sxb-engineering-development-system/

And software tools here:

https://wdc65xx.com/WDCTools

1.1 Features of the W65C02S

∙ 8-bit data bus

∙ 16-bit address bus provides access to 65,536 bytes of memory space

∙ 8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register

∙ 16-bit Program Counter

∙ 70 instructions

∙ 16 addressing modes

∙ 212 Operation Codes (OpCodes)

∙ Vector Pull (VPB) output indicates when interrupt vectors are being addressed

∙ WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease
interrupt latency and provide synchronization with external events
∙ Variable length instruction set provides for lower power and smaller code optimization over fixed
length instruction set processors
∙ Fully static circuitry

∙ Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/- 10%, 5.0+/- 5% specified

∙ Low Power consumption, 150uA@1MHz

 5

2 FUNCTIONAL DESCRIPTION
The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control Section.
Instructions obtained from program memory are executed by implementing a series of data transfers within the
Register Section. Signals that cause data transfers are generated within the Control Section.

2.1 Instruction Register (IR) and Decode

The Operation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the Data
Bus and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing and
interrupt signals, to generate various control signals for program execution.

2.2 Timing Control Unit (TCU)

The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is set to
zero for each instruction fetch, and is advanced at the beginning of each cycle for as many cycles as is
required to complete the instruction. Data transfers between registers depend upon decoding the contents of
both the IR and the TCU.

2.3 Arithmetic and Logic Unit (ALU)

All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU also
calculates the effective address for relative and indexed addressing modes. The result of a data operation is
stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags are updated following
the ALU data operation.

2.4 Accumulator Register (A)

The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and the
result of arithmetic and logical operations. Reconfigured versions of this processor family could have additional
accumulators.

2.5 Index Registers (X and Y)

There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to provide an
index value for calculation of the effective address. When executing an instruction with indexed addressing, the
microprocessor fetches the OpCode and the base address, and then modifies the address by adding the Index
Register contents to the address prior to performing the desired operation .

2.6 Processor Status Register (P)

The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C), Negative
(N), Overflow (V) and Zero (Z) status flags serve to report the status of ALU operations. These status flags are
tested with Conditional Branch instructions. The Decimal (D) and IRQB disable (I) are used as mode select
flags. These flags are set by the program to change microprocessor operations. Bit 5 is available for a user
status or mode bit.

6
 2.7 Program Counter Register (PC)

The 16-bit Program Counter Register (PC) provides the addresses which are used to step the microprocessor
through sequential program instructions. This register is incremented each time an instruction or operand is
fetched from program memory.

2.8 Stack Pointer Register (S)

The Stack Pointer Register (S) is an 8-bit register which is used to indicate the next available location in the
stack memory area. It serves as the effective address in stack addressing modes as well as subroutine and
interrupt processing.

REGISTER SECTION CONTROL SECTION

RESB IRQB NMIB

INTERRUPT INSTRUCTION STACK POINT REGISTER RDY

LOGIC DECODE (S)

SYNC

ADDRESS BUS ALU

A0-A15 MLB
INDEX REGISTER Y DATA BUS

TIMING
CONTROL
INDEX REGISTER X VPB

ACCUMULATOR A DATA BUS INSTRUCTION D0-D7

BUFFER REGISTER PHI2

PCL

PCH
PHI1O PHI2O SOB
CLOCK
GENERATOR/ OSCILLATOR RWB BE

INPUT DATA LATCH PROCESSOR

(DL) STATUS
REGISTER P

Figure 2-1 W65C02S Internal Architecture Simplified Block Diagram

7
15 1 A Accumulator A
7
PCH
0
Y Index Register Y
7
0

X Index Register X
7
0

PCL S Program Counter PC

7
0
0 Stack Pointer S
87

N V 1 B D I Z C Processor Status Register “P”

Carry 1 = True
Zero 1 = True
IRQB disable 1 = disable
Decimal mode 1 = true
BRK command 1 = BRK, 0 = IRQB

Overflow 1 = true
Negative 1 = neg

Figure 2-2 W65C02S Microprocessor Programming Model

3 PIN FUNCTION DESCRIPTION

3.1 Address Bus (A0-A15)
The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the
Data Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal.

3.2 Bus Enable (BE)

The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers. When
Bus Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers are set to
the high impedance status. Bus Enable is an asynchronous signal.

3.3 Data Bus (D0-D7)

The eight Data Bus lines D0-D7 are used to provide instructions, data and addresses to the microprocessor
and exchange data with memory and I/O registers. These lines may be set to the high impedance state by the
Bus Enable (BE) signal.

3.4 Interrupt Request (IRQB)

The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The
program counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I)
flag is set to a “1” disabling further interrupts before jumping to the interrupt handler. These values are used to
return the processor to its original state prior to the IRQB interrupt. The IRQB low level should be held until the
interrupt handler clears the interrupt request source. When Return from Interrupt (RTI) is executed the (I) flag is
restored and a new interrupt can be handled. If the (I) flag is cleared in an interrupt handler, nested interrupts
can occur. The Wait-for-Interrupt (WAI) instruction may be used to reduce power and synchronize with, as an
example timer interrupt requests.

3.5 Memory Lock (MLB)

The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in a
multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB is low.
Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
referencing instructions.

3.6 Non-Maskable Interrupt (NMIB)

A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence after the
current instruction is completed. Since NMIB is an edge-sensitive input, an interrupt will occur if there is a
negative transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further interrupts
will occur if NMIB remains low. The NMIB signal going low causes the Program Counter (PC) and Processor
Status Register information to be pushed onto the stack before jumping to the interrupt handler. These values
are used to return the processor to its original state prior to the NMIB interrupt.

3.7 No Connect (NC)

The No Connect (NC) pins are not connected internally and should not be connected externally.

3.8 Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O)

Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby
Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers since the
microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from PHI2. Phase 1 Out
(PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for driving PHI2 and used for the
main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems
for system timing and internal oscillators when an external crystal was used.

3.9 Read/Write (RWB)

The Read/Write (RWB) output signal is used to control data transfer. When in the high state, the
microprocessor is reading data from memory or I/O. When in the low state, the Data Bus contains valid data to
be written from the microprocessor and stored at the addressed memory or I/O location. The RWB signal is set
to the high impedance state when Bus Enable (BE) is low.

3.10 Ready (RDY)

A low input logic level on the Ready (RDY) will halt the microprocessor in its current state. Returning RDY to
the high state allows the microprocessor to continue operation following the next PHI2 negative transition. This
bi-directional signal allows the user to single-cycle the microprocessor on all cycles including write cycles. A
negative transition to the low state prior to the falling edge of PHI2 will halt the microprocessor with the output
address lines reflecting the current address being fetched. This assumes the processor setup time is met. This
condition will remain through a subsequent PHI2 in which the ready signal is low. This feature allows
microprocessor interfacing with low-speed memory as well as direct memory access (DMA). The WAI
instruction pulls RDY low signaling the WAit-for-Interrupt condition, thus RDY is a bi-directional pin. On the
W65C02 hard core there is a WAIT output signal that can be used in ASIC's thus removing the bi-directional
signal and RDY becomes only the input. In such a situation the WAI instruction will pull WAIT low and must be
used external of the core to pull RDY low or the processor will continue as if the WAI never happened. The
microprocessor will be released when RDY is high and a falling edge of PHI2 occurs. This again assumes the
processor control setup time is met. The RDY pin no longer has an active pull up. It is suggested that a pull up
resistor be used on this pin when not being used. The RDY pin can still be wire ORed.

3.11 Reset (RESB)

The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB signal
must be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect
while RESB is being held low. All Registers are initialized by software except the Decimal and Interrupt disable
mode select bits of the Processor Status Register (P) are initialized by hardware. When a positive edge is
detected, there will be a reset sequence lasting seven clock cycles. The program counter is loaded with the
reset vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control.
RESB should be held high after reset for normal operation.

Processor Status Register (P)

76543210
**1101**
NVBDIZC

*=software initialized

10

3.12 Set Overflow (SOB)

A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The
signal is sampled on the rising edge of PHI2. SOB was originally intended for fast input recognition because it
can be tested with a branch instruction; however, it is not recommended in new system design and was seldom
used in the past.

3.13 SYNChronize with OpCode fetch (SYNC)

The OpCode fetch cycle of the microprocessor instruction is indicated with SYNC high. The SYNC output is
provided to identify those cycles during which the microprocessor is fetching an OpCode. The SYNC line goes
high during the clock cycle of an OpCode fetch and stays high for the entire cycle. If the RDY line is pulled low
during the clock cycle in which SYNC went high, the processor will stop in its current state and will remain in
the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause
single instruction execution.

3.14 Power (VDD) and Ground (VSS)

VDD is the positive power supply voltage and VSS is system logic ground.
3.15 Vector Pull (VPB)

The Vector Pull (VPB) output indicates that a vector location is being addressed during an interrupt sequence.
VPB is low during the last interrupt sequence cycles, during which time the processor reads the interrupt
vector. The VPB signal may be used to select and prioritize interrupts from several sources by modifying the
vector addresses.

11

Table 3-1 Vector Locations

FFFE, F BRK/IRQB Software/Hardware

FFFC, D RESB Hardware

FFFA, B NMIB Hardware

Table 3-2 Pin Function Table

Pin Description

A0-A15 Address Bus

BE
Bus Enable
D0-D7
Data Bus
IRQB
MLB Interrupt Request
NC Memory Lock
 No Connection
NMIB
PHI1O Non-Maskable Interrupt
PHI2 Phase 1 Out Clock
PHI2O
Phase 2 In Clock
RDY
Phase 2 Out Clock
RESB
RWB Ready
SOB Reset
SYNC
Read/Write
VDD
VPB Set Overflow

VSS Synchronize

Positive Power Supply

Vector Pull

Internal Logic Ground

12

Figure 3-1 W65C02S 40 Pin PDIP Pinout

Figure 3-2 W65C02S 44 Pin PLCC Pinout

13

Figure 3-3 W65C02S 44 Pin QFP Pinout

 14

4 ADDRESSING MODES
The W65C02S is capable of directly addressing 65,536 bytes of memory. The Program Address and Data
Address space is contiguous throughout the 65,536 byte address space. Words, arrays, records, or any data
structures may span the 65,536 byte address space. The following addressing mode descriptions provide
additional detail as to how effective addresses are calculated. Sixteen addressing modes are available for the
W65C02S. This address space has special significance within certain addressing modes.

4.1 Absolute a

With Absolute addressing the second and third bytes of the instruction from the 16-bit address.

Byte:
ADH ADL OpCode
Instruction:

Operand Address:

4.2 Absolute Indexed Indirect (a,x) ADH ADL

2 1 0
With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third
byes of the instruction to form an address to a pointer. This address mode is only used with the JMP instruction
and the program Counter is loaded with the first and second bytes at this pointer.

Byte:
Instruction:

Indirect Base address: ADH ADL

Indirect address: X
New PC value:
effective address
4.3 Absolute Indexed with X a,x
indirect address
2 1 0

ADH ADL OpCode

+

With the Absolute Indexed with X addressing mode, the X Index Register is added to the second and third
bytes of the instruction to form the 16-bits of the effective address.

Byte: +
Instruction: Operand address:
2 1 0 ADH ADL

ADH ADL OpCode X

effective address

15
 4.4 Absolute Indexed with Y a, y

With the Absolute Indexed with Y addressing mode, the Y Index Register is added to the second and third
bytes of the instruction to form the 16-bit effective address.

Byte:
ADH ADL OpCode
Instruction:
2 1 0
+
Y
Operand address:

4.5 Absolute Indirect (a) effective address

ADH ADL
With the Absolute Indirect addressing mode, the second and third bytes of the instruction form an address to a
pointer. This address mode is only used with the JMP instruction and the Program Counter is loaded with the
first and second bytes at this pointer.

Byte:
Instruction:

Indirect address:

New PC value:

4.6 Accumulator A
2 1 0

ADH ADL OpCode

ADH ADL

indirect address
 With Accumulator addressing the operand is implied as the Accumulator and therefore only a single byte forms
the instruction.

Byte:
OpCode
Instruction:
2 1 0
Operand: accumulator

4.7 Immediate Addressing #

With Immediate Addressing the operand is the second byte of the instruction.

Byte:
Instruction: Operand:

2 1 0 Operand

Operand OpCode

16

4.8 Implied i

Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction.

Byte:
OpCode
Instruction:
2 1 0
Operand address: implied

4.9 Program Counter Relative r

The Program Counter relative addressing mode, sometimes referred to as Relative Addressing, is used with
the Branch instructions. If the condition being tested is met, the second byte of the instruction is added to the
Program Counter and program control is transferred to this new memory location.

Byte:
offset OpCode
Instruction:
2 1 0
+
offset
New PC value

4.10 Stack s effective address

PCH PCL
The Stack may use memory from 0100 to 01FF and the effective address of the Stack address mode will
always be within this range. Stack addressing refers to all instructions that push or pull data from the stack,
such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts and Return from Interrupt.

Byte:
2 1 0
Instruction:

Operand address:

4.11 Zero Page zp

 OpCode
1 S

With Zero Page (zp) addressing the second byte of the instruction is the address of the operand in page zero.

Byte:
Instruction:

Operand address:
2 1 0

zp OpCode

0 zp

17
 4.12 Zero Page Indexed Indirect (zp,x)
The Zero Page Indexed Indirect addressing mode is often referred to as Indirect,X. The second byte of the
instruction is the zero page address to which the X Index Register is added and the result points to the low byte
of the indirect address.

Byte:
Instruction:

Base Address: zp

Indirect Address: + X

Operand address: 0 address

4.13 Zero Page Indexed with X zp,x

2 1 0
indirect address
zp OpCode

With Zero Page Indexed with X addressing mode, the X Index Register is added to the second byte of
instruction to form the effective address.

Byte:
zp OpCode
Instruction:

Base Address:

Operand Address: zp

4.14 Zero Page Indexed with Y zp, y + X

2 1 0
0 effective address

With Zero Page Indexed with Y addressing, the second byte of the instruction is the zero page address to
which the Y Index Register is added to form the page zero effective address.

Byte:
zp OpCode
Instruction:

Base Address:

Operand Address: zp

4.15 Zero Page Indirect (zp) + Y

2 1 0
0 effective address

With Zero Page Indirect addressing mode, the second byte of the instruction is a zero page indirect address
that points to the low byte of a two byte effective address.

Byte: Indirect Address: Operand Address:

Instruction:
 2 1 0

zp OpCode
indirect address

0 zp 18

4.16 Zero Page Indirect Indexed with Y (zp), y

The Zero Page Indirect Indexed with Y addressing mode is often referred to as Indirect Y. The second byte of
the instruction points to the low byte of a two byte (16-bit) base address in page zero. Y Index Register is
added to the base address to form the effective address.

Byte:
Instruction:
0 zp
Indirect Base Address: Operand Address:

indirect base address

2 1 0
+ Y
zp OpCode
effective address

19

Table 4-1 Addressing Mode Table

Address Mode Instruction Times in
Memory Cycle

Original W65C02S Original

NMOS 6502 NMOS 6502

1. Absolute a 4 (3) 4 (3) 3

2. Absolute Indexed Indirect (a,x) - 6 -

3. Absolute Indexed with X a,x 4 (1,3) 4 (1,3) 3

4. Absolute Indexed with Y a,y 4 (1) 4 (1) 3

5. Absolute Indirect (a) 5 6 3

6. Accumulator A 2 2 1

7. Immediate # 2 2 2
 8. Implied i 2 2 1

9. Program Counter Relative r 2 (1,2) 2 (1,2) 1

10. Stack s 3-7 3-7 1

11. Zero Page zp 3 (3) 3 (3) 2

12. Zero Page Indexed Indirect (zp,x) 6 6 2

13. Zero Page Indexed with X zp,x 4 (3) 4 (3) 2

14. Zero Page Indexed with Y zp,y 4 4 2

15. Zero Page Indirect (zp) - 5 -

16. Zero Page Indirect Indexed with Y 5 (1) 5 (1) 2

(zp),y

Memory Utilization in Number of

Program Sequence Bytes

W65C02S

3
3
3
3
3
1
2
1
1
1
2
2
2
2
2
2

Notes: (indicated in parenthesis) –

1. Page boundary, add 1 cycle if page boundary is crossed when forming address. Add 1 cycle for STA abs,X
regardless of boundary crossing.
2. Branch taken, add 1 cycle if branch is taken
3. Read-Modify-Write, add 2 cycles
 20

5 OPERATION TABLES
Table 5-1 Instruction Set Table
2.
1. ADC ADd memory to accumulator with Carry 2 CPY ComPare memory and Y register
3.
2. AND "AND" memory with accumulator
2 DEC DECrement memory or accumulate by one
3. ASL Arithmetic Shift one bit Left, memory or 4.
accumulator
2 DEX DEcrement X by one
4. Branch on Bit Reset 5.
∙BBR
2 DEY DEcrement Y by one
5. Branch of Bit Set 6.
∙BBS

2 EOR "Exclusive OR" memory with accumulate

6. BCC Branch on Carry Clear (Pc=0) 7.

7. BCS Branch on Carry Set (Pc=1) 2 INC INCrement memory or accumulate by one
8.
8. BEQ Branch if EQual (Pz=1)
2 INX INcrement X register by one
9. BIT BIt Test 9.

1 BMI Branch if result MInus (Pn=1) 3 INY INcrement Y register by one

0. 0.

1 BNE Branch if Not Equal (Pz=0) 3 JMP JuMP to new location

1. 1.

1 BPL Branch if result PLus (Pn=0) 3 JSR Jump to new location Saving Return (Jump to
2. 2. SubRoutine)

1 BRanch Always 3 LDA LoaD Accumulator with memory

3.
∙BRA 3.

1 BRK BReaK instruction 3 LDX LoaD the X register with memory

4. 4.

1 BVC Branch on oVerflow Clear (Pv=0) 3 LDY LoaD the Y register with memory
5. 5.

1 BVS Branch on oVerflow Set (Pv=1) 3 LSR Logical Shift one bit Right memory or
6. 6. accumulator

1 CLC CLear Cary flag 3 NOP No OPeration

7. 7.

1 CLD CLear Decimal mode

8.

1 CLI CLear Interrupt disable bit 3 ORA "OR" memory with Accumulator
9. 8.

2 CLV CLear oVerflow flag 3 PHA PusH Accumulator on stack

0. 9.

2 CMP CoMPare memory and accumulator 4 PHP PusH Processor status on stack
1. 0.

2 CPX ComPare memory and X register

 4 PusH X register on stack 6 TSX Transfer the Stack pointer to the X register
1.
∙PHX 6.

4 PusH Y register on stack 6 TXA Transfer the X register to the Accumulator

2.
∙PHY 7.

4 PLA PuLl Accumulator from stack 6 TXS Transfer the X register to the Stack
3. 8. pointer register

4 PLP PuLl Processor status from stack 6 TYA Transfer Y register to the Accumulator
4. 9.

4 PuLl X register from stack 7 WAit for Interrupt

5.
∙PLX ∙WAI
0.

4 PuLl Y register from stack

6.
∙PLY

Note:∙= New Instruction

4 Reset Memory Bit
7.
∙RMB

4 ROL ROtate one bit Left memory or accumulator

8.

4 ROR ROtate one bit Right memory or accumulator

9.

5 RTI ReTurn from Interrupt

0.

5 RTS ReTurn from Subroutine

1.

5 SBC SuBtract memory from accumulator

2. with borrow (Carry bit)

5 SEC SEt Carry

3.

5 SED SEt Decimal mode

4.

5 SEI SEt Interrupt disable status

5.

5 Set Memory Bit

6.
∙SMB

5 STA STore Accumulator in memory

7.

5 SToP mode
8.
∙STP

5 STX STore the X register in memory

9.

6 STY STore the Y register in memory

0.

6 STore Zero in memory

1.
∙STZ

6 TAX Transfer the Accumulator to the X register

2.

6 TAY Transfer the Accumulator to the Y register

3.

6 Test and Reset memory Bit

4.
∙TRB

6 Test and Set memory Bit

5.
∙TSB
 21
Table 5-2 W65C02S OpCode Matrix
MSD W65C02S OpCode Matrix M
S
D

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 BRK ORA TSB ORA ASL RMB PHP ORA ASL TSB ORA ASL BBR 0
s (zp,x zp zp 0 s # A a a 0
zp ∙ a∙
)
zp ∙ r∙

1 BPL ORA ORA TRB ORA ASL RMB CLC ORA INC TRB ORA ASL BBR 1
r (zp), zp,x zp,x 1 i a,y a,x a,x 1
A*
(zp)
zp ∙ a∙
y
* zp ∙ r∙

2 JSR AND BIT AND ROL RMB PLP AND ROL BIT AND ROL BBR 2
a (zp,x zp zp zp 2 s # A a a a 2
)
zp ∙ r∙

3 BMI AND AND BIT AND ROL RMB SEC AND DEC BIT AND ROL BBR 3
r (zp), zp,x zp,x 3 I a,y a,x a,x 3
A* a,x *
(zp) zp,x
y
* * zp ∙ r∙

4 RTI EOR EOR LSR RMB PHA EOR LSR JMP EOR LSR BBR 4
s (zp,x zp zp 4 s # A a a a 4
)
zp ∙ r∙

5 BVC EOR EOR EOR LSR RMB CLI EOR PHY EOR LSR BBR 5
r (zp), (zp) zp,x zp,x 5 i a,y a,x a,x 5
s∙
y
* zp ∙ r∙

6 RTS ADC STZ ADC ROR RMB PLA ADC ROR JMP ADC ROR BBR 6
s (zp,x zp zp 6 s # A (a) a a 6
zp ∙
)
zp ∙ r∙

7 BVS ADC ADC STZ ADC ROR RMB SEI ADC PLY JMP ADC ROR BBR 7
r (zp), (zp) zp,x zp,x zp,x 7 i a,y (a.x) a,x a,x 7
s∙
y
* ∙ zp ∙ * r∙

8 BRA STA STY STA STX SMB DEY BIT TXA STY STA STX BBS 8
(zp,x zp zp zp 0 i i a a a 0
r∙ #*
)
zp ∙ r∙

9 BCC STA STA STY STA STX SMB TYA STA TXS STZ STA STZ BBS 9
r (zp), (zp) zp,x zp,x zp,y 1 i a,y i a,x 1
a∙ a,x ∙
y
* zp ∙ r∙

A LDY LDA LDX LDY LDA LDX SMB TAY LDA TAX LDY LDA LDX BBS A
# (zp,x # zp zp zp 2 i # i A a a 2
)
zp ∙ r∙

B BCS LDA LDA LDY LDA LDX SMB CLV LDA TSX LDY LDA LDX BBS B
r (zp), (zp) zp,x zp,x zp,y 3 i A,y i a,x a,x a,y 3
y
* zp ∙ r∙

C CPY CMP CPY CMP DEC SMB INY CMP DEX WAI CPY CMP DEC BBS C
# (zp,x zp zp zp 4 i # i a a a 4
I∙
)
zp ∙ r∙

D BNE CMP CMP CMP DEC SMB CLD CMP PHX STP CMP DEC BBS D
r (zp), (zp) zp,x zp,x 5 i a,y a,x a,x 5
s∙ I∙
y
* zp ∙ r∙
E CPX SBC CPX SBC INC SMB INX SBC NOP CPX SBC INC BBS E
# (zp,x zp zp zp 6 i # i a a a 6
)
zp ∙ r∙

F BEQ SBC SBC SBC INC SMB SED SBC PLX SBC INC BBS F
r (zp), (zp) zp,x zp,x 7 i a,y a,x a,x 7
s∙
y
* zp ∙ r∙

0 1 2 3 4 5 6 7 8 9 A B C D E F

* = Old instruction with new addressing modes

∙ = New Instruction

22
6 DC, AC AND TIMING CHARACTERISTICS

Table 6-1 Absolute Maximum Ratings

Rating Symbol Value

Supply Voltage VDD -0.3 to +7.0V

Input Voltage -0.3 to VDD
VIN
Storage Temperature +0.3V -55°C to
TS
+150°C

This device contains input protection against damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of voltages higher than the maximum rating.

Note: Exceeding these ratings may result in permanent damage. Functional operation under these conditions
is not implied.
 23
6.2 DC Characteristics TA = -40°C to +85°C (PLCC, QFP) TA= 0°C to 70°C (DIP)

Table 6-2 DC Characteristics

5.0 +/- 5% 3.3 +/- 10% 3.0 +/- 5% 2.5 +/- 5% 1.8 +/- 5% Unit
s

Min Max Min Max Min Max Min Max Min Max

Supply Voltage 4.75 5.25 3.0 3.6 2.85 3.15 2.37 2.63 1.71 1.89 V

Input High Voltage (1) VDDx0.7 VDD+0.3 VDDx0.7 VDD+0. VDDx0.7 VDD+0. VDDx0.7 VDD+0. VDDx0.7 VDD+0.3 V
BE, D0-D7, RDY, SOB VDD-0.4 VDD+0.3 VDD-0.4 3 VDD-0.4 3 VDD-0.4 3 VDD-0.4 VDD+0.3
IRQB, NMIB, PHI2, RESB VDD+0. VDD+0. VDD+0.
3 3 3

Input Low Voltage (1) VSS-0.3 VDDx0.3 VSS-0.3 VDDx0. VSS-0.3 VDDx0.3 VSS-0.3 VDDx0.3 VSS-0.3 VDDx0.3 V
BE, D0-D7, RDY, SOB, VSS-0.3 VSS+0.4 VSS-0.3 3 VSS-0.3 VSS+0.4 VSS-0.3 VSS+0.4 VSS-0.3 VSS+0.1
IRQB, NMIB, PHI2, RESB VSS+0.4

Input Leakage Current (Vin=0.4 to 2.4, -20 20 -20 20 -20 20 -20 20 -20 20 nA
VDD=max)
BE, IRQB, NMIB, PHI2, RESB, SOB, RDY

D0-D7 (off state) -20 20 -20 20 -20 20 -20 20 -20 20 nA

Output High current (Voh=VDD-.4, VDD=min) 700 - 350 - 300 - 200 - 100 - uA
A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB,
SYNC, VPB

Output Low current (Vol=0.4, VDD=min) A0- 1.6 - 1.6 - 1.6 - 1.0 - 0.5 - mA
A15, D0-D7, MLB, PHI1O, PHI2O, RDY, RWB,
SYNC, VPB

Supply Current (with Tester Loading) - 1.5 - 1.0 - 1.0 - 0.75 - 0.5 mA/
Supply Current (Core) - 0.5 - 0.3 - 0.25 - 0.2 - 0.15 MHz

Standby Current Outputs Unloaded - 1 - 1 - 1 - 1 - 1 uA

BE, IRQB, NMIB, PHI2, SOB=VDD

*Capacitance (Vin=0V, TA=25°C, f-1MHz) - 5 - 5 - 5 - 5 - 5 pF

BE, IRQB, NMIB, PHI2, RESB, RDY,
SOB A0-A15, D0-D7, RWB
*Not inspected during production test; verified on a
sample basis.

Symbol

VDD

Vih

Vil

in

Iin

Ioh

Iol

Idd

Isby

Cin
Cts

(1) For high speed tests, Vih and Vil are set for VDD-.2v and VSS+.2V. The input “1” and “0” thresholds are tested at 1 MHz.
(mA) IDD Typical 0.6u processed device (Core power + + (VOLTS) VDD + +
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5
only) + +
0.1 1.0 0.5 +
(With tester loading) +
1MHz Operation@85°C
Typical 0.6µ processed device @85°C
+

0.0
0.0
0123456
Figure 6-1 Idd vs Vdd
Figure 6-2 F Max vs Vdd
VDD (VOLTS)
048
2 6 10 12 14 16 18 20 F Max (MHz)

24
6.3 AC Characteristics TA = -40°C to +85°C (PLCC, QFP) TA= 0°C to 70°C (DIP)

Table 6-3 AC Characteristics

Symbol Parameter 5.0 +/-5% 3.3 +/-10% 3.0 +/-5% 2.5 +/-5% 1.8 +/-5% Units

14MHz 8MHz 8MHz 4MHz 2MHz

Min Max Min Max Min Max Min Max Min Max

VDD Supply Voltage 4.75 5.25 3.0 3.6 2.85 3.15 2.37 2.675 1.7 1.89 V
5 1

tACC Access Time 30 - 70 - 70 - 145 - 290 - nS

tAH Address Hold Time 10 - 10 - 10 - 10 - 10 - nS

tADS Address Setup Time - 30 - 40 - 40 - 75 - 150 nS

tBVD BE to Valid Data (1) - 25 - 30 - 30 - 30 - 30 nS

CEXT Capacitive Load (2) - 35 - 35 - 35 - 35 - 35 pF

tPWH Clock Pulse Width High 35 - 62 - 62 - 125 - 250 - nS

tPWL Clock Pulse Width Low 35 - 63 - 63 - 125 - 250 - nS

tCYC Cycle Time (3) 70 - 125 - 125 - 250 - 500 - nS

tF,tR Fall Time, Rise Time - 5 - 5 - 5 - 5 - 5 nS

tPCH Processor Control Hold 10 - 10 - 10 - 10 - 10 - nS

Time

tPCS Processor Control Setup 10 - 15 - 15 - 30 - 60 - nS

Time

tDHR Read Data Hold Time 10 - 10 - 10 - 10 - 10 - nS

tDSR Read Data Setup Time 10 - 15 - 15 - 30 - 60 - nS

tMDS Write Data Delay Time - 25 - 40 - 40 - 70 - 140 nS

tDHW Write Data Hold Time 10 - 10 - 10 - 10 - 10 - nS

1. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data
2. ATE or loading on all outputs
3. Since this is a static design, the maximum cycle time could be infinite.
 25

PHI2 tPWH
tAH
tPWL See note 1

tAH
A0-A15, MLB,
R/W, SYNC, VPB
tR
tF

READ DATA tDHR tDHR

tADS tACC tDSR tMDS

WRITE DATA tPC WRITE DATA

SOB tDHW tDHW S

IRQB, NMIB,
RDY, RESB
tPCH tPCH

BE
tPCS

DATA

tBV
D

Figure 6-3 General Timing Diagram

Timing Notes:

1. Timing measurement points are 50% VDD.

2. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for
system time base and PHI2 processor input clock.

26
Table 6-4 Operation, Operation Codes and Status Register
 Operation a A # i r s Processor Status Register (P)
Mn # Immediate Data (a, a, a, (a z (z z z (z (z *User Defined
~ NOT x y ) p
em x) p, p, p, p) p)
→ AND x y
omi v OR x) ,y
76543210
c v Exclusive OR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NV11DIZC

ADC A+M+C→A 6D 7D 79 0A 69 65 61 75 72 71 NV....ZCN.....Z.N.....ZC

AND 2D 3D 39 29 25 21 35 32 31
A^M→A
ASL 0E 1E 06 16

C←7 6 5 4 3 2 1 0 ←0

BBR0 Branch on bit 0 0F ........................

BBR1 reset Branch on 1F
BBR2 bit 1 reset 2F
Branch on bit 2

reset

BBR3 Branch on bit 3 3F ........................

BBR4 reset Branch on 4F
BBR5 bit 4 reset 5F
Branch on bit 5

reset

BBR6 Branch on bit 6 6F ........................

BBR7 reset Branch on 7F
BBS0 bit 7 reset 8F
Branch on bit 0

set

BBS1 Branch on bit 1 set 9F .......................

BBS2 Branch on bit 2 set AF
BBS3 Branch on bit 3 set BF

BBS4 Branch on bit 4 set CF ........................

BBS5 Branch on bit 5 set DF
BBS6 Branch on bit 6 set EF

BBS7 Branch on bit 7 set FF ........................

BCC Branch C = 0 90
BCS Branch if C=1 B0

BEQ Branch if Z=1 2C 3C 89 F0 24 34 . . . . . . . . M 7 M6 . . . Z . . . . . . . . .

BIT A^M

BMI Branch if N=0 30

BN Branch if Z=0 D0 ................

E
Branch if N=0 10
BPL
Branch Always 80
BRA

BRK Break 50 00 ...101..................

BVC Branch if V=0 70
BV Branch if V=1
S

CL C→0 18 .......0....0........0..
C
D8
CL 0→D
D 58

CLI 0→1

CLV 0→V CD DD D9 C9 B8 C5 C1 D5 D2 D1 .0......N.....ZCN.....ZC

CMP EC E0 E4
A-M
CP
X X-M
 CP Y-M CC DE 3A C0 CA C4 D6 N.....ZCN.....Z.N.....Z.
Y
Decrement CE C6
DEC
X-1 → X
DE
X

DE Y-1 → Y 4D 5D 59 1A 49 88 45 41 55 52 51 N.....Z.N.....Z.N.....Z.
Y
EE FE E6 F6
EOR AvM→A

INC Increments

INX X+1 → X 4C 7C 6C E8 N.....Z.N.....Z.........

INY C8
Y+1 → Y
JMP
Jump to new location

27
Operation a A # i r s Processor Status Register (P)
Mn # Immediate Data (a,x a,x a, (a z (z zp, zp, (zp (zp *User Defined
em ~ NOT ) y ) p x y )
^ AND p, ),y
om v OR x)
xv Exclusive OR
ic

76543210

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NV11DIZC

JS Jump to Subroutine 20 BD B9 A9 A5 A1 B5 B6 B2 B1 N.....Z.N.....Z.N.....Z.

R
M→A AD BE A2 A6
LDA
AE
LDX M→X

M→Y
LDY AC BC 4A A0 EA A4 B4 N.....Z.0.....ZC........
LSR 4E 5E 46 56
0→76543210
NOP

→ C No Operation

AVM→A
ORA 0D 1D 19 09 48 05 01 15 12 11 N.....Z.................
PHA 08
A → Ms, S-1 → S
PHP

P → Ms, S-1 → S

X → Ms, S-1 → S
PHX DA ................N.....Z.
PHY 5A
Y → Ms, S-1 → S
PLA 68

S + 1→S, Ms → A

S + 1→S, Ms → P
PLP 28 NV.1DIZCN.....Z.N.....
PLX FA Z.
S + 1→S, Ms → X
PLY 7A

S + 1→S, Ms → Y

RMB0 Reset Memory Bit 0 07 ........................

RMB1 Reset Memory Bit 1 17

RMB2 Reset Memory Bit 2 27

RMB3 Reset Memory Bit 3 37 ........................

RMB4 Reset Memory Bit 4 47

RMB5 Reset Memory Bit 5 57

RMB6 Reset Memory Bit 6 2E 3E 2A 67 36 ...............N.....ZC

RMB7 Reset Memory Bit 7 77

ROL
C←7 6 5 4 3 2 1 0 ← C 26

ROR 6E 7E 6A 40 66 76 N . . . . . Z C N V . 1. D I Z
C→7 6 5 4 3 2 1 0
RTI 60 C........
 → C Return from
RTS

Interrupt

Return from Subroutine

A - M - (~C) → A
SBC ED FD F9 E9 38 E5 E1 F5 F2 F1 NV....ZC.......1....1...
SEC F8
1→C
SED

1→D

1→I
SEI 78 .....1..

SMB0 Set Memory Bit 0 87 ........

SMB1 Set Memory Bit 1 97 ........

SMB2 Set Memory Bit 2 A7 ........

SMB3 Set Memory Bit 3 B7 ........

SMB4 Set Memory Bit 4 C7 ........

SMB5 Set Memory Bit 5 D7 ........

SMB6 Set Memory Bit 6 E7 ........

SMB7 Set Memory Bit 7 F7 ........

A→M
STA 8D 9D 99 85 81 95 92 91 ........

ST DB ........
STOP (1→ PHI2)
P

X→M
ST 8E 86 96 ........
X

28
Operation a A # i r s Processor Status Register (P)
Mn # Immediate (a, a,x a, (a z (z zp, zp, (zp (zp *User Defined
Data ~ NOT y ) p x y )
em x) p, ),y
^ AND
om v OR x)
xv Exclusive OR
ic
76543210

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NV11DIZC

Y →M
STY 8C 9E AA 84 94 ................N.....Z.
STZ 9C 64 74
00 → M
TAX

A→X

M→X
TAY 1C A8 14 N . . . . . Z . . . . . . . Z . . . . . . . Z. .
TRB 0C 04
~A∧M → M
TSB

AVM→M

S→X
TSX BA N . . . . . Z . N . . . . . Z. . . . . . . . . .
TXA 8A
X→A
TXS 9A

X→S

Y→A
TYA 98 N.....Z.........

WAI CB
0 → RDY

29
7 CAVEATS
 Table 7-1 Microprocessor Operational Enhancements
Function NMOS 6502 W65C02S

Indexed addressing across page Extra read of invalid address. Extra read of last instruction byte.
boundary

Execution of invalid OpCodes. Some terminate only by reset. All are NOP's (reserved for future
Results are undefined. use). OpCode Bytes Cycles
02,22,42,62,82 2 2
C2, E2
X3,OB-BB,EB,FB 1 1
44 2 3 54,D4,F4 2 4 5C 3 8 DC,FC 3
4

Jump indirect, operand = XXFF. Page address does not increment. Page address increments, one additional
cycle.

Read/Modify/Write instruction at One read and two write cycles. Two read and one write cycle.
effective address.

Decimal flag. Indeterminate after reset. Initialized to binary mode (D=0) after
reset and interrupts.

Flags after decimal operation. Invalid N, V and Z flags. Valid flags. One additional cycle.

Interrupt after fetch of BRK Interrupt vector is loaded; BRK BRK is executed, and then interrupt is
instruction vector is ignored. executed.

Ready. Input. Bi-directional, WAI instruction pulls low.

Latest TSMC devices no longer have an
internal pull up. An external pullup should
be used if RDY is not driven and a
resistor added when driven by a gate to
allow for the W65C02S to pull RDY low.

Read/Modify/Write instructions Seven cycles. Six cycles.

absolute indexed in same page.

Oscillator. Requires external active Crystal or RC network will oscillate when

components. connected between PHI2 and PHI10.

Assertion of Ready (RDY) during Ignored. Stops processor during PHI2, and WAI
write operations. instruction pulls RDY low.

Clock inputs. PHI2 is the only required clock. PHI2 is the only required clock.

Unused input-only pins and RDY. Must be tied to VDD. Must be tied to VDD.

The BRK instruction for both the NMOS 6502 and 65C02 is a 2 byte instruction. The NMOS and CMOS
devices simply skips the second byte (i.e. doesn’t care about the second byte) by incrementing the program
counter twice. It is important to realize that if a return from interrupt is used it will return to the location after the
second or signature byte.

30
8 HARD CORE MODEL
8.1 Features of the W65C02S Hard Core Model

∙ The W65C02S core uses the same instruction set as the W65C02S.

∙ The only functional difference between the W65C02S and W65C02S core is the RDY pin. The W65C02S
RDY pin is bi-directional. The W65C02S core RDY function is split into 3 pins, RDY, WAITN and WAITP.
The WAITN output goes low and WAITP goes high when a WAI instruction is executed.
 ∙ The ESD and latch-up buffers have been removed.

∙ The output from the core is the buffer N-channel and the P-channel transistor drivers. ∙ The following

inputs, if not used, must be pulled to the high state: RDY, IRQB, NMIB, BE and SOB. ∙ The timing of the
W65C02S core is the same as the W65C02S.

9 SOFT CORE RTL MODEL

9.1 W65C02 Synthesizable RTL-Code in Verilog HDL

The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model is
equivalent to the original W65C02S hardcore. The W65C02 RTL-Code is available as the core model and the
W65C02S standard chip model. The standard chip model includes the soft-core and the buffer ring in RTL-
Code.

31
10 ORDERING INFORMATION RoHS/Green Compliance
G = RoHS/Green Compliant (Wafer and Packaging)
Example: W65C02S6TPLG-14 Temperature/Processing
Description
Blank = -40°C to + 85°C (PLCC and QFP) 0°C to 70°C (DIP) Speed
W65C = standard product
Designator
Product Identification Number
-14 = 14MHz
Foundry Process W65C
6=.6u 1P/2M CMOS Process
T= TSMC Foundry
Package 02S

P = Plastic Dual-In-Line, 40 pins

PL = Plastic Leaded Chip Carrier, 44 pins
Q = Quad Flat Pack, 44 pins
 6T G

PL

-14

____________________________________________________________________________________ To
receive general sales or technical support on standard product or information about our module library
licenses, contact us at:

The Western Design Center, Inc.

2166 East Brown Road
Mesa, Arizona 85213 USA
Phone: 480-962-4545 Fax: 480-835-6442
[email protected]
www.WDC65xx.com
www.WesternDesignCenter.com

_______________________________________________________________________________________

WARNING: MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE

Internal static discharge circuits are provided to minimize part damage due to environmental static electrical
charge build-ups. Industry established recommendations for handling MOS circuits include:

1. Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product
in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at
conductive work stations.
3. Ground all assembly and repair tools.

32