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Synthesis

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Md. Mahadi Hasan Bhuiyan
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37 views3 pages

Synthesis

Uploaded by

Md. Mahadi Hasan Bhuiyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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########################################################################

## to get this script up


and running, enter the command ##
## >> dc_shell
##
## after it appears
##
## >> source <name of
the script> ##
##
##

########################################################################

########## clear the dc memory of any designs


remove_design -all

########## Setup the search path, target library and link library to the standard
cell locations
set_app_var search_path "$search_path
/home/mb211102/work/synthesis/spi_synthesis/rtl/"
set_app_var target_library
"/pnr/pnr/training_materials/libraries/stdlib/rev_1.0/lib/tcbn45gsbwplvtwcl.db"
set_app_var link_library "* $target_library"

########## Analyze the HDL files


analyze -format sverilog {../rtl/} -autoread

########## elaborating the top automatically sets the top module as the current
design --> allows for parameter overrides
elaborate spi_top

############## set the operating conditions


set_operating_conditions WCLCOM -library tcbn45gsbwplvtwcl
#set_operating_conditions LTCOM -library tcbn45gsbwplvtlt

########## save the unmapped ddc (optional)


##write_file -f ddc -hier -output ../db/spi_top.ddc

########### link to check for any unresolved designs


link

########### apply if you dont want the synthesis tool to not optimize any
particular block
##set_dont_touch u_spi_tx_rx_ctrl/u_rx_control/rx_stat_reg_data*

############# add buffers to outputs that go to multiple output ports


#set_fix_multiple_port_nets -all
#set_fix_multiple_port_nets -outputs
#set_fix_multiple_port_nets -buffer_constants
############## apply the constraints on the design by reading in the sdc file
read_sdc ../sdc/spi_constraints.sdc

############## compile the design


compile
# <-- this uses the medium map effort and is enough for basic synthesis
#--> use the following for more harsher timing constraints:
#compile -map_effort high
#-boundary_optimization

############### remove any sort of unconnected ports that have not been used...
##remove_unconnected_ports -blast_buses [find -hierarchy cell {"*"}]

############## to generate netlist of the entire hierarchy:


write -hierarchy -format verilog -output
/home/mb211102/work/synthesis/spi_synthesis/spi_netlist.v

############## report generation


#report_area -hierarchy >
/home/mb211102/work/synthesis/spi_synthesis/report/spi.area
#report_timing -max_paths 10 -from [all_inputs] -to [all_registers -data_pins] -
significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/spi_timing_in2reg.timing
#report_timing -max_paths 10 -from [all_registers -data_pins] -to [all_registers -
data_pins] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/spi_timing_reg2reg.timing
#report_timing -max_paths 10 -from [all_registers -data_pins] -to [all_outputs] -
significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/spi_timing_reg2out.timing
#report_cell > /home/mb211102/work/synthesis/spi_synthesis/report/spi.cell

report_area -hierarchy >


/home/mb211102/work/synthesis/spi_synthesis/report/spi.area

report_timing -max_paths 10 -delay_type max -from [all_inputs] -to [all_registers -


data_pins] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/in2reg_setup.timing
report_timing -max_paths 10 -delay_type min -from [all_inputs] -to [all_registers -
data_pins] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/in2reg_hold.timing
report_timing -max_paths 10 -delay_type min -from [all_registers -data_pins] -to
[all_registers -data_pins] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/reg2reg_hold.timing
report_timing -max_paths 10 -delay_type max -from [all_registers -data_pins] -to
[all_registers -data_pins] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/reg2reg_setup.timing
report_timing -max_paths 10 -delay_type min -from [all_registers -data_pins] -to
[all_outputs] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/reg2out_hold.timing
report_timing -max_paths 10 -delay_type max -from [all_registers -data_pins] -to
[all_outputs] -significant_digits 5 >
/home/mb211102/work/synthesis/spi_synthesis/report/reg2out_setup.timing
report_cell > /home/mb211102/work/synthesis/spi_synthesis/report/spi.cell
############## show in gui mode
gui_start

########################################################################
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##
##
##
##
END OF SCRIPT ##
##
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##

########################################################################

################# some other stuff


##set_load -max [expr {800.0/1000}] $INPTS
#set_driving_cell -max -lib_cell INVD0BWPLVT $INPTS
#set_max_capacitance [expr {800.0/1000}] $INPTS

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