III Sem(2020-21)

Fundamental of Digital Logic

and Computer Architecture
(CST251)

Mr. P.R. Pardhi|Assistant Professor

Computer Science and Engineering| RCOEM,Nagpur
UNIT 2 : Combinational Circuits

 Objectives
 To study Adder(Half,Full),Subtractor(Half,Full).
 To study Ripple and carry look-ahead adder.
 To study Encoder and Decoder.
 To study Multiplexor and Demultiplexor
 Half Adder

 Half adder is a combinational logic circuit with two

inputs and two outputs.
 It is a basic building block for addition of two single
bit numbers.`
A Sum

Inputs Half Outputs

Adder
B Carry
Half Adder

Truth Table for Half Adder

Input Output

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Half Adder
K-map for Sum Output:
A
A A
B 0 1
S  AB  AB
0 0 1
B
S  A B
B 1 1 0

K-map for Carry Output:

A
A A
B 0 1

B 0 0 0 C  AB

B 1 0 1
Half Adder

Logic Diagram:

A
S  A B
B

C  AB
Half Adder
Logic Diagram using Basic Gates:

A B

S  A B

C  AB
 Full Adder

Full adder is a combinational logic circuit with

three inputs and two outputs.

A Sum

Inputs B Full Outputs

Adder
Carry

Cin
Full Adder
Truth Table

Inputs Outputs
A B Cin Sum (S) Carry (C)
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
Full Adder
K-map for Sum Output:

BC BC BC BC BC
00 01 11 10
A S  ABC  ABC  ABC  ABC
0 1 0 1
A 0 S  ABC  ABC  ABC  ABC
A 1 1 0 1 0 S  C( AB  AB)  C( AB  AB)
Let AB  AB  X
ABC
ABC ABC
ABC  S  C( X )  C( X )
S  C X
Let X  A B
S  C  A B
Full Adder

K-map for Carry Output:

BC BC BC BC BC
A 00 01 11 10

0 0 1 0
A 0
C  AB  BC  AC
A 1 0 1 1 1

BC
AB
AC
Full Adder
Logic Diagram:

A B C

S  A B  C

C  AB  BC  AC
Full Adder using Half Adders

A S0 S1 Sum
HA1 HA2
B C0 C1

C
Carry
Full Adder using Half Adders
 Sum = A ⊕ B ⊕ Cin
 Cout = AB + (A ⊕ B). Cin
= AB + ( A’. B + A. B’). Cin
= AB + A’. B Cin + A. B’. Cin
= B (A + A’. Cin) + A. B’. Cin
= B(A+Cin)+A.B’.Cin
= AB+BCin+A.B’Cin
=AB+(B+A.B’)Cin
=AB+(A+B)Cin
=AB+ACin+BCin
 Half Subtractor
Half subtractor is a combinational logic circuit
with two inputs and two outputs.

It is a basic building block for subtraction of two

single bit numbers.

A Difference

Inputs Half Outputs

Subtractor
B Borrow
Half Subtractor
Truth Table

Input Output

A B Difference (D) Borrow (B)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Half Subtractor
K-map for Difference Output:
A
A A
B 0 1
D  AB  AB
0 0 1
B
D  A B
B 1 1 0

K-map for Borrow Output:

B
B B
A 0 1

0 1
A 0 B  AB
A 1 0 0
Half Subtractor
Logic Diagram:

A
D  A B
B

B  AB
Half Subtractor
Logic Diagram using Basic Gates:

A B

D  A B

B  AB
 Full Subtractor

Full subtractor is a combinational logic circuit

with three inputs and two outputs.

A Difference

Inputs B Full Outputs

Subtractor
Borrow

Bin
Full Subtractor
Truth Table

Inputs Outputs
A B Bin (C) Difference (D) Borrow (B0)
0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
Full Subtractor
K-map for Difference Output:

BC BC BC BC BC
00 01 11 10
A D  ABC  ABC  ABC  ABC
0 1 0 1
A 0 D  ABC  ABC  ABC  ABC
A 1 1 0 1 0 D  C( AB  AB)  C( AB  AB)
Let AB  AB  X
ABC
ABC ABC
ABC  D  C( X )  C( X )
DCX
Let X  A B
D  C  A B
Full Subtractor

K-map for Borrow Output:

BC BC BC BC BC
A 00 01 11 10

0 1 1 1
A 0
B 0  AB  BC  AC
A 1 0 0 1 0
Full Subtractor
Logic Diagram:
A B C

D  A B  C

B 0  A B  B C  AC
N – Bit Parallel Adder

 The full adder is capable of adding two single digit binary

numbers along with a carry input.

 But in practice we need to add binary numbers which are much

longer than one bit.

 To add two n-bit binary numbers we need to use the n-bit parallel
adder.

 It uses a number of full adders in cascade.

 The carry output of the previous full adder is connected to the
carry input of the next full adder.
 N – Bit Parallel Adder

An  1 Bn  1 A2 B2 A1 B1 A0 B0

FA-(n-1) FA-2 FA-1 FA-0

C0 C in

Sn  1 S2 S1 S0
4 – Bit Parallel Adder
 A3A2A1A0=1101
 B3B2B1B0=0101

A0 B0 Cin = S0 Cout
1 + 1 + 0 = 0 1 LSB
A1 B1 Cin = S1 Cout
0 +0 + 1 = 1 0
A2 B2 Cin = S2 Cout
1 +1 + 0 = 0 1
A3 B3 Cin = S3 Cout
1 + 0 + 1 = 0 1 MSB

S4
 4 – Bit Binary Parallel Adder

A3 B3 A2 B2 A1 B1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 C in

S3 S2 S1 S0
 4 – Bit Binary Parallel Adder

A Binary number B Binary number

A 3 A 2 A1 A 0 B 3 B 2 B1 B 0

IC 7483 Cin
C0
Carry
Carry
Input
Output

S3 S 2 S1 S0
Sum Output
Carry Look Ahead Adder
 A look ahead carry adder is fast adder which
improves speed by reducing the amount of time
required to determine carry bits. It reduces the time
which are delayed at each stage.
Carry Look Ahead Adder
EXPRESSION FOR CARRY GENERATION AND
PROPOGATION

 Gi = Ai. Bi(Carry Generation)

 Pi = Ai ⊕ Bi(Carry Propagation)

 Using the Gi and Pi terms the Sum Si and Carry Ci+1 are
given as below –
Si = Pi ⊕ Ci
Ci+1 = Ci.Pi +Gi
 Therefore, the carry bits C1, C2, C3, and C4 can be
calculated as
C1 = C0.P0+G0.
C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1.
C3 = C2.P2+G2 = (C1.P1+G1).P2+G2.
C4 = C3.P3+G3 = C0.P0.P1.P2.P3 + P3.P2.P1.G0 +
P3.P2.G1 + G2.P3 + G3.
4-bit Carry look ahead adder
Page 35
Design of 1 Digit BCD Adder
As we know BCD addition rules, we understand that the 4 bit BCD adder should
consists of following:

 A 4 bit binary adder to add the given two (4 bit

numbers).

 A combinational logic circuit to check if sum is greater than 9 or carry 1.

 One more 4 bit binary adder to add 0110 to the invalid BCD sum or if carry is
1

8=1000

4=0100

1100

0110 Add6

10010
Design of 1 Digit BCD Adder
Logic Table for design of Logic circuit:

Inputs Y Inputs Y
S3 S2 S1 S0 S3 S2 S1 S0
0 0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 1
0 0 1 1 0 1 0 1 1 1 Sum is
invalid
0 1 0 0 0 1 1 0 0 1 BCD
Number
0 1 0 1 0 1 1 0 1 1 Y=1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 1 1 1 1
Design of 1 Digit BCD Adder

K-map for Logic circuit:

S1S0 S1S0 S1S0 S1S0 S1S0

S3s2 00 01 11 10
0 1 3 2
S3S2 00 0 0 0 0
4 5 7 6
S3S2 01 0 0 0 0
12 13 15 14 Y  S 3S 2  S 3S1
S3S2 11 1 1 1 1
8 9 11 10
S3S2 10 0 0 1 1

S3S2 S1S3
Design of 1 Digit BCD Adder
A BCD no. B BCD no.

Combinational
Logic Circuit
C0 IC 7483-I
S 3 S 2 S1 S 0 C in

Y' Y

C0
IC 7483-II
Not used C in
S3 S 2 S1 S0

Carry output
BCD Output Sum
BCD Substraction Using 9’S Complement

 Take 9’S complement of subtrahend.

 Add it to the minuend using BCD addition.
 If the result is invalid BCD then correct by adding 6.
 Shift carry to next bit.
 If end around carry generated then add it to the
result.
BCD Substraction Using 9’S Complement
9’S complement Circuit
BCD Substraction Using 10’S Complement

 Take 10’S complement of subtrahend.

 Add it to the minuend using BCD addition.
 If the result is invalid BCD then correct by adding 6.
 Shift carry to next bit.
 If end around carry generated then discard it. If carry
is not generated then result is negative and consider
10’S complement of result to get actual value.
BCD Substraction Using 10’S Complement
10’S complement Circuit
 Decoder
 A decoder is a combinational circuit that convert
binary information from n input lines to maximum
2𝑛 unique output line.
 If n-bit decoded information has unused or don’t
care combinations , the decoder output will have
less than 2𝑛 output.

‘n’ ‘2n’
. decoder .
inputs . .
outputs
. .
 2 to 4 Line Decoder

Y0
A
2:4 Y1
Inputs Block Diagram
B Decoder Y2
Y3
Enable
E Enable Data Outputs
i/p
Input Inputs

E A B D0 D1 D2 D3

0 X X 0 0 0 0
Truth Table
1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1
2 to 4 Line Decoder

B
E A
A B

D0

D1

D2

D3
3 to 8 Line Decoder

D0
Block Diagram A D1
Input D2
B D3
3:8
D4
Decoder
C D5
D6
D7

Enable
Input
3 to 8 Line Decoder
Truth Table

Enabl
Inputs Outputs
e i/p
E A B C D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0
0
 D0=A’B’C’
 D1=A’B’C
 D2=A’BC’
 D3=A’BC
 D4=AB’C’
 D5=AB’C
 D6=ABC’
 D7=ABC
Combinational Logic Implementation

Implement a full adder circuit with a decoder and two

OR gates.
S(X,YZ)= 1,2,4,7 C(X,Y,Z)= (3,5,6,7)
 5:32 line decoder with four 3:8 decoder with
enable and 2:4 line decoder.
 Encoder

 Encoder is a combinational circuit which is designed

to perform the inverse operation of decoder.
 An encoder has 2𝑛 (or less) input lines and n output
lines. The output lines generated the binary code for
2𝑛 variable.

“2𝑛 or . .
‘n’
Encoder outputs
less” . .
inputs . .
Decimal to BCD Encoder

Y0 = D1 + D3 + D5 + D7 + D9
Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Y3 = D8 + D9
Continue..
Octal to Binary Encoder

Y0 = D1 + D3 + D5 + D7
Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Continue…
Priority Encoder

 A standard digital encoder has one limitation that it would

produce an error at its output if more than one input is active
at a given time.
 It generates an undefined combination of outputs, if the two
inputs are logic 1 simultaneously.
 To overcome this problem, encoder circuit must establish a
priority such that only one input is encoded at such cases.
 This means that whenever two inputs are equal to logic 1
simultaneously, then the encoder must priorities the level of
each input such that it produce output corresponds to highest
priority input. Such an encoder is called as priority encoder.
Continue…
 A priority encoder is one of the types of encoders
in which an ordering is imposed to the inputs that
means compared with the standard encoder, it
includes the priority function.
 This priority is based on the relative magnitudes of
the inputs. Hence, the input with larger magnitude is
the one that is encoded first.
 Priority encoders can select the inputs with highest
priority in many practical applications. This process
of selection is called arbitration.
4-Input Priority Encoder
 This Priority encoder consists of 4 inputs and three outputs.
Although an encoder has 2n inputs and n outputs, it has a
third output ‘V’ which is a valid bit indicator and is set to one
when one or more inputs are active or equal to 1.
 This valid bit is zero when all the inputs are zero which
indicates that there is no valid input. On this condition, other
outputs are considered as don’t care conditions and are not
inspected when V is zero.
 D3 has the highest priority and D0 has lowest priority. When
D3 is active or 1, then regardless of other inputs, the output
is 11.
 when D3 is 0 and D2 is 1 then regardless of other two
inputs (which has lower priority), the output is 10.
Decimal- to- BCD Priority Encoder.
 This type of encoder performs the same operation as
that of a normal decimal to BCD encoder as encoding
the decimal digits into 4-bit BCD outputs. However, it
consists of an additional functionality of providing
priority. That means the BCD output is produced
corresponding to the highest priority of a decimal digit
appearing on the inputs irrespective of all other inputs.
 This encoder has nine active low inputs representing the
decimal digits from 1 to 9. According to the highest
order activated input, it produces the inverted BCD
code.
 When all the inputs from D1 to D9 are logic 1, all the
outputs are set to 1111 which is the inverse of 0000, i.e.,
BCD code for 0.
 When D9 is 1, the output is 0110, which is the inverse of
1001, i.e., BCD code for 9.
 The outputs are normally high when none of the input is
activated and this case corresponds to the decimal 0 inputs.
Thus, when all the inputs are high, the encoder assumes the
decimal 0 state as there is no D0 input.
 If the two inputs are activated at the same time, suppose D3
and D5 then the highest priority of these inputs, i.e., D5 is
encoded as 1010 which is the inverse of 0101, that’s how
this encoder is called as priority encoder.
Decimal to BCD Priority Encoder

 Y0 =D1D2’D4’D6’D8’+D3D4’D6’D8’+D5D6’D8’+D7D8’+D9
 Y1 =D2D4’D5’D8’D9’+D2D4’D5’D8’D9’+D3D4’D5’D8’D9’+D
6D8’D9’+D7D8’D9’

 Y2 = D4D8’D9’+D5’D8’D9’+D6D8’D9’+D7D8’D9’
 Y3 = D8 + D9
8 to 3 Priority Encoder or Octal to Binary
Priority Encoder
 Design priority encoder for the following priorities
1)D1>D0>D2>D3
D1 D0 D2 D3 X Y V
0 0 0 0 X X 0
0 0 0 1 1 1 1
0 0 1 X 1 0 1
0 1 X X 0 0 1
1 X X X 0 1 1

V=D3+D2+D0+D1
 For X:

X=D0’D1’

 For Y:

Y=D0’D1’D2’+D0
Multiplexor

 Multiplexer is a circuit which has

a number of inputs but only one output.
 Multiplexer is a circuit which transmits
large number of information signals over a single
line.
 Multiplexer is also known as “Data Selector” or
MUX.
Necessity of Multiplexers

 In most of the electronic systems, the digital data is

available on more than one lines. It is necessary to route
this data over a single line.
 Under such circumstances we require a circuit which
select one of the many inputs at a time.
 This circuit is nothing but a multiplexer. Which has many
inputs, one output and some select lines.
 Multiplexer improves the reliability of the digital system
because it reduces the number of external wired
connections.
Advantages of Multiplexers

It reduces the number of wires.

So it reduces the circuit complexity and cost.

We can implement many combinational circuits
using Mux.

It simplifies the logic design.

It does not need the k-map and simplification.

Applications of Multiplexers

It is used as a data selector to select one out of

many data inputs.

It is used for simplification of logic design.

It is used in data acquisition system.

In designing the combinational circuits.

In D to A converters.

To minimize the number of connections.

Block Diagram of Multiplexer

D0
D1
Data D2
Inputs D3 Y
. n:1
.
. Mux Output
.
.
Dn-1

E
Enable Input
. . ..

Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram

Relation between Data Input Lines & Select Lines

In general multiplexer contains , n data lines,

one output line and m select lines.

To select n inputs we need m select lines .

Types of Multiplexers

2:1 Multiplexer

4:1 Multiplexer

8:1 Multiplexer

16:1 Multiplexer

32:1 Multiplexer

64:1 Multiplexer

and so on…………
 2:1 Multiplexer

Data D0
Inputs 2:1 Y
D1 Block Diagram
Mux
Output
E
Enable Input
s
Select Lines
Enable i/p Select i/p Output
(E) (S) (Y)

0 X 0
Truth Table
1 0 D0

1 1 D1
Realization of 2:1 Mux using gates

S D1 D0
S

SD0
Y

Output
SD 1
 4:1 Multiplexer

Truth Table
Block Diagram
Output
Enable i/p Select i/p
D0
D1 E S1 S0 Y
Data
Y
Inputs D2 4:1
Mux 0 X X 0
D3 Output
D0
1 0 0
E
1 0 1 D1
Enable Input
S1 S0
1 1 0 D2
Select Lines
D3
1 1 1

80
Realization of 4:1 Mux using gates

S1 S0

S1S 0D0
D0
S1S 0 D 1
D1 Y
Output
D2
S1S 0D2

D3 S1S 0 D3
 8:1 Multiplexer

Truth Table
Block Diagram
Outp
Enable
D0 Select i/p ut
i/p
D1
E S2 S1 S0 Y
D2
0 X X X 0
Data D3 Y
Inputs D4 1 0 0 0 D0
8:1 Output 1 0 0 1 D1
D5 Mux
1 0 1 0 D2
D6
1 0 1 1 D3
D7
1 1 0 0 D4
E 1 1 0 1 D5
Enable Input 1 1 1 0 D6
S2 S1 S0 1 1 1 1 D7
Select Lines
Mux Tree

The multiplexers having more number of inputs

can be obtained by cascading two or more
multiplexers with less number of inputs. This is
called as Multiplexer Tree.

For example, 32:1 mux can be realized using two

16:1 mux and one 2:1 mux.
8:1 Multiplexer using 4:1 Multiplexer

D0
D1
Y1
D2 4:1
Mux
D3

Select S2 E S1 S0 Y
Lines S1
S0 Output
S1 S0
D4
D5
4:1
D6 Mux
Y2
D7

E
8:1 Multiplexer using 4:1and 2:1 Multiplexer

D0
D1
Y1
D2 4:1
Mux
D3

D0
E S1 S0 2:1 Y
D1
S1 Mux
S0 Output
E
S1 S0
D4
D5 S2
4:1
D6 Mux
Y2
D7

E
 16:1 Mux using 4:1 Mux

D0
D1 4:1 Y1
D2 Mux
D3
S1 S0
S1
S0
D4 S1 S0
D5 4:1 Y2
D6 Mux
D7 D0
D1 4:1 Y
D2
Mux
D8
D3 S
1 S0 Output
D9 4:1 Y3
D10
Mux
D11
S1 S0 S3 S2

D12 S1 S0
D13
4:1 Y4
D14 Mux
D15
Realization of Boolean expression using Mux

We can implement any Boolean expression

using Multiplexers.

It reduces circuit complexity.

It does not require any simplification

Example 1

To implement the function F(A, B, C)= Σ (1, 2, 5, 7) using

(a) 8 to 1 MUX (b) 4 to 1 MUX
Example 1 continue…..

Let’s now take the variable A for input lines and B, C for selection lines.
N=3 so MUX is 2 N-1= 22 = 4 to 1
So min terms with A in compliment form are 0 – 3
So min terms with A in un-compliment form are 4–7
Example 2

To implement the function F(A, B, C, D)= Σ (1, 2, 5, 7, 9, 14)

using MUX using different variable as selection variable.
Let’s now take the variable A for input lines and B, C & D for selection lines.
N=4 so MUX is 2 N-1= 23 = 8 to 1
So min terms with A in compliment form are 0 – 7
So min terms with A in un-compliment form are 8 – 15
De-multiplexer

A de-multiplexer performs the reverse

operation of a multiplexer i.e. it receives one
input and distributes it over several outputs.
At a time only one output line is selected by the
select lines and the input is transmitted to the
selected output line.
It has only one input line, n number of output
lines and m number of select lines.
Block Diagram of De-multiplexer

Y0
Y1
Y2
Data Y3
Input 1:n .
.
De-mux .
Outputs
.
.
Yn-1
E
Enable
Input . . ..

Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram

Relation between Data Output Lines & Select Lines

In general de-multiplexer contains , n output

lines, one input line and m select lines.

To select n outputs we need m select lines.

Types of De-multiplexers

1:2 De-multiplexer
1:4 De-multiplexer
1:8 De-multiplexer
1:16 De-multiplexer
1:32 De-multiplexer
1:64 De-multiplexer
and so on…………
1: 2 De-multiplexer

Y0
Data Din 1:2
Block Diagram
Input De-mux
Y1
E
Enable
Input S
Select Lines Enable i/p Select i/p Outputs

E S Y0 Y1

Truth Table 0 X 0 0

1 0 Din 0

1 1 0 Din
1:2 De-mux using basic gates

E Din S
S

Y0

Y1
 1: 4 De-multiplexer

Block Diagram

Y0
Data 1:4 Y1
Input Din De-mux Y2
S S Y3
E Enable i/p
Select i/p Outputs
Enable
Input E S1 S0 Y0 Y1 Y2 Y3
1 0
Select Lines
0 X X 0 0 0 0

1 0 0 Din 0 0 0
Truth Table
1 0 1 0 Din 0 0

1 1 0 0 0 Din 0

1 1 1 0 0 0 Din
1:4 De-mux using basic gates

E Din S 1 S0
S1 S0

Y0

Y1

Y2

Y3
1: 8 De-multiplexer

Y0
Block Diagram
Y1
Data Din Y2
1:8 Y3
Input Y4
De-mux
Y5
Y6
E Y7
Enable
Input
S2 S1 S0
Select Lines
 1: 8 De-multiplexer
Truth Table

Enabl
Select i/p Outputs
e i/p

E S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 Din
1 0 0 1 0 0 0 0 0 0 Din 0

1 0 1 0 0 0 0 0 0 Din 0 0

1 0 1 1 0 0 0 0 Din 0 0 0

1 1 0 0 0 0 0 Din 0 0 0 0

1 1 0 1 0 0 Din 0 0 0 0 0

1 1 1 0 0 Din 0 0 0 0 0 0

1 1 1 Din 0 0 0 0 0 0 0
1
De-mux Tree

Similar to multiplexer we can construct the de-

multiplexer with more number of lines using de-

multiplexer having less number of lines. This is

call as “De-mux Tree”.

1:4 De-mux using 1:2 De-mux

Data Y0 Y0
1:2
Input Din De-mux
Y1 Y1
S1 E S0
Select
Lines
S0

S0
Y0 Y2
Din 1:2
De-mux
Y1 Y3
E
1:16 De-mux using 1:4 De- Y0
1:4 Y1
mux Din De-mux Y2
Y3
S1 S0

S1 S0 Y4
1:4 Y5
Din Y6
Data Y0 De-mux
Din 1:4 Y7
Input Y1
De-mux Y2
Y3
S1 S0
Y8
1:4 Y9
Din De-mux
Y10
S3 S2 S1 S0 Y11

S1 S0 Y12
Din 1:4 Y13
De-mux Y14 S1 S0
Y15