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FIFO Implementation

The ultimate goat

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53 views5 pages

FIFO Implementation

The ultimate goat

Uploaded by

vermamaggi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Birla Institute of

Technology & Science,


Pilani, Hyderabad Campus

Question-1: Implementation of FIFO

ID No. Name
2023H1400128H V. Sahat Monal
Verilog Design code for FIFO
// Code your design here
module main_fifo#(parameter dt_width = 8, ff_depth = 18)
(clk,rst,push_valid,pop_valid,push_data/*in_data*/,pop_data/*out_data*/
,full,empty);
input clk,rst; input [dt_width-1:0] push_data; output reg [dt_width-1:0]
pop_data;
input pop_valid/*(front)*/;input push_valid/*(back)*/; output full, empty;

reg [dt_width-1:0] fifo [ff_depth-1:0];


reg [$clog2(dt_width)-1:0] r_ptr,w_ptr;

always @(posedge clk) begin


if(rst == 0) begin
r_ptr <= 0; w_ptr <= 0;
pop_data <= 0;
end
else begin
if(push_valid & full==0) begin //back is write
fifo[w_ptr] = push_data;
w_ptr = w_ptr + 1'b1;
end
if(pop_valid & empty!=1) begin //front is read
pop_data = fifo[r_ptr];
r_ptr = r_ptr + 1'b1;
end
end
end
assign full = (w_ptr+1'b1 == r_ptr);
assign empty = (w_ptr == r_ptr);
endmodule
Verilog Test Bench code for FIFO with
Assertions:
`timescale 1ns / 1ps

module tb_fifo();

// Parameters
parameter DATA_WIDTH = 8;
parameter FIFO_DEPTH = 16;

// Signals
reg clk = 0;
reg reset = 1;
reg push_valid = 0;
reg [DATA_WIDTH-1:0] push_data = 0;
reg pop_valid = 0;
wire [DATA_WIDTH-1:0] pop_data;
wire empty;
wire full;

// Instantiate FIFO module


main_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) dut (
.clk(clk),
.reset(reset),
.push_valid(push_valid),
.push_data(push_data),
.pop_valid(pop_valid),
.pop_data(pop_data),
.empty(empty),
.full(full)
);

// Clock generation
always #5 clk = ~clk;

// Stimulus
initial begin
// Reset
#10 reset = 0;

// Test push and pop operations


push_data = 8'hFF;
push_valid = 1;
#20;
push_valid = 0;
#20;
pop_valid = 1;
#20;
pop_valid = 0;
#20;

// Test full and empty conditions


push_valid = 1;
#20;
push_valid = 0;
#20;

// End simulation
$stop;
end

// Assertions
// Assertion 1: After reset, write pointer (wr_ptr) should be at 0.
assert property (@(posedge clk) disable iff (reset) wr_ptr == 0);
// Assertion 2: If push_valid is asserted and wr_ptr is less than
FIFO_DEPTH, wr_ptr should increment by 1.
assert property (@(posedge clk) disable iff (reset) (push_valid && wr_ptr
< FIFO_DEPTH) |-> (wr_ptr == $past(wr_ptr) + 1));
// Assertion 3: If push_valid is asserted and wr_ptr is less than
FIFO_DEPTH, the data at wr_ptr in memory should be equal to push_data.
assert property (@(posedge clk) disable iff (reset) (push_valid && wr_ptr
< FIFO_DEPTH) |-> (memory[wr_ptr] == push_data));
// Assertion 4: If pop_valid is asserted, rd_ptr is less than FIFO_DEPTH,
and rd_ptr is less than wr_ptr, rd_ptr should increment by 1.
assert property (@(posedge clk) disable iff (reset) (pop_valid && rd_ptr <
FIFO_DEPTH && rd_ptr < wr_ptr) |-> (rd_ptr == $past(rd_ptr) + 1));
// Assertion 5: If pop_valid is asserted and rd_ptr is less than
FIFO_DEPTH, pop_data should be equal to the data at rd_ptr in memory.
assert property (@(posedge clk) disable iff (reset) (pop_valid && rd_ptr <
FIFO_DEPTH) |-> (pop_data == memory[rd_ptr]));
// Assertion 6: The empty flag should be asserted when wr_ptr is equal to
0 or when rd_ptr is equal to wr_ptr.
assert property (@(posedge clk) disable iff (reset) (empty) |-> (wr_ptr ==
0 || rd_ptr == wr_ptr));
// Assertion 7: The full flag should be asserted when wr_ptr is equal to
FIFO_DEPTH.
assert property (@(posedge clk) disable iff (reset) (full) |-> (wr_ptr ==
FIFO_DEPTH));

endmodule
Vivado Results

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