Worksheet 8
Worksheet 8
:OBJECTIVES
:At the end of this session the student should be able to
1. Construct a half adder using basic logic gates.
2. Construct a half subtractor using universal gates.
3. Prepare the experimental setup properly, operate the equipment and measuring instruments safely,
and get the readings correctly.
4. Compare the experimental values with the predicted values.
Introduction:
A half adder has two inputs for the two bits to be added and two outputs: one from the XOR gate for the
sum S and another from the AND gate for the carry C into the higher adder position.
A full adder is a combinational circuit that forms the arithmetic sum of inputs. It consists of three inputs
and two outputs. A full adder is used to add three bits at a time, but a half adder cannot do so. In a full
adder, the sum output will be taken from XOR gate while the carry output will be taken from the OR
gate.
The half subtractor is constructed using XOR and AND gate. The half subtractor has two inputs and two
outputs: the difference and borrow. The difference output comes from the XOR gate, while the borrow
output is implemented using an AND gate and an inverter.
1
Apparatus and Materials Required
Procedure
1. Check all ICs and components using the IC tester and multimeter.
2. Connect the circuit as shown in the diagram.
3. Set the DC power supply to 5 volts on the breadboard.
4. Connect the Vcc and GND supply to the ICs.
5. Apply various inputs to the IC as shown on the truth table and record the outputs.
6. If there is any problem, check the power supply, check for open and short circuit, and check all
components again.
The Half adder using (a) NAND gates and (b) XOR and AND gates
Write the equations between the inputs and outputs of the circuit:
C=
S=
3
The Half Subtractor using (a) NAND gates and (b) XOR, Inverter and AND gates
Write the equations between the inputs and outputs of the circuit:
BR =
D=
4
The full adder using (a) NAND gates and (b) XOR, AND and OR gate.
5
The Full Subtractor using (a) NAND gates and (b) XOR, Inverter, OR and AND gates.