veCAD-CAD-MAN-TR2008002

ISSN:

veCAD Technical Documentation

L-edit Tutorial on two-input OR gate layout

and verification using LVS

Mohamed Khalil-Hani, PhD

Dr. Shaikh Nasir bin Shaikh Husin
En. Zulkifli bin Md. Yusof

Version Date: 13 Jan 2010 (Issue 1.2)

Abstract/Summary:

This tutorial shows a step-by step guide on how to design an OR gate layout
using L-edit and how to verify its functionality compared to schematic design
using LVS verification tool.

Contents:

1. About this L-edit tutorial

2. L-edit Tutorial
3. LVS tutorial

Revision history:

Version Date Author Change

Issue 1.1 2010-1-13 Annuar Front page formatting
Issue 1.2 2010-1-13 Liew Tek Introduction
Yee

Please send comments and inquiries to:

VLSI-ECAD Research Laboratory (veCAD)

Faculty of Electrical Engineering
University Teknologi Malaysia (UTM)
81310 Skudai, Johor.
[email protected]
www.fke.utm.my/vecad

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 About this L-edit Tutorial
VLSI-ECAD RESEARCH LABORATORY
UNIVERSITI TEKNOLOGI MALAYSIA

Introduction This tutorial is intended to give Tanner EDA user an introduction

of Tanner EDA L-edit. Tanner EDA L-edit is used to capture the
design at layout level. The creation of the mask layout is one of the
most important steps in the full custom (bottom up) design flow,
where the designer describes the detailed geometry and the
relative positioning of each mask layer to be used in actual
fabrication. The work is done through L-Edit layout editor.
Physical layout design is very tightly linked to overall circuit
performance (area, speed and power dissipation) since the
physical structures determines the parasitic capacitances and
resistances, and obviously, the silicon area that is used to realized
a certain function.

Hardware & This tutorial requires the following hardware and software:
Software  A PC running the Windows NT, 2000 or XP operating systems.
 Tanner v8 for Windows.
Requirements Vista and above: run as Administrator and Windows XP
compatibility mode

Prerequisite This tutorial assumes that you have familiar with the following items:
 Basic knowledge on OR gate design
Knowledge

Objectives 1. To expose the user to some of the basic function of L-Edit

user interface.
2. To expose the user to the LVS verification tool.

Assignment 1. Two-input OR gate layout using L-Edit.

2. Proven functionality of circuit simulation.
Deliverables 3. Neat report (layout files, simulation files, netlist, etc…).

Discussions 1. What would happen if you broke the design rule?

2. In your opinion, what makes the design rule? Give points
to support your answers.

[1] Jan M. Rabaey, Anantha Chandrakasan, “Digital Integrated

Reference Circuits: A Design Perspective”, second edition, Prentice Hall,
Upper Saddle River, New Jersey 200

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Creating 2-input OR Gate: Layout Design

1. Launch L-Edit and ignore any warning and

continue using the program. You may want to maximize the layout sheet. You can zoom to
the default position by pressing the <Home> key on your keyboard. The L-Edit window
looks probably almost like this:

This tool indicates the selected layer.

This box display the mouse buttons functions. As an example, the Left
Mouse Button (LMB) indicates a „CHOOSE‟ function and the Right
Mouse Button (RMB) indicates a „MENU‟ function.

(0,0) Coordinate

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2. Change the layout setting to mtsmcn025. File>Replace Setup. Browse for
mtsmcn025.tdb file then click OK. A notification dialogue box will appear. Just click OK.

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3. To create N-well mask on the layout sheet, click N-Well layer button at the layer tool
and click the Box option button at the Drawing tool. Click the LMB on the sheet and drag to
draw the N Well mask polygon.

N Well
layer
palette
selected

Click here

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 5. Resize the N Well polygon to 43 λ by 21 λ. This is how it is done:

i. Press and hold <Ctrl> and click RMB to the desired edge.

ii. Press and hold <Alt> and drag LMB pointed to the desired edge to resize the polygon.

Original Selected Dragged edge Resulting

polygon edge polygon

You can use the keyboard arrow key to scroll around the layout sheet and the zoom button
to zoom the layout sheet according to the mouse function.

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6. Once you have desired N Well size, you can start drawing the Active layer. To do that,
Select the Active layer button at the layer tool, and draw it as shown below:

2.3

2.3

2.3

i. minimum distance between source‟s/drain‟s Active layer and Well - 6 λ (2.3)*

*Design rule number generated from L-edit after DRC for error checking. More details in
MOSIS design rule documentation.

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7. Draw the Poly layer as shown below. The steps are as same as drawing other layers.

3.2

3.1

3.4

3.3

i. minimum width - 2 (3.1)

ii. minimum distance between poly - 2 (3.2)
iii. Poly can exceed Active as minimum as 2 (3.3)
iv. Active can exceed Poly as minimum as 2 (3.4)

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8. Draw the N-select mask.

4.2

4.2

Minimum distance between N-Select and Active - 2 (4.2)

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9. Draw the P-select mask.

4.2

4.2

Minimum distance between N-Select and Active - 2 (4.2)

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10. Draw the Contact mask.

6.4

6.2 4.3

6.1

6.3

i. size - 2 x 2 (6.1)
ii. minimum distance between Contact and Active - 1.5 (6.2)
iii. minimum distance between Contacts - 2 (6.3)
iv. minimum distance between Poly and Contact - 2 (6.4)
v. minimum distance between Select and Contact - 1 (4.3)

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11. Draw metal1 mask.

7.1

7.3

i. minimum width - 3
ii. minimum distance between Metal1 and Contact - 1

There are two ways of drawing orthogonal polygon:

Nibble style

To draw an orthogonal polygon we must draw square polygon first. If the polygon is drawn,
select the polygon.

Click here

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The mouse button function box shows „DRAW BOX‟ for LMB. Draw a box on top of
unwanted area then the area will be deleted.

Drawn box A nibble box drawn Resulting polygon

on top of unwanted
area
Merge sytle

Draw side by side polygons. Select the polygons.

Merge the polygons using the Merge option in the Draw menu. Draw>Merge.

Three polygons side by Resulting polygon

side
These methods can ease the layout design process.

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12. Define ports as shown below.

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 i. If you want to create a port at Metal1 layer, the port‟s polygon must be from the same
Metal1 layer type (you must first clicked the Metal1 layer button in the layer toolbox).
If it is a Poly‟s port, use Poly layer.

ii.

Click here

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Draw a small box (2x2 recommended) in the polygon (example: Metal1). A dialogue box
appears.

Give the port a

name and click OK

13. Now that you have vdd, vss, a_bar, b_bar and y ports defined. Proceed with the Design
Rule Check (DRC).

i.

Click here

Check:
- Place error ports
- Write errors to file:

ii.

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iii. Please define the location and give a name to the .DRC error file. All the errors in the
design will be recorded in this file after DRC. Keep this file as reference. Click Ok to
continue.

Example: There are 5 errors in

this design.

iv.

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 v. To remove the X error‟s marks, go to Tools>Clear Error Layer. A dialogue box will
appear. Click 'OK.'

vi. To view the errors, open the .DRC file with any text editor.

vii. The coordinate shown in this file is from the right coordinate to the wrong coordinate.

viii. Make step by step corrections because maybe the other errors will be undone.

ix. Redo DRC.

14. You should handle ALL the errors before proceed. Now that the errors are handled, we
can extract the spice parameters file.

i.

Click here

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 ii.
Define the extract definition file
State the SPICE output file.
Click „Run‟

iii. Ignore all capacitance.

Now that you have the SPICE parameter file/netlist, it can be simulated using Tanner tool as
you‟ve done it in S-Edit tutorial.

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Comparing 2-input OR gate: Schematic entry versus Layout

1. Run LVS.exe located in LVS folder to execute the tool.

2. Create new LVS setup. Go to File>New. Then choose LVS Setup and click OK. This will
open the setup window.

3. In Input Files section under File tab, browse for the layout and schematic netlist
files (generated in Schematic and Layout tutorials).

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4. Once you have browsed the netlist files, specify (click the button) the output file
location in the Output Files section. This is the output file for the caparison result.

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5. Finally, click the Run Verification button . A Verification window will indicate that
the circuits are equal. If the circuits are not equal, please check your layout design and
regenerate new netlist file for another verification.

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