Introduction: AMBA

Advanced Microcontroller Bus Architecture

To connect w m peripherals to the CPOCores proffered Architectureenoughothersare Available
generalcompassionbtwper forecast
Different Boss are required
Kinds Buss available AMBA Bus
of WISHBONEBUS

Most Modern Processors IENABMBA Bus

LPC23xx 2 versions of AMBA
STM32Fuxx AMBA BUS EMMET
3 SILLY

ra Soc vs nController
Bus Terminologines
microcontroller
SI
Singlechipwithmore Single chipwithlessspecific
Specific peripherals peripherals I
Small control
Intended
for
applications Intended
for
withmore requirements Applications withless
andmore complexity PGott 2
highlost
I
by
providesvalue
provides value
minimizing cost
by 3
maximizingfunctionality
typicalexternalstorage varies
Indigent
varies fromMBgarage
toTB from ABtoMB
flashEEPROM 4
Multicore Generally singleCore
O what is Called a bus master 5
Usually in Separate 110Controller that directs
A feature supported by many bus 1 Sync Asyne Bus
architectures that enables a device Buses have Clocks
connected to the bus to initiate DMA Sync
Address control signal en
Datatransfer all this happens g
generation
transactions at
TheBusmaster generates the Address the edge of Cia
it can be NP or DMA or any other AsyneBuses don'thave Clocks
peripheral No use of Cin
communication somekind
for
HANDSHAKING Is
of
Reg
2 Arbitration Central Distributed Because there is no CIA to
Inmultimaster multislave Bus one syne operation b w thedevices
have Masterslavearch
ofthe masters needs to singlemastermultipleslaves
control over the Bus
whogets control Determined
by an qq.ypgy.gggym
arbitrator Synebuses arefasterthan
2types ofarbitration schemes Asyne becausethere is no
Centralized overhead to establish a
Distributed timereference for each
transaction
 2 A Centralized arbitrationscheme
2A1
Daisychain
Onlysinglebusarbiter performs
the veg arbitrationand it can
be either a processor or a
Separate DMs controller
2 kinds simpleandcheapermethod If a request atthe
makes
morethan onedevice
wherearethemasters Sametimethendevice
Diasychain usethesamelinefor thatis closer to the
IndependentRequest making an requests arbiter willgetbus

an Independentrequest
eachbushasits ownrequest and grant 2 Distributed Arbitration
B
highestpriority requests andassets all devices participate in

in
of nextBus
the system selection master
Ittheremultiplesimultaneousbusrequests used in Ic can.Bus
then we can havesomewind ofpriority notcommonlyused in processor
scheme fined
priorityscheme
Roundrobin Buses

Singledatatransfer transferred
only one datathe will be croconnected to any yoperipheral
The size of data can be And limitedamount of mym is
16bits 32bitsorbitsdependingonBus
size available iiiin peripheralmmtypeis
FIFO
Bursttransfer say
Can have n no datatransfers starting address on08
This is called a of
beat
Beatcan be of sizeSay
any

j
Beatn n 32 bitdata willbe
my
tampered
accounted in terms of beats
8 kc.im
2types
Incrementing Burst

3B Incremental Burst
when CPU connects to mm
4 Pipelining
are ima
large no of locations
available MBofmym Sol to Do Bus pipelining
On08 Busoperation has 2 parts
startingaddress to I generate address Ctrlsignal
Lo 2 Data trouser

i Master a oxo oxon onor onoc nofenddresation

Ontosoar
Slave Datas Datar Batas Batan
Data 2
I
gempos
transfer
Added
of Edda Ten
notransfer Datestransferred
 split transfers
Splittransfers BusPipelining is a requirement
for are also Master Slave Arbitrator
3 entities required

Masters addr.gen
tor.si
m
Arbiter
Slave Da At
Sa
WN Wh N Wh MAtransfer
prioritiesDefault
Beatle
datatransfer requestdata
Requests Wh
masters Wh M highest
2slaves notready fromSs
respondsby aspue pom sa But sa declares M
s s acceptsoneneg 7 slaves not ready ready fortransfer
respondsby aspur toArbiterrestores Ms
Fregrestistreatied Daraa ismade the
availableto52 Mpriorityof Ms n y
gymsand arbiter Fregrestistreateved
MenowtheDATAwill
3 Arbitershiftsthe by m3 and arbiter
betransferred
8 the
p
mummy Arbitershifts
Msisremovedfrom
pygmy
Msisremovedfrom

Allows Bus transfers in out of Order fusion

High Speed Low Speed Bus

LowSpeedGus
legacyperipheral GPlos
TimersSPIsUARes

Gets Connected to how speed bus

High Speed bus
Mlm DMAcontrolled USB EthernetCpu
AMBASB APB
Bridge
Translation bw Lowspeedbus Highspeed
Bus
MultipleBuses are perAMBAspecification
 AMBA 2.0
APB SimpleBus
Buses in AMBAv2.0 IN ro
APB AMBA PeripherialBus forlow Bwperipherals
No pipeline
AMB AMBA HighspeedBus tocommunicate withmaster
ASB AMBA System Bus use Bridge
ReadwritesharestheSame
set ofsignals
Nothinglikesplittransfers
AHB NoBursttransfer
Connected devices are capable
ofhigher Speed and B W ASB
DMA DSPCore Coprocessor Pipelined
Limited no of devices can No Burst transfer
be Connected about16 No Split transfer
Shared data Control
lines Highspeed Bus
Bursed data transferPossible Multimaster Bus
Pipelined Similar to AMB
Split transfers supported LPC23xx don't have ASB
Multimaster Bus onlyAMB
How does Multimaster Bus work
Arbiter
decides the Busmaster

knowwhich
suppose
reamed
areadingfromms msis nowdoesdecoder
mrnaanineofslavestoenable
am
arbiterrandomlygrantsonestome we
istheypand
mox's
address c ontrol
on
sn of
address is
Ms madeavailable ofDecoder
maisaddress the
einearb yp slave
chooses correct

say thedatait toberead

v
fromsa asarb isYpto
address control
selected
sais
mox R EA D
Decoder readmux
ofLine
enables
themrnaea of sa
83iteaddtsFreinsa

SayMswanttowritein S2
was b
Arbiter selectsMsandArb
line is set suchthatm3s
is selectedbyAddress
Address
I
v
and Mox
control

ArbiteralsosetsArbasuch
WRITE
that MWDATA M3isselected
of
bythe writeMox
M3writedatain
 AMB MASTER

Address controlsignals reset

signal
useforgeneratingaddress cinsignalasitissynebus
rewrite I write open
oreadoper for
ready transfer
split
transfer
sizeofdatatransferred
8
seventicaltranspernonsegeans
sizeofBurst
transfer

th
nooustyagaman

jm
Mlmprotectionlevel
notusedhere

separatedata
linesforRead write

AMB SLAVE AMB Arbiter

t oop
Yp to opfromslave
slave cryptomaster
nodatalines
 AMBA 3.0

4kindsofBuses AMB Lite

AMBAPeripheralBus
I

AMBAtracing Bus weused 2

for
debugging
AMB Bothare
AMBlite n

AMBAinterconnectBus split signals

we removed rest is same
as AMB
Singlemaster so no arbiter
IssuewithAmb common qq.me is present
allowsonlyamasterassume
Solution as AMB lite
SOLUTION
removed Ts changes in interface multiple
gloves
Aversmaster

master
Blite
An
no mix
AMBSlave interconnections lite
splittransfer
removed

gym
Amblite

If we wanttohavemultiplemasters
usingantslite usemultilayerAMBlite INTERCONNECT MATRIX
Issue Anislite is a singlemaster Complexset ofswitches
Businterface
same asareas
formultimastersystem
isolates all the
components that
masters is introduced
iii considered tobe
Eachmasteris
its own layer
Itaerefreitonoititiaginedinter
connectwhere all masters
areIsolated
isveg from eachother
My M2 canconn with 3
The interconnectshould beable 52 S3 simultaneously
to accessshare all slaves
Because both are in
performedbythe multilayer
different layers
Interconnect matin takes caresof this
interconnectcomponents
 with Sane Slave
if both the masterswant to
communicate
what
I say Ms Maprovide addrofS2
Wh 2 Theaddress is storedin
to handle this 3
YpstageBuffersboth
sheaddrfrom Ypstage
Buffersgoesto slave2Arbiter
through interconnecting Yw
4slave2 Arbiterdecideswithwhich
master slave2 communicates
Say It communicateswithM1
Datawill be readfromS2
andstored in opstage
pm nyM1
collected
by
now takes data
and saves it again
M2
into for 4
a stagehere it will
from
go to M2

AMBA v3.0 Axl 1

notimp because sem32 don'thaveAxD
Specialize in Burstmodeof
datatransfer
Master Initiator
stave target
for multiplemaster
develop Commswitch
matrin
more of an AsyneBus
Channel BasedArchi

2 3
AxlRead BurstBased
duress
trait 2naan
five
channels
3 ataman
remote

3Bnejaige aDatainsew
5reads
aBnejelige

4 5
Axl write Advantage ofAxl overand
1validadar 2maanready burst
snares
addressistobe
Baejo eachtime gen Because intais
case
synced
Interiors
3rsnesaise for
geguaress entire
abaggata snaanready
address whenamasterinitiates a
Ignition
toreamourstaxanons
multiple
transaction wo
waitingitto
complete it canissue next
aBnejdige o utstanding
transaction

smaanreads a sees
response
Baines
out oforder transactions
tosame
which weorder
place
t ransactionsare
in
sent to
and order responseneed
notbe of
same
aBug
cigar