Clock in 57m32

four Sources of CIN 1 2

generation Very stable Crystals are used
1 HSI High speed internal elk in Sem32
InternalRC cat is present Temperature controlled Crystals
freq 16MHz A sensor is available keeps
monitoring the temp of the
2 HSE Highspeed external Cir Surrounding area Alarms on
External interrupt if temp goes out of
freq u to26MHz Range indicating that freq may
Vary
Oven controlled crystals
Have internal temperature controlled
Fiatthe Pu cat mechanisms which
you will varying temp
be generating the system the crystal adjust states so that
Clk it keeps generating a fined freq
PLL cat will ensure that
the system ax is stable clock Sources during reset
and locked to a particularfreq
1 when system Resets external Clas
4 Low freq will not be functioning
lower the frog of operation 2 It starts with MSI
lower is the powerConsuption 3 Source can be
Later the Clk
Certain modes where lowpower changed to MSE
modes are proffered 4 How does it happens
Two Clocks are available
I RTC LSEfreq 32.768kHz
External Clock
awhythis fog
the Rec generates times
in seconds
So 32.768A 216
divide it by210and get
I see
use to WAKE
up the Sem32
when it is in any of the
low power modes
2 LSI LSI frey 32kHz
used bydevices like the
WATCHDOG
whenyourhighspeedclocks
are not working then it
can work with low speed
Clocks
 System Clock Generation
1 HSI or MSE can be
selected as Yp
2 The selection can be
done using RCC PLLCFGRneg
3 The Selected Source is given
as an Yp to a PLL M
divided cat
Limitation to PLL Mvalve
Range 2 to63
This feeds the
4 RCC CGFR 103 frug to the UCO
Rcc configuration register Ilp freq rangeto uco
The value ofthis register tells which I to2MHz
mode is being used
value mode 5 P Pu Rea n
00 Ms PLL P
O 1 HSE Piga valve allowed 2,46,8
10 PLL
y notallowed It is a multiplier
Valves 50 to 432
PLL will be bypassed if HSI
and HSE is selected 6 freq gp of Vco
Ranges 250to338MHz

7 Maximumvalue ofsystemCiti
manvalue 168MHz
 RCC PLL Configuration register RCC PLLCFGR

1 The Mvalues
6 bits are available
Valid values are 2to32 Clocks
2 The N values All the clocks apartfromsystemCIN
a bits
ValidValves are 50 to 432 s up work higher freq
3 PLL P z as works lower freq
2 bits he works twice the freq
Valves Divideby 3
0 0 2
ofAPB
u
0 1 4
10 6 All 3 haveSeparate clock
11 8 Zoo
5
4 PLLSRC
PLL can be used as
a source elven this
bit is 1
5 PLLQ
used 125 interface
for
Cleaveit for now
Can continuetooverran
o
 Peripheral Clock Generation
2
1 Generation from System Clock
The system UN
generated earlier
is used to
generate ur
signal for
The peripherals

I GATED PERIPHERAL CLOCK 5 TIMERS

Every clock that goes to the ADBperipheral has timers associated
peripheral insem32 is gated with them
TIMERzooin no APBI
If you don't want to use Timer 1,89,1911 APB2
the peripheral you can workingof timer
disable the GATE If APBI Pre scaler L
Then associated timer PeriCir
This saves power forgot will work samefrog
If not usinga peripheral If APBI pre scalar 1 2,4 D
block its clock gate Then associated timer will work
twice the freq
2 AMB Pre Scalar Same forAPB2 and its timers
can have different possible
values
you can have some freq
as system an or divide it
by2
Say Pre scalarvalue 1
MCLA 168 Catman
SYSTICK 1688MHS
3 APB I
lower freq than AMB
man frog 42MHz
divide the 168MHzfreqby
4 to get42MHz
4 APB2
Twice the frog ofAPBI
man frog 89MMS
divide by 2 4168 2
 Registers Involved
RCC C FOR
configuration Register

used for Selecting Presealers AMB we can look the car freq
b w HSI MSE PLL Pre sealers APBI On GPlos
OO MSI Presealers APB MCOI makesthe Ciaavailable Pao
01 HSE Prescaler Rec
1 O PLL 0 I IS CIN
I I notallowed HSE

MCO2 makesthe ciravailableonPag

Portcannot work freq
greater than 100MHz
Goso if source Cla are greater
than 100MHz then Prescale
then to use it
RCC API ENR
API enable register

1 forevery peripheral the 2 To enable the gates to isdifferent

Cla is gated peripherals this register used
to use the peripheral
then only enable the corresponding bits are set 1 to
gater enable the gate for that
peripheral
Example
4

I 2
5
G

f
I System Clock 168MHz
2 AMBPrescaler 1 To AMB 168MHz
3 SYSTCW MCLAG 21MM3s
4 APBI pre scalar 4 no APB I 42MHz To PCEk 42MHz
5 APBI pre scalar 1 As TIMERS 42 2 84MASS
G APB2 pre scalar 2 eAPB2 84MH3 us PCCA 84MHz
7 APB2 pre scalar I TIMERS 2 84 168MHz
 RCC CR
RCC Clock config reg

all 0 them
keepnow 0 for

1 HSI 3 HSE 5 MSEBypass bit

Bit y on Bite 1 ON Bit 1 HSE is Bypassed
Bit 0 OFF Bit to off and yp is directly
from the crystal
2 If Then you
1 4 471 6 Clocksecurity bit
Can evead it to see La HSEready Bit 1 any time cir valve
MSI is ready changes an interrupt
f will be raised
7 PLL Indicatingthat Cla is unstable
bit 1 ON
Bit 0 OFF
8 471
Le PLLready

followthissegence to use the CIN

SYSCLK GEN set M P 0 04 0 Pope
I elven system evesets HSI is defaultcir
for 00 means div by2
2 tochange to E
33612 168MHz
I Go to Rcc Cruey 5 To select MSE as source forPLL
resionbit o o reseon bit 1 I go to RCC PLLCFOR
wadomserpa PLLSR Bit L HSEis source
bit t
3 bit 1 mentstep 6 Turn on the PLL
If MSERDY i go to RCC er neg
nay PLLON Bit L
1 Goto RCC PLLCEGR RCCPLLConfigevey 7 Load the prescalevalves
Crystaloscifreq 12MHz
8 9 go to RCC CFORMeg
Thistis inPLLM a selectPLL Swi L
divide it by92 Vco needelk of1mn as source swoo
Let up sysciafreq 168mHz HPREEO 1
Set PLLN 336 PPRELLO H
PPRE2 203 2
opof Uco 336MHz
 In Cat
10 CheckPLLRD bit for I Fossomies
If bit I nextstep
12mF
Rooms ok
11 select the PLL as source cselected selected
games
for System Clock
I go to RCC CGFR I O
SWI I to PLL is source
Sw 0 0
 Low power modes STM 32
I
1Doty cycle is always
involved in Embeddedsystems
RunsforSometimes
Goes in low powermode forremaining
time
2 Currentis measured as NAlmas

3 PowerConsumed
ZangXV
IronRuntimes
Istandogxstandbytime
g Gereepxsleeptime
5 If Considering only Run Standby t Estopxstoptime
Totaltime
Jang IronXruntime Istandoyxstandbytime
Totaltime

3
Powersavingfeaturesof Sem322 More Power Saving methods
1 IfExternalVoltage
Regulator is good
enough thenthe
internal one can
be bypassed
2 Acceleratoravailable
forreopens
Delaysare ted
whiledataloading
3 every elk for
device isgated

Generally not used and is 4 Largedatatransfer use DMA Keep

any Cpu off
5 Keep Code Size minimum
 Low power modes
1 Sleepmode masccurrent
2 Stopmode
3 Standleymode

sleep mode
meteroatingsleepmode
I
Executing the WF wait for
interrupt or WFE wait for
event instr
2 Method2
If already in low pwrmode
and interruptcomes to This
will take you to normalmode
After servicing ISR you can
Come back to sleepmode
by using SLEEPonEXIT bit
available in system Ctrlneg
set the bit to enable
this
3 is off
Only Core are
Peripherals on
CIA is cut

Stop or standby mode

1 PWRCR Power Ctrlneg
2 In sleepmode If you are
deepsleep mode
Thenyoueither
go in
Stopmode or standby mode
This is decided by PDDs
bit
 features of stop mode features of standby mode
1 All peripherals will be cutoff 1 minimumpower consuption
of all
other than the core modes
2 Peripherals which will be 2 All peripherals are turnedoff
are using low speed
working 3 functional in this mode
CIA LSE or LSE
3 watchdog Rec will be working Independent watchdog
These can full thesystem out Rec
fromstop mode LSI RC
External Interrupts can also LSE Osc
put it out of stopmode
4 movingfromMHz to aM3 Current
consumption will decrease

Memory Rep
s addressis of32 bit
2 4GBmlm is available
Breakup in diagram
3 Code Area These are

James
PeripheralArea
by user

4 manufacturer can change

Mlm mapaccording to
chip no