CS3351 Digital Principles and Computer Organization
CS3351 Digital Principles and Computer Organization
Question Bank
M1 To excel in teaching and learning, research and innovation by promoting the principles of
scientific analysis and creative thinking
To equip students with values, ethics and life skills needed to enrich their lives and enable
M3
them to meaningfully contribute to the progress of society
M4 To prepare students for higher studies and lifelong learning, enrich them with the practical
and entrepreneurial skills necessary to excel as future professionals and contribute to
Nation’s economy
Problem analysis: Identify, formulate, review research literature, and analyze complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual Knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities
PO8
and norms of the engineering practice.
Life-long learning: Recognize the need for, and have the preparation and ability to
PO12 engage in independent and life-long learning in the broadest context of technological
change.
Vision of Department
To emerge as a globally prominent department, developing ethical computer professionals,
innovators and entrepreneurs with academic excellence through quality education and research .
Mission of Department
To create computer professionals with an ability to identify and formulate the engineering
M1
problems and also to provide innovative solutions through effective teaching learning process.
M3 To produce engineers with good professional sKills, ethical values and life skills for the
betterment of the society.
PEO2 To apply core-analytical Knowledge and appropriate techniques and provide solutions to
real time challenges of national and global society
PEO3 Apply ethical Knowledge for professional excellence and leadership for the betterment of
the society.
PEO4 Develop life-long learning skills needed for better employment and entrepreneurship
SYLLABUS
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands
of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location,
Address and Operation – Instruction and Instruction Sequencing – Addressing Modes, Encoding
of Machine Instruction – Interaction between Assembly and High Level Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards. 67
COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of an instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O communication
TOTAL: 75 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog
HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization
and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”,
Tenth Edition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
PART – A
CO Mapping : CO202.1
S. Question Blooms Competenc PO
N Taxanomy e
o. Level
1 Find the Octal equivalent of the hexadecimal number
PO1, PO2,
DC.BA. (May/June 2016) BTL-5 Evaluating
PO3
2 What is meant by multilevel gates networks?(May/June BTL-1 Rememberi PO1
2016) ng
3 Discuss the NOR operation with a truth table. BTL-1 Rememberi PO1
(Nov./Dec. 2015) ng
4 Write short notes on weighted binary codes. (Nov./Dec. BTL-1 Rememberi PO1
2015) ng
5 Convert (126)10 to Octal number and binary number. BTL-1 Rememberi PO1
(Nov./Dec. 2015) ng
6 Prove the following using Demorgan’ theorem [(X+Y)’+ BTL-1 Rememberi PO1
(X+Y)’]’= X+Y (May 2015) ng
12 Realize XOR gate using only 4 NAND gates. (Dec 2013) Understan
BTL-2 PO1, PO2
ding
13 Realize JK flip flop using D flip flop. (Dec 2013) BTL-1 Rememberi PO1
ng
14 Convert the following hexadecimal numbers into BTL-1 Rememberi PO1
decimal numbers: ( Dec 2012) ng
a)263, b)1C3
15 What is the significance of BCD code. ( Dec 2012) BTL-1 Rememberi PO1
ng
16 Simplify the expression: X = (A’+B)(A+B+D)D’. BTL-1 Rememberi PO1
ng
17 Convert (11001010)2 into gray code. BTL-1 Rememberi PO1
ng
b) Convert a Gray code 11101101 into binary code.
25 Plot the expression on K-map: F (w,x,y) =∑m (0, 1, 3, 5, BTL-1 Rememberi PO1
6) + d (2, 4). ng
PART B
1 Reduce the expression using Quine McCluskey's method PO1,
F(x1, x2, x3, x4, x5) = ∑m (0, 2, 4, 5, 6, 7, 8, 10, 14, 17, 18, BTL-6 PO2,
Creating
21, 29, 31) + ∑d (11, 20, 22) (May/June 2016) PO3,
PO4
2 Simplify the following switching functions using Quine
PO1,
McCluskey's tabulation method and realize expression
PO2,
using gates F(A,B,C,D) = Σ(0,5,7,8,9,10, 11, 14,15). BTL-5 Evaluating
PO3,
(Nov/Dec 2015) PO4
3 Simplify the following switching functions using Karnaugh BTL-1 Remembering PO1
map method and realize expression using gates F(A,B,C,D)
= Σ(0,3,5,7,8,9,10,12,15). (Nov/Dec 2015)
4 (a) Express the following function in sum of min-terms and BTL-5 Evaluating PO1,
PO2,
product of max-terms F(X,Y,Z)=X+YZ (May 2015)
PO3,
PO4
10 Simplify the given boolean function in POS form using K- BTL-5 Evaluating PO1,
map and draw the logic diagram using Only NOR gates PO2,
F(A,B,C,D)= ∑m (0,1,4,7,8,10,12,15)+d(2,6,11,14). PO3,
(Dec2013) PO4
ii)Convert 78.510 into binary.
iii)Find the dual and complement of the following Boolean
expression Xyz’+x’yz+z(xy+w).
UNIT II
SYNCHRONOUS SEQUENTIAL LOGIC
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of FF, Analysis
and design of clocked sequential circuits – Design – Moore/Mealy models, state minimization, state
assignment, circuit implementation - Registers – Counters.
PART – A
CO Mapping : CO202. 2
S. Question Blooms Competence PO
N Taxanom
o. y Level
1 Design the combinational circuit with 3 inputs and 1 BTL-1 Remembering PO1
output. The output is 1 when the binary value of the input
is less than 3. The output is 0 otherwise.
(May/June 2016)
7 Write the data flow description of a 4-bit comparator. BTL-1 Remembering PO1
(May 2015)
8 Implement a full adder with 4×1 multiplexer. (May 2015) BTL-1 Remembering PO1
9 Implement the following Boolean function using 8:1 BTL-1 Remembering PO1
multiplexer F(A,B,C)= ∑m(1,3,5,6)(Dec 2014)
13 Obtain the truth table for BCD to Excess-3 code BTL-1 Remembering PO1
converter. (Dec 2013)
14 Write the stimulus for 2 to 1 line MUX. (June 2012) BTL-1 Remembering PO1
15 Distinguish between a decoder and a demultiplexer. (June BTL-1 Remembering PO1
2012)
16 Design a 2-bit binary to gray code converter. BTL-1 Remembering PO1
17 Draw the 4 bit Gray to Binary code converter. BTL-1 Remembering PO1
18 Draw the 4 bit Binary to Gray code converter. BTL-1 Remembering PO1
19 Distinguish between combinational logic and sequential BTL-1 Remembering PO1
logic.
20 Implement half Adder using NAND Gates. BTL-1 Remembering PO1
22 Give the truth table for half adder and write the PO1,
expression for sum and carry. PO2,
BTL-5 Evaluating
PO3,
PO4
23 Mention the different type of binary codes. BTL-1 Remembering PO1
PART B
1 Implement the following Boolean function with 4 X 1
multiplexer and external gates. Connect inputs A and B to the
selection lines. The input requiremnts for the four data lines
will be a function of variables C and D these values are
obatined by expressing F as a function of C and D for each
four cases when AB = 00, 01, 10 and 11. These functions may PO1,
have to be implemented with external gates. F(A, B, C, D) = BTL-5 PO2,
Evaluating
Σ (1, 2, 5, 7, 8, 10, 11, 13, 15). (May/June 2016) PO3,
PO4
2 Design a full adder with x, y, z and two outputs S and C. The BTL-6 Creating PO1,
circuits performs x+y+z, z is the input carry, C is the output PO2,
carry and S is the Sum. PO3
(May/June 2016)
PO1,
PO2,
BTL-5 Evaluating
PO3,
PO4
10 Understanding PO1,
Construct a 4 to 16 line decoder with an enable input using F(W,X,Y,
Z)= ∑m PO2
five 2 to 4 line decoders with
(0,1,3,4,8,
enable inputs. (June 2012) 9,15).
UNIT III
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands of
Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location, Address
and Operation – Instruction and Instruction Sequencing – Addressing Modes, Encoding of Machine
Instruction – Interaction between Assembly and High Level Language
PART-A
Bloom’s
Q. No. Questions CO
Level
Write the basic functional units of computer? (APR/MAY 2017,NOV/DEC C204. BTL1
2017) 1
2. The basic functional units of a computer are input unit, output unit, memory unit,
ALU unit and control unit.
What is a bus? What are the different buses in a CPU? [ APR/MAY 2011] C204. BTL1
1
A group of lines that serve as a connecting path for several devices is called
bus .The different buses in a CPU are 1] Data bus 2] Address bus 3] Control bus.
3.
What is meant by stored program concepts? C204. BTL1
4. 1
Stored program concept is an idea of storing the program and data in the memory
List the eight great ideas invented by computer architecture? APR/MAY-2015 C204. BTL1
1
Design for Moore’s Law
Use abstraction to simplify design
Make the common case fast
8 Performance via Parallelism
Performance via Pipelining
Performance via Prediction
Hierarchy of Memory
Dependability via Redundancy
List out the methods used to improve system performance. C204. BTL1
1
The methods used to improve system performance are
21 Processor clock
Basic Performance Equation
Pipelining
Clock rate
Instruction set
Compiler
Define addressing modes and its various types.(nov/dec 2017) C204. BTL1
1
The different ways in which the location of a operand is specified in an
22 instruction is referred to as addressing modes. The various types are
Immediate Addressing, Register Addressing, Based or Displacement
Addressing, PC-Relative Addressing, Pseudodirect Addressing.
25
Define Relative mode addressing. C204. BTL1
(Nov 2014) 1
In PC-relative mode addressing, the branch address is the sum of the PC and a
26 constant in the instruction. - In the relative address mode, the effective address is
determined by the index mode by using the program counter in stead of general
purpose processor register. This mode is called relative address mode.
31 Distinguish between auto increment and auto decrement addressing mode? C204. BTL1
1
MAY/JUNE 2016
A special case of indirect register mode. The register whose number is included in
the instruction code, contains the address of the operand. Autoincrement Mode =
after operand addressing , the contents of the register is incremented. Decrement
Mode = before operand addressing, the contents of the register is decrement. We
denote the autoincrement mode by putting the specified register in parentheses, to
show that the contents of the register are used as the efficient address, followed by
a plus sign to indicate that these contents are to be incremented after the operand is
accessed. Thus, using register R4, the autoincrement mode is written as (R4)+.
32
In the above example, we could also say that computer B is 1.5 times slower
than computer A, since
means that
33 Our favorite program runs in 10 seconds on computer A, which has a 2 GHz C204. BTL1
clock. We are trying to help a computer designer build a computer, B, which 1
will run this program in 6 seconds. The designer has determined that a
substantial increase in the clock rate is possible, but this increase will affect
the rest of the CPU design, causing computer B to require 1.2 times as many
clock cycles as computer A for this program. What clock rate should we tell
the designer to target?
Let’s first find the number of clock cycles required for the program on A:
CPU time for B can be found using this equation:
To run the program in 6 seconds, B must have twice the clock rate of A.
34 Suppose we have two implementations of the same instruction set C204. BTL1
architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for 1
some program, and computer B has a clock cycle time of 500 ps and a CPI of
1.2 for the same program. Which computer is faster for this program and by
how much?
We know that each computer executes the same number of instructions for the
program; let’s call this number I. First, find the number of processor clock cycles
for each computer:
Now we can compute the CPU time for each computer:
Likewise, for B:
Clearly, computer A is faster. The amount faster is given by the ratio of the
execution times:
We can conclude that computer A is 1.2 times as fast as computer B for this
program.
Define CPU execution time and list the types. C204. BTL1
1
CPU execution time
Also called CPU time. The actual time the CPU spends computing for a
specific task.
Types:
35
User CPU time
The CPU time spent in the operating system performing tasks on behalf of
the program
Define response time C204. BTL1
1
36 Response time:
Also called execution time. The total time required for the computer to
complete a task, including disk accesses, memory accesses, I/O activities,
operating system overhead, CPU execution time, and so on.
Write Basic performance equation in terms of instruction count (the number C204. BTL1
of instructions executed by the program), CPI, and clock cycle time. 1
39
3.J-type or Jump
What are the types of instruction in MIPS.(APR/MAY2018) C204. BTL1
1
1. Arithmetic instruction
2. Data transfer Instruction
48 3. Logical Instruction
4. Conditional Branch Instruction
5. Unconditional jump Instruction
Bloom’s
Q. No. Questions CO
Level
Explain the various components of computer System with neat diagram (16) C204. BTL5
1
.(NOV/DEC2014,NOV/DEC2015,APR/MAY 2016,NOV/DEC
2. 2016,APR/MAY2018)) (Page.No:16-17)
Define Addressing mode and explain the different types of basic C204. BTL5
addressing modes with an example 1
(Page.No:116-117)
i)Discuss the Logical operations and control operations of computer (12) C204. BTL6
1
(Page.No:87-89)
5.
ii)Write short notes on Power wall(6)
(Page.No:40-42)
6. Consider three diff erent processors P1, P2, and P3 executing the same instruction C204. BTL5
set. P1 has 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a 1
CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. (APR/MAY 2018)
a. Which processor has the highest performance expressed in instructions
per second?
c. We are trying to reduce the execution time by 30% but this leads to an
increase
of 20% in the CPI. What clock rate should we have to get this time
reduction?
(Refer Notes)
Explain various instruction format illustrate the same with an example C204. BTL5
7. 1
NOV/DEC2017 (Page.No:80-86)
Explain direct ,immediate ,relative and indexed addressing modes with C204. BTL5
8. example APR/MAY2018 (Page.No:116-117) 1
State the CPU performance equation and the factors that affect performance C204. BTL5
(8) 1
9.
(NOV/DEC2014) (Refer Notes)
Discuss about the various techniques to represent instructions in a computer C204. BTL6
system. 1
10.
(APRIL/MAY2015,NOV/DEC 2017) (Page.No:80-86)
What is the need for addressing in a computer system?Explain the different C204. BTL5
addressing modes with suitable examples.(APRIL/MAY2015) 1
11.
(Page.No:116-117)
Explain types of operations and operands with examples.(NOV/DEC 2017) C204. BTL5
12. 1
(Page.No:63-70)
Consider two diff erent implementations of the same instruction C204. BTL5
13. 1
set architecture. Th e instructions can be divided into four classes according
to
their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs
of 1, 2, 3,
into classes as follows: 10% class A, 20% class B, 50% class C, and 20%
class D,
(Refer Notes)
(Refer Notes)
Describe the steps that transform a program written in a high-level C204. BTL4
1
language such as C into a representation that is directly executed by a
15.
computer processor.
(Refer Notes)
UNIT IV 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards – Exceptions.
PART-A
Bloom’s
Q. No. Questions CO
Level
What is pipelining?
The time required between moving an instruction one step down the pipeline is
a processor cycle.
3.
What is a pipeline hazard and what are its types? C204. BTL1
3
Any condition that causes the pipeline to stall is called hazard. They are
8
also called as stalls or bubbles. The various pipeline hazards are:
The term exception is used to refer to any event that causes an interruption.
15
Interrupt:
An exception that comes from outside of the processor. There are two
types of interrupt.
16 Why is branch prediction algorithm needed? Differentiate between the C204. BTL1
static and dynamic techniques. (May 2013,APR/MAY 2015,NOV/DEC 15) 3
The branch instruction will introduce branch penalty which would reduce the
gain in performance expected from pipelining. Branch instructions can be
handled in several ways to reduce their negative impact on the rate of
execution of instructions. Thus the branch prediction algorithm is needed.
The idea is that the processor hardware assesses the likelihood of a given
branch being taken by keeping track of branch decisions every time that
instruction is executed. The execution history used in predicting the outcome
of a given branch instruction is the result of the most recent execution of that
instruction.
How do control instructions like branch, cause problems in a pipelined C204. BTL1
processor? 3
Pipelined processor gives the best throughput for sequenced line instruction.
In branch instruction, as it has to calculate the target address, whether the
18
instruction jump from one memory location to other. In the meantime, before
calculating the larger, the next sequence instructions are got into the pipelines,
which are rolled back, when target is calculated.
Branch difficulties → Arises from branch and other instruction that change the
value of PC (Program Counter).
One of the most important methods for finding and exploiting more ILP is
speculation. It is an approach whereby the compiler or processor guesses the
outcome of an instruction to remove it as dependence in executing other
instructions. For example, we might speculate on the outcome of a branch, so
that instructions after the branch could be executed earlier.
Precise interrupt
0000 AND
0001 OR
38
0010 add
0110 sub
1100 NOR
Define Don’t-care term C204. BTL1
An element of a logical function in which the output does not depend on 3
the values of all the inputs
39
40
46
What is Control Hazard? C204. BTL1
Control hazard is also called as branch hazard. When the proper 3
instruction cannot execute in the proper pipeline clock cycle because the
47 instruction that was fetched is not the one that is needed; that is, the flow of
instruction addresses is not what the pipeline expected.
Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial Interface
– Interrupt I/O – Interconnection Standards: USB, SATA
PART -A
Bloom’s
Q. No. Questions CO
Level
A structure that uses multiple levels of memory with different speeds and
3. sizes. The faster memories are more expensive per bit than the slower memories.
How cache memory is used to reduce the execution time. (APR/MAY’10) C204. BTL6
5
7 If active portions of the program and data are placed in a fast small memory,
the average memory access time can be reduced, thus reducing the total
execution time of the program. Such a fast small memory is called as cache
memory.
storage. Two major motivations for virtual memory: to allow efficient and safe
sharing of memory among multiple programs, and to remove the programming
burdens of a small, limited amount of main memory
Distinguish between isolated and memory mapped I/O? (May 2013) C204. BTL1
5
The isolated I/O method isolates memory and I/O addresses so that memory
address values are not affected by interface address assignment since each has its
15 own address space.
In memory mapped I/O, there are no specific input or output instructions. The
CPU can manipulate I/O data residing in interface registers with the same
instructions that are used to manipulate memory words
When I/O devices and the memory share the same address space, the
arrangement is called memory mapped I/O. The machine instructions that can
access memory is used to trfer data to or from an I/O device.
16
I/O mapped I/O:
Here the I/O devices the memories have different address space. It has special
I/O instructions. The advantage of a separate I/O address space is that I/O
devices deals with fewer address lines.
SRAMs are simply integrated circuits that are memory arrays with a single
access port that can provide either a read or a write. SRAMs have a fixed access
time to any datum.
SRAMs don’t need to refresh and so the access time is very close to the cycle
time. SRAMs typically use six to eight transistors per bit to prevent the
information from being disturbed when read. SRAM needs only minimal power to
retain the charge in standby mode.
26
C204. BTL1
Point out how DMA can improve I/O speed? APRIL/MAY 2015 5
CPU speeds continue to increase, and new CPUs have multiple processing
elements on the same chip.A large amount of data can be processed very quickly
Problem in the transfer of data to CPU or even memory in a reasonable amount of
time so that CPU has some work to do at all time . Without DMA, when the CPU
27
is using programmed input/output, it is typically fully occupied for the entire
duration of the read or write operation, and is thus unavailable to perform other
work. With DMA, the CPU first initiates the transfer, then it does other operations
while the transfer is in progress, and it finally receives an interrupt from the DMA
controller when the operation is done.
28 C204. BTL1
What are the various memory Technologies?NOV/DEC 2015 5
Memory Technologies
C204. BTL3
5
What is flash memory?
In many computers the cache block size is in the range 32 to 128 bytes. C204. BTL1
What would be the main Advantages and disadvantages of making the size 5
of the cache blocks larger or smaller?
30
Larger the size of the cache fewer be the cache misses if most of the data in the
block are actually used. It will be wasteful if much of the data are not used before
the cache block is moved from cache. Smaller size means more misses
C204. BTL1
5
Define miss rate.
36
Miss rate The fraction of memory accesses not found in a level of the
memory hierarchy.
40 C204. BTL1
5
What are the steps to be taken on an instruction cache miss:
2. Instruct main memory to perform a read and wait for the memory to
complete its access.
3. Write the cache entry, putting the data from memory in the data portion of
the entry, writing the upper bits of the address (from the ALU) into the tag
field, and turning the valid bit on.
4. Restart the instruction execution at the first step, which will refetch the
instruction, this time finding it in the cache
C204. BTL1
5
What are the techniques to improve cache performance?
C204. BTL1
5
Define dirty bit
44
dirty bit is commonly used. This status bit indicates whether the block is dirty
(modified while in the cache) or clean (not modified).
C204. BTL1
5
What are the messages transferred in DMA?
46
PART -B
Bloom’s
Q. No. Questions CO
Level
Expain in detail about memory Hierarchy with neat diagram C204. BTL5
2. . 5
( Page.No:-374-378)
Discuss the methods used to measure and improve the performance of the C204. BTL6
4. .
cache.(NOV/DEC 2017) ( Page.No:-398-417) 5
Explain the virtual memory address translation and TLB with necessary C204. BTL5
diagram.(APRIL/MAY2015,NOV/DEC 2015,NOV/DEC 5
5. 2016,APR/MAY2018) ( Page.No:-427-452)
C204. BTL5
5
Draw the typical block diagram of a DMA controller and explain how it is
6.
used for direct data transfer between memory and peripherals. (NOV/DEC
2015,MAY/JUNE 2016,NOV/DEC 2016,MAY/JUN 2018) Page.No:-399-
402)
Describe in detail about programmed Input/Output with neat diagram C204. BTL5
8. 5
(MAY/JUN 2018) (Refer notes)
Draw different memory address layouts and brief about the technique used C204. BTL5
to increase the average rate of fetching words from the main memory (8) 5
10. (NOV/DEC2014)
(Refer notes)
Explain in detail about any two standard input and output interfaces C204. BTL5
required to connect the I/O devices to the bus.(NOV/DEC2014) 5
11.
(Page.No:-438-452)
Explain mapping functions in cache memory in cache memory to determine C204. BTL5
how memory blocks are placed in cache (Nov/Dec 2014) (Refer notes) 5
12.
Explain the various mapping techniques associated with cache memories C204. BTL5
(MAY/JUNE 2016,MAY/JUN 2018) 5
13.
(Refer notes)
Explain sequence of operations carried on by a processor when interrupted C204. BTL5
14. by a peripheral device connected to it(MAY/JUN 2018) (Page.No:-436- 5
242)
Explain virtual memory and the advantages of using virtual memory C204. BTL5
15. 5
(Page.No:-427-252)
PART-B
Bloom’s
Q. No. Questions CO
Level
Explain the basic MIPS implementation with binary multiplexers and C204.3 BTL5
1. .
control lines(16) NOV/DEC 15 (Page.No:244-251)
What is hazards ?Explain the different types of pipeline hazards with C204.3 BTL5
suitable examples.(NOV/DEC2014,APRIL/MAY2015,MAY/JUNE
2. 2016,NOV/DEC2017) (Page.No:303-324)
3. Explain how the instruction pipeline works. What are the various situations C204.3 BTL5
where an instruction pipeline can stall? Illustration with an example?
NOV/DEC 2015,NOV/DEC 2016.( Page.No:301-302)
Explain data path in detail(NOV/DEC 14,NOV/DEC2017) C204.3 BTL5
4.
( Page.No:251-259)
Explain in detail How exceptions are handled in MIPS architecture. C204.3 BTL5
6.
(APRIL/MAY2015) .( Page.No:325-332)
C204.3 BTL3
10. Why is branch prediction algorithm needed?Differentiate between static
and dynamic techniques?NOV/DEC 2016 .( Page.No:321-323)
Design a simple path with control implementation and explain in C204.3 BTL6
11.
detail(MAY/JUN 2018) ( Page.No:251-271)
Discuss the limitation in implementing the processor path. Suggest the C204.3 BTL6
12.
methods to overcome them(NOV/DEC 2018) (Refer notes)
13. When processor designers consider a possible improvement to the processor C204.3 BTL5
the following three problems, assume that we are starting with a datapath
where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have
latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps,
respectively,and costs of 1000, 30, 10, 100, 200, 2000, and 500,
respectively.Consider the addition of a multiplier to the ALU. Th is addition
will add 300 ps to the latency of the ALU and will add a cost of 600 to the
ALU. Th e result will be 5% fewer instructions executed since we will no
longer need to emulate the MUL instruction.
1 What is the clock cycle time with and without this improvement?
(Refer notes)
For the problems in this exercise, assume that there are no pipeline stalls C204.3 BTL3
and that the breakdown of executed instructions is as follows:
circuit needed? What is this circuit doing in cycles in which its input is not
needed? (Refer notes)
loop:lw r1,0(r1)
and r1,r1,r2
lw r1,0(r1)
15. lw r1,0(r1)
beq r1,r0,loop
Assume that perfect branch prediction is used (no stalls due to control
hazards),that there are no delay slots, and that the pipeline has full
forwarding support. Also assume that many iterations of this loop are
executed before the loop exits. (Refer notes)