Modelling-Optimization-Hardware Implementation and Validation of Digital Signal Processing Algorithms
Modelling-Optimization-Hardware Implementation and Validation of Digital Signal Processing Algorithms
Abstract
.
Keywords: QCM, ZnO nanorods, Gas sensing
Tóm tắt
(mỗi phần từ 100 đến 150 từ).
Từ khóa: QCM, Thanh nano ZnO, Cảm biến khí (từ 3 đến 5 từ hoặc cụm từ)
1. Introduction*
Nowadays, digital signal processing algorithms are
used in almost all electronic systems. In multimedia
application, digital signal processing have replaced all
analog processing components in audio, video
encoders/decoders, speech, image processing. In
telecommunications, digital processing has been
applied not only in baseband frequency domain but
also in intermediate and even in radio frequency
domains.
Digital signal processing algorithms can be
implemented in general purpose processors (GPPs),
digital signal processors (DSPs), field-programmable
gate arrays (FPGAs), and application-specific
integrated circuit (ASICs). Implementation in GPPs
and DSPs are fast and simple by using signal
processing specific Application Programming
Interfaces (APIs) and libraries. The APIs and libraries
in GPPs, and DSPs provide digital signal processing
instructions/functions such as multiplier-
accumulations, floating point number operations, …
However, GPPs and DSPs often consume more
*
Corresponding author: Tel.: (+84) 912.345.678
Email: [email protected]
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Journal of Science and Technology
However, implementation in FPGAs and ASICs often The channel mismatches in TI-ADCs can be
requires more efforts as the lack of supported effectively handled by analog and/or mixed signal
libraries. In order to save hardware resource as well calibration techniques~\cite{El-
as energy consumption, the fixed-point architecture Chammas2010,Doris2011,Stepanovic2013}.
needed to be designed from the floating point However, such techniques use an additional analog
algorithm as the fixed point hardware is much circuit with longer design time. Recently, all-digital
cheaper and less complex than floating point one. calibration techniques have been proposed~\
Many methods for floating point to fixed point cite{Jamal2004b,Francois2012,Venosa2012,Matsuno
conversion in some environments have been proposed 2013,Hleduc, Nicolas2014}. The all-digital
that help to shorten implementation time. In \ techniques can be developed faster, make use of the
cite{banerjee2003automatic}, a method that is used advantages of CMOS technology scaling, and easier
to convert from floating point Matlab application into to port to the next technology generation. In previous
fixed point version for hardware implementation is works, only the calibration algorithms were proposed,
proposed. The proposed method is associated with but the design methodology for such algorithms are
AccelFPGA behavioral synthesis tool \ not mentioned.
cite{banerjee2003accelfpga}. By using this tool,
synthesizable HDL source code can be generated In this paper, the calibration algorithm proposed in~\
automatically from Matlab descriptions of DSP cite{Hleduc} should be designed, optimized, and
algorithms. In \cite{shi2003automated}, a floating validated in ASIC and FPGA technology.
point to fixed point conversion methodology for The paper is organized as follows. In Section 2, the
digital VLSI signal processing systems is proposed. basic concepts of TIADC as well as its signal model
In \cite{shi2004automated}, the same author of \ will be briefly formulated. Section 3 presents the all-
cite{shi2003automated} presents a tool that digital calibration architecture~\cite{Hleduc} . In
automates the floating-point to fixed-point conversion Section 4, a systematic methodology flow for
process for the same kind of system. According to \ hardware implementation and optimization of the
cite{shi2004automated}, this tool automatically proposed algorithm is described. Section 5 will
optimizes fixed-point data types of arithmetic represents the FPGA validation and ASIC synthesis
operators, including overflow modes, integer word results for the implemented hardware. Finally,
lengths, fractional word lengths, and the number Section 6 summaries the paper.
systems. In \cite{coors2002design}, FRIDGE design
2. Fundamental of TIADCs
environment is introduced. In this environment,
there's a tool that supports the floating point to fixed- In a \emph{Time Interleaved Analog to Digital
point transformation in which signal processing Converter} (TIADC), $M$ sub ADCs (channels)
algorithms coded in floating-point ANSI C are works in parallel manner. The sub ADCs are driven
converted to a fixed-point representation in SystemC. by the equally phase-shifted clocks at frequency
$f_s/M$. The output of the TIADC being formed by
When high speed, high resolution Analog to Digital multiplexing the sub-ADC outputs is the sampled
Converters are needed in modern communication input at sampling rate $f_s$. Figure~\ref{fig:tiadc}
systems such as broadband satellite receivers, cable demonstrates the TIADC general structure as well as
TV tunners, Software-Defined Radios, time- the sampling clocks of the sub-ADCs.
interleaved techniques are often used to design such
ADCs. Time-interleaved consists of several slow but
accurate sub-ADCs working parallelly [ccurate sub-
ADCs working parallelly []. However, the resolution
(or the effective number of bits) of TI-ADCs is
reduced because of the mismatches in gain, offset,
timing parameters of sub-ADCs. Such mismatches
generate spurious frequency elements at the TI-ADC
outputs, hence, decrease the SFDR/SNDR
performance of the converters. Because the sub-ADCs are driven by same frequency
clocks with equally time-shifted by $T_s$, they can
consecutively sample the input signal at every
sampling period $T_s$. When the sub-ADCs are
ideally identical (in term of their transfer functions),
the output of TIADC is the same as an ADC worked
at sampling rate $f_s$. However, because the sub-
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Journal of Science and Technology
ADCs are not identical, their transfer functions are piezoelectric material suitable for the QCM due to its
not the same, there will be error in the TIADC output. high sensitivity to mass change on the surface. The
resonant frequency (fo) in this work was evaluated
In the scope of sub-ADC mismatches, we can use a
from the conductance peak. It has been observed that
simplified digital signal processing model of TIADCs
the conductance versus frequency curve shows a
as shown in~Figure~\ref{fig:tiadc-dsp}. The input
fundamental resonance peak at 5.48 MHz (Fig. 2b).
signal sampled at clock rate $f_s$ and concurrently
The ZnO nanorods were then grown on one side of
fed to the discrete transfer functions $H_m$ of sub-
the Au electrode-coated QCM by the wet chemical
ADCs. The transfer function $H_m$ characterizes the
route. Fig. 3 shows SEM images of the top-view (3a)
behavior of the sub-ADC $m$ gain ($1+g_m$), offset
and side-view (3b) of as-grown ZnO nanorods on the
($o_m$) and timing error ($t_m$) shown in Figure~\
Au electrode of the QCM. The morphology of the
ref{fig:sub-ADC-Hk}. After that, the interleaving
ZnO nanorods with a hexagonal structure was
behavior of the TIADC is model by downsampling,
vertically well-aligned and uniformly distributed on
upsampling and pseudo delay $Z^k$, $Z^-k$ blocks.
the Au electrode of the QCM. This shows that the
exposed area of the sensing layer was remarkably
enhanced compared with the sensing layer of the ZnO
nanowires [1]. The average diameter and length of
ZnO nanorods were around 100 nm and 3 m,
respectively. In comparison with the ZnO nanowires
that were first synthesized by evaporating high purity
zinc pellets at 900 ºC and were then distributed on the
QCM [2], the wet chemical route has many
advantages such as low cost, low temperature
operation, high preferred orientation, and
environmental friendliness. This method can also
directly grow ZnO nanorods with high uniform
distribution on a large area.
Table 1. The main components of fresh cassava
Composition base on dry
Main components
weight (%, w/w)
The output $y(n)$ of the M-channel TIADC can be Water concentration 58.6 - 59.9
written as follows: Starch 28 - 31
y (n)=[¿ y (0), y (1)… , y (M −1), … ,¿ y (Mi), y (Mi+1),
Fig. … y (Mi+
5a ,shows thek), … , y (Mi+
response M −1),…
transients ]
of the ZnO
In frequency domain, the nanorod-coated QCM sensor to switching-on and off
of the NH3 gas-flow with different concentrations (50,
3. All digital calibration for TIADC timing error 100, and 200 ppm) at room temperature (25 ºC). In
In this section, we briefly describe all digital the first stage, the sensor flushed a reference air gas
calibration technique to handle the timing error flow of 15 sccm to obtain a baseline. The sensor was
occuring in TIADC due to clock skew mismatch then exposed to a NH3 gas flow of 15 sccm with a
proposed in ~\cite{Hleduc}. certain concentration, which leads to frequency
response until a steady stage was reached, indicating
The calibration technique for TIADC is often maximum adsorption of NH3 gas onto the QCM
based on Least Mean Square architecture in which a sensor. The NH3 gas flow was finally replaced by the
LMS feed back loop is used to estimate the error air gas flow and the sensor returned back to its
coefficients of the spurios components in the output baseline. In this experiment, the flow rate of the
signals. diluted ammonia gas and dry air was fixed at 15
3. Results and disscution sccm. Hence, in the gas sensing chamber, the flow
and pressure were ensured to be constant. The change
Fig. 2 shows a photograph and the resonant in resonant frequency of a QCM (∆f) can be related to
characteristics of the as-fabricated QCM device using the change in mass (∆m) due to the adsorption of NH 3
AT-cut quartz crystal plate as a precursor substrate. gas.
The AT-cut quartz crystal is well known as a
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Journal of Science and Technology
Fig. 1. SEM images of ZnO nanorods grown by wet chemical bath deposition: (a) top-view and (b) side-view.
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Journal of Science and Technology
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