8085 Instruction Set :

An Instruction is a binary pattern designed inside a microprocessor to perform

specific functions. The all instructions group is called instruction set.

 Instruction set determines what functions the microprocessor can perform.

 The 8085 microprocessor includes the instruction set of 8088A and two
additional instructions.

 Each instruction has two parts.

– The first part is the task or operation to be performed. This part is called the
“opcode” (operation code).
– The second part is the data to be operated on Called the “operand”.

Instruction set of 8085 microprocessor

 Data Transfer Instruction
 Arithmetic Instructions
 Logical Instructions
 Branching Instructions
 Control Instructions

Data transfer instructions

 These instructions move data between registers,
 between memory and registers.
 Data between a memory location and a register
 Data between an I\O Device and the accumulator.
 These instructions copy data from source to destination.
 While copying, the contents of source are not modified.

Example: MOV, MVI, IN, OUT, LDA, STA, LDAX, STAX, LXI,
LHLD,SHLD, XCHG
Opcode Operand Description
MOV Rd, Rs Copy from source to destination.

M, Rs All MOV instructions are of 1-byte instruction

Rd, M

Dr VP Dubey
 MOV Rd, Rs  Copy the contents of source register to destination
register
Rd or Rs : A,B,C,D,E,H,L

 The contents of the source register are not altered.

Ex. MOV A, B; MOV B,C ; MOV E,A etc
MOV M, Rs Copy the contents of source register(Rs) to memory
specified by HL pair register.

MOV M, A Copy the contents of accumulator to the memory

address specified by HL pair register
MOV Rd, M Copy the contents of memory location specified by HL
pair register to the destination register(Rd)
-The 16-bit contents of the HL register pair are treated
as a 16-bit address and used to identify the memory
location.
-The HL register pair is always used in conjunction with
the memory register “M”
MOV B, M Copy the contents of memory specified by HL pair
register to the register B
MVI Rd, 8 -bit Move Immediate 8 bit data
M, 8 -bit
MVI A, 8-bit  2-byte instruction
 Copy the 2nd byte of 8 bit-data to the accumulator
MVI M, 8-bit  2-byte instruction
 Copy the 2nd byte of 8-bit data to the accumulator
OUT 8-bit port -Output to the port
address -1-byte instruction
Copies the contents of the accumulator to the output
port address
IN 8-bit port -Input from the port
address -1-byte instruction
Copies the 2nd byte from the port address to the
accumulator

LDA 16-bit address Load accumulator

- 3-byte instruction

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 -Copies the contents of memory location specified
by16 –bit address
- the contents of source is not changed
Example: LDA 2500H
LDAX B/D register pair Load accumulator direct
1-byte instruction
This instruction only uses the BC or DE pair.
– It does not accept the HL pair
LDAX B Copy the 8-bit contents of the memory location
specified by the BC register pair into the
Accumulator
LDAX D -copies the contents of memory location specified
by DE pair register into the accumulator
-The contents of the register pair and the memory
location are not changed
LXI RP, 16-bit data Load register pair(RP) immediate
-3-byte instruction
-loads 16-bit data in the specified register pair
LXI B, 16-bit data Load 16-bit number immediate in BC pair register
LXI D, 16-bit data Load 16-bit number immediate in DE pair register
LXI H, 16-bit data Load 16-bit number immediate in HL pair register
LXI SP, 16-bit data Load 16-bit address immediate in stack pointer
register

The upper two digits are placed in the 1st register of the pair and the
lower two digits(8-bits) in the 2nd register.

LXI B, 30 00
B 30 00 C

Opcode Operand Description

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STA 16-bit Store Accumulator Direct
address
e.g. STA 3502H; store the contents of accumulator to the memory
location 3502H
STAX Reg. Pair Store accumulator indirect
STAX B Copy the contents of accumulator into the memory
location specified by the contents of the B,C register
pair.

STAX D Copy the contents of accumulator into the memory

location specified by the contents of the D,E register
pair.

Opcode Operand Description

LHLD 16-bit address Load H-L register pair direct
 3- byte instruction
 It Copies the contents of the memory location
specified by 16-bit address to register L and copies
the contents of next memory location in register H.
*The contents of source memory location is not
altered.
SHLD 16-bit address Store H-L register pair direct
 3- byte instruction
 Store contents of register L to the memory
location specified by the 16-bit address in the
operands , and contents of H-register are stored in
next memory location by increasing the operand.
 The contents of registers H,L are not changed.
XCHG None -Exchange H and L with D and E
-1-byte instruction
The contents of register H are exchanged with D and
contents of L are exchanged with contents of E
register.
SPHL None Copy H-L pair to the Stack Pointer (SP)
-This instruction loads the contents of H-L pair into SP
register.

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XTHL None Exchange H–L with top of stack
- The contents of L register are exchanged with the
location pointed out by the contents of the SP.
-The contents of H register are exchanged with the
next location (SP + 1).

PUSH Reg. pair Push register pair onto stack

PUSH B -The contents of register pair are copied onto stack.

PUSH D -SP is decremented and the contents of high-order

registers (B, D, H, A) are copied into stack.
PUSH H
-SP is again decremented and the contents of low-
PUSH SP order registers (C, E, L, Flags) are copied into stack.

POP Reg. pair Pop stack to register pair

POP B -The contents of top of stack are copied into register

pair.
POP D -The contents of location pointed out by SP are copied
to the low-order register (C, E, L, Flags).
POP H
-SP is incremented and the contents of location are
POP SP copied to the high-order register (B, D, H, A).

Arithmetic Operations
These instructions perform the following arithmetic operations:

 Addition
 Subtract
 Increment
 Decrement
Opcode operands Description

ADD R/M Add register or memory to accumulator

-Add contents of register(R) or memory(M) to

the contents of accumulator

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 -The result is stored in accumulator.
-If the operand is memory location, its address
is specified by H-L pair.
Example: ADD C or ADD M
ADI 8-bit data Add immediate to accumulator
-The 8-bit data is added to the contents of accumulator.
-The result is stored in accumulator.
-All flags are modified to reflect the result of the
addition.
Example: ADI 35H
ACI 8-bit data Add immediate to accumulator with carry
-The 8-bit data and the Carry Flag (CY) are added to the
contents of accumulator.
-The result is stored in accumulator.
-All flags are modified to reflect the result of the addition
ADC R/M Add register or memory to accumulator with
carry
-The contents of register or memory and Carry
Flag (CY) are added to the contents of accumulator.
-The result is stored in accumulator.
-If the operand is memory location, its address is
specified by H-L pair
-All flags are modified to reflect the result of the addition
Example: ADC D or ADC M
DAD. Reg. Pair Double addition
-Add register pair to H and L register
-the 16-bit contents of specified register pair are added to
the contents of the HL register pair and sum is saved in
the HL register pair.
-The contents of source registers are not altered
DAA None Decimal Adjust Accumulator
-1-byte instruction

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 -The contents of accumulator are changed from binary
value to two 4-digit binary coded decimal(BCD) digits.
-This is only instruction that uses auxiliary
flag(internally) to perform the binary to BCD conversion.
Example:
• DAD RP HL ← HL + RP
• Only instruction that performs 16-bit addition.
• Only CY Flag is affected.
• Takes 3 machine cycles for execution.
E.g.
• DAD B HL ← HL + BC
• DAD D HL ← HL + DE
• DAD H HL ← HL + HL
• DAD SP HL ← HL + SP

DAA – Decimal Adjust Accumulator

• DAA A ← BCD (A) after ADD
– Used after ADD instruction.
– Checks both the Nibbles of Accumulator
• Lower Nibble > 9 OR Flag AC=1 then
Lower Nibble ← Lower Nibble + 6
• Higher Nibble > 9 OR Flag CY=1 then
Higher Nibble ← Higher Nibble + 6
FLAGS: All the flags are affected.
Opcode operands Description
SUB R/M Subtract register or memory from
accumulator
-Subtract contents of register(R) or memory(M) from
the contents of accumulator
-The result is stored in accumulator.
-If the operand is memory location, its
address is specified by H-L pair.

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 -All flags are modified to reflect the result of
subtraction
Example: SUB C or SUB M
SUI 8-bit data Subtract immediate from accumulator
-The 8-bit data is subtracted from the contents of
accumulator.
-The result is stored in accumulator.
-All flags are modified to reflect the result of the
subtraction
Example: SUI 35H
SBB R/M Subtract register or memory from accumulator
with borrow
-The contents of the register or memory location and
Borrow Flag (i.e. CY) are subtracted from the contents of
the accumulator.
-The result is stored in accumulator.
-If the operand is memory location, its address is
specified by H-L pair.
-All flags are modified to reflect the result of
subtraction.
Example: SBB B or SBB M
SBI 8-bit data Subtract immediate from accumulator with
borrow
-The 8-bit data and the Borrow Flag (i.e. CY) is
subtracted from the contents of the accumulator.
-The result is stored in accumulator.
-All flags are modified to reflect the result of
subtraction.
Example: SBI 55 H
INR R/M Increment register or memory by 1
-The result is stored in the same place.
-If the operand is a memory location, its address is
specified by the contents of H-L pair.

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INX Reg.pair Increment register pair by 1
-The contents of register pair are incremented by 1.
-The result is stored in the same place.
Example: INX H
DCR R/M Decrement register or memory by 1
-The result is stored in the same place.
-If the operand is a memory location, its address is
specified by the contents of H-L pair.
DCX Reg.pair Decrement register pair by 1
-The contents of register pair are decremented by 1.
-The result is stored in the same place.
Example: DCX SP

• INR R – Increment the contents of specified register by 1.

– R←R+1
– R can be any of the general purpose registers (A, B, C, D, E, H, L).
– Affects all the flags except CY.
– Register Addressing Mode.
– 1-byte instruction and takes 1 Machine Cycle for execution.
– E.g. INR B, INR A, INR C, INR D, INR E, INR H, INR L
– Amounts to 7 different Opcodes.
• DCR R – Decrement the specified register by 1.
– R←R-1
– R can be any of the general purpose registers (A, B, C, D, E, H, L).
– Affects all the flags except CY.
– Register Addressing Mode.
– 1-byte instruction and takes 1 Machine Cycle for execution.
– E.g. DCR C, DCR H.
– Amounts to 7 different Opcodes.
• INR M – Increment the content of memory (location specified
by HL Pair) by 1.
– ((HL)) ← ((HL)) + 1
– Affects all the flags except CY.
– Indirect Addressing Mode.
– 1-byte instruction
– Takes 3 Machine Cycles (Fetch, Read and Write) for execution.

Dr VP Dubey
 • DCR M – Decrement the indirect byte by 1 (memory location
specified by HL Pair).
– ((HL)) ← ((HL)) – 1
– Affects all the flags except CY.
– Indirect Addressing Mode.
– 1-byte instruction
– Takes 3 Machine Cycles (Fetch, Read and Write) for execution.
Logic Operations
These instructions perform logical operations on data stored in registers,
memory and status flags.
*All operations are performed in context to Accumulator.
 The logical operations are:
 AND
 OR
 XOR
 Rotate
 Compare
 Complement
–ANA, ANI, ORA, ORI, XRA , XRI, RAL, RLC, RAR, RRC, CMP, CPI, CMA
Source: Accumulator and
– An 8-bit number
– The contents of a register
– The contents of a memory location
• Destination: Accumulator
Carry & Auxiliary carry flags are fixed and don’t convey useful
information.
• NOT => CMA

• Bitwise AND => ANA

• Bitwise OR => ORA

Dr VP Dubey
 • Bitwise XOR => XRA

Logical instructions
Opcode operands Description
CMA NONE Complement the contents of ACC.
ANA R/M AND Accumulator with Register/Memory
ANI 8-bit AND Accumulator with an 8-bit number
ORA R/M OR Accumulator with Register/Memory
ORI 8-bit OR Accumulator with an 8-bit number
XRA R/M XOR Accumulator with Register/Memory
XRI 8-bit XOR Accumulator with an 8-bit number
Explanation:
• CMA A ← NOT (A)
– None of the Flags are affected.

– Only Accumulator is complemented.

– E.g. Let Flags are SF=0, ZF=0, PF=1, AC=1, CY=0 and A = 59H

A = 59H = 0101 1001

After CMA, A = 1010 0110 = A6H

FLAGS: SF=0, ZF=0, PF=1, AC=1, CY=0

Flags are same as previous i.e. unaffected.

LOGICAL AND
• ANA R ;A ← A AND R

– Ex. ANA D ; A ← A AND D

• ANA M ; A ← A AND ((HL))

• ANI DATA8 ; A ← A AND DATA8

– Ex. ANI 80H A ← A AND 80H

• CY=0, AC=1, Rest of the flags are affected by the result.

Dr VP Dubey
e.g. ANI F0H A ← A AND F0H
• ANI F0H, would MASK the Lower nibble of A.

• Let A = 45H = 0100 0101

• F0H = 1111 0000

• After ANDing A = 0100 0000 = 40H

• Lower Nibble 0101(05) is Masked.

• FLAGS: SF = 0, ZF=0, PF=0.

LOGICAL OR
• ORA R ; A ← A OR R

• E.g. ORA D ; A ← A OR D

• ORI DATA8 ; A ← A OR DATA8

• E.g. ORI 75H ; A ← A OR 75H

• ORA M ; A ← A OR ((HL))

• CY=0, AC=0, Rest of the flags are affected by the result.

LOGICAL XOR
• XRA R ; A ← A XOR R
– E.g. XRA D ; A ← A XOR D

• XRI DATA8 ;A ← A XOR DATA8

– E.g. XRI 95H ; A ← A XOR 95H
• XRA M ;A ← A XOR ((HL))
• CY=0, AC=0, Rest of the flags are affected by the result.
e.g XRI FFH ; A ← A XOR FFH

Dr VP Dubey
 XRI FFH, would Complement the content of A.

Let A = 45H = 0100 0101

F0H = 1111 1111
After XORing A = 1011 1010 = BAH

Accumulator is Complemented.

• FLAGS: SF = 1, ZF=0, PF=1.

Masking of bits:
 The AND instruction can be used to clear specific destination bits while
preserving others.
 A 0 mask bit clears the corresponding destination bit; a 1 mask bit
preserves the corresponding destination bit.
 The OR instruction can be used to set specific destination bits while
preserving the others.
 A 1 mask bit sets the corresponding destination bit; a 0 mask bit preserves
the corresponding destination bit.
 The XOR instruction can be used to complement specific destination bits
while preserving the others.
 A 1 mask bit complements the corresponding destination bit; a 0 mask bit
preserves the corresponding destination bit.

Complement:
• 1’s complement of the contents of the accumulator.
CMA No operand

 Compare
– Compare the contents of a register or memory location with the contents of
the accumulator for equality, greater than or less than.

CMP R/M Compare the contents of the register or

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 memory location to the contents of the
accumulator.
 if (A) < (register(R))/memory(M)): carry flag is set
 if (A) = (R/M): zero flag is set
 if (A) > (R/M): carry and zero flags are reset.

CPI 8-bit Compare the 8-bit number to the contents

of the accumulator.
• The compare instruction sets the flags (Z, CY, and S).
• The compare is done using an internal subtraction that does not change the
contents of the accumulator. A – (R / M / 8-bit data)

 if (A) < data: carry flag is set

 if (A) = data: zero flag is set
 if (A) > data: carry and zero flags are reset
 Example: CPI 29H
e.g. CMP B ;FLAG ← A - B
– Compare register B with Accumulator
– It performs a subtraction to compare
– Result of the subtraction is not stored i.e. after CMP, both A & B
remains unaffected.
– Result of subtraction is reflected through the Flags i.e. all the flags are
affected by CMP

Example:
Let initially A = 45H and B = 30H
Execution of CMP B means
– Perform A–B = 45H-30H= 15H = (0001 0101)B
After Execution of CMP B

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 – A = 45H and B = 30H
– Flags SF=0, ZF=0, PF=0, AC=0, CY=0.
– Note that both A & B, remains unaffected from compare but
all the flags are affected.
Uses
CY=1  A<B,
CY=0  A≥B,
(CY=0 AND ZF=0)  A>B

• CMP R FLAGS ← A - R
– E.g. CMP D FLAGS ← A - D

• CPI DATA8 FLAGS ← A - DATA8

– E.g. CPI 80H FLAGS ← A - 80H

• CMP M FLAGS ← A - ((HL))

Additional Logic Operations

 Rotate the contents of the accumulator one position to the left or
right.
RLC Rotate the accumulator left.
Bit 7 goes to bit 0 AND the Carry flag.

RAL Rotate the accumulator left through the carry.

Bit 7 goes to the carry and carry goes to bit 0

RRC Rotate the accumulator right.

Bit 0 goes to bit 7 AND the Carry flag.

RAR Rotate the accumulator right through the carry.

Bit 0 goes to the carry and carry goes to bit 7.

Rotating Accumulator(Acc)
• RAR Rotate Acc Right through Carry

Dr VP Dubey
 CY  A7, A7  A6, ….. A1  A0 , A0  CY

• RRC Rotate Acc Right without Carry

A7  A6, ….. A1  A0 , A0  A7 , A0  CY

Example:
RAR Rotate Acc Right through Carry
CY  A7, A7  A6, ….. A1  A0 , A0  CY

Before Instruction ; A= 81H

81H

After RAR A Instruction

40 H

RRC Rotate Acc Right without Carry

Dr VP Dubey
 - Each binary bit of the accumulator is rotated right by one bit
position
A7  A6, ….. A1  A0 , A0  A7 , A0  CY

Before RRC Instruction

A=81H

CY=0 1 0 0 0 0 0 0 1

After 1st RRC Instruction

A=CO H

CY=1 1 1 0 0 0 0 0 0

Rotating Accumulator
• RAL Rotate Acc Left through Carry
CY ← A7, A7 ← A6, ……. A1 ← A0 , A0 ← CY

CY=0 A7 A6 A5 A4 A3 A2 A1 A0

Example
Before RAL Instruction
AA H
CY=0 1 0 1 0 1 0 1 0

Dr VP Dubey
 After 1st RAL Instruction
54 H
1 0 1 0 1 0 1 0 0

After 2nd RAL Instruction

A9 H
0 1 0 1 0 1 0 0 1

 RLC Rotate Acc Left without Carry

- Each binary bit of the accumulator is rotated left by one
position.
CY ← A7, A7 ← A6, ….. A1 ← A0 , A0 ← A7

CY A7 A6 A5 A4 A3 A2 A1 A0

Before RLC Instruction

AA H

0 1 0 1 0 1 0 1 0

After 1st RLC Instruction

55 H
1 0 1 0 1 0 1 0 1

After 2nd RLC Instruction

AA H

1 0 1 0 1 0 1 0
Dr VP Dubey
 Opcode operands Description
CMC None Complement carry

-The Carry flag is complemented.

-No other flags are affected.
Example: CMC.
Opcode operand Description

STC None Set the carry flag

-The Carry flag is set to 1.
-No other flags are affected.
Example: STC.
Branch Instructions
Opcode operands Description

JMP 16-bit address - 3-byte instruction

-The 2nd and 3rd bytes specify the 16-bit

memory address

• JMP – Jump (Go) to an instruction to execute.

E.g. JMP LABEL

• This instruction is used to change the execution sequence.

• LABEL is a symbol placed before instruction where processor
has to jump.
• E.g. JMP HERE
• Next is a simple example for understanding JMP

• JMP ADDRESS – Jump (Go) to ADDRESS to execute an instruction.

• ADDRESS is actually the memory address where instruction
INR A (Last Slide) is stored in memory.
• E.g. JMP 5000H

Dr VP Dubey
 • PCH ← 50H and PCL ← 00H, finally PC=5000H,
showing address of instruction to be executed.
• It takes 3 Machine Cycles for execution.

Conditional JMPs
- The conditional jump instructions allow the microprocessor to take
decisions based on certain conditions indicated by flags
- The jump instruction used only four flags
Carry flag, Zero flag, Sign flag and Parity flag
- Two jump instructions are associated with each flag
Opcode Operand Description
JC 16-bit Jump if a Carry Generated(CF=1)
i.e. Jump on Carry(CF = 1).

JNC 16-bit Jump if Carry Not Generated

i.e. Jump on No carry(CF = 0)
JZ 16-bit Jump on Zero(ZF=1)
JNZ 16-bit Jump on No Zero(ZF=0)
JP 16-bit Jump if Result is Positive
i.e. Jump on SF = 0

JM 16-bit Jump if Result is Minus (Negative),

i.e. Jump on SF = 1.
JPE 16-bit Jump on EVEN Parity
or Jump if Parity is SET, i.e. Jump on PF = 1.

JPO 16-bit Jump on ODD Parity, or Jump if Parity is NOT

SET i.e. Jump on PF = 0.
*All instructions transfer the program to a memory location
Explanation:
• JZ – Jump (Go) to instruction to execute if ZF=1.
E.g. JZ ADDRESS (Memory Address)
• Executes similar to JMP but checks ZF before jump. If ZF=1
then jump otherwise don’t jump.
• JNZ– Jump (Go) to instruction to execute if ZF=0.
E.g. JNZ ADDRESS (Memory Address)

Dr VP Dubey
 • Executes similar to JZ but checks for ZF=0 before
jump. If ZF=0 then jump otherwise don’t jump.

Opcode operand Description

CALL 16-bit address Call unconditionally
- Used to CALL subroutine
-The program sequence is transferred to the memory location specified by
the 16-bit address given in the operand.

-Before the transfer, the address of the next instruction after CALL (the
contents of the program counter) is pushed onto the stack.

Example: CALL 2025 H.

Opcode operand Description
Cx 16-bit address Call conditionally
-The program sequence is transferred to the memory location specified by the 16-
bit address given in the operand based on the specified flag of the PSW.

-Before the transfer, the address of the next instruction after the call (the contents
of the program counter) is pushed onto the stack

Opcode Operand Description

CC 16-bit address CALL a subroutine if a Carry
Generated(CF=1) i.e. CALL on Carry(CF = 1).
CNC 16-bit address Call a subroutine if Carry Not Generated
i.e. Call on No carry(CF = 0)
CZ 16-bit address Call a subroutine on Zero i.e Call on (ZF=1)
CNZ 16-bit address Call a subroutine on No Zero i.e. (ZF=0)
CP 16-bit address Call a subroutine if Result is Positive
i.e. Call on SF = 0

CM 16-bit address Call a subroutine if Result is

Minus(Negative), i.e. Call on SF = 1.
CPE 16-bit address Call a subroutine on EVEN Parity
or Call if Parity is SET,i.e. Call on PF = 1.
CPO 16-bit address Call a subroutine on ODD Parity, or Call if

Dr VP Dubey
 Parity is NOT SET i.e. Call on PF = 0.
Return Instruction
Opcode Operand Description
RET None Return unconditionally

-The program sequence is transferred from the subroutine to the calling

program.

-The two bytes from the top of the stack are copied into the program counter,
and program execution begins at the new address

Opcode operand Description

Rx 16-bit address Return conditionally
-The program sequence is transferred from the subroutine to the calling
program based on the specified flag of the PSW.

-The two bytes from the top of the stack are copied into the program counter,
and program execution begins at the new address.

Opcode Operand Description

RC 16-bit Return from a subroutine if a Carry
Generated(CF=1)i.e. Return on Carry(CF = 1).

RNC 16-bit Return from a subroutine if Carry Not Generated

i.e. Return on No carry(CF = 0)
RZ 16-bit Return from a subroutine on Zero(ZF=1)
RNZ 16-bit Return from a subroutine on No Zero(ZF=0)

RP 16-bit Return from a subroutine if Result is Positive

i.e. Return on SF = 0
RM 16-bit Return from subroutine if Result is Minus
(Negative), i.e. Return on SF = 1.

RPE 16-bit Return from subroutine on EVEN Parity

or Return if Parity is SET,i.e. Return on PF = 1.
RPO 16-bit Return from subroutine on ODD Parity,
or return if Parity is NOT SET i.e. return on PF=0

Dr VP Dubey
Stack, I/O and Machine Control Operations

 IN port-address. ;Input to accumulator from I/O port

[A] <-- [Port]

 OUT port-address ;Output from accumulator to I/O port

[Port] <-- [A]

 PUSH rp ;Push the content of register pair onto stack

 PUSH PSW ;PUSH Processor Status Word
 POP rp ;POP(retrieve) the content of register pair, which
is saved, from the stack
 POP PSW ;Pop Processor Status Word
 HLT No operand (Halt)
 XTHL No operand ;Exchange stack-top with H-L
 SPHL ;Move the contents of H-L pair to stack
pointer
 EI ;Enable Interrupts
 DI ;Disable Interrupts
 SIM ;Set Interrupt Masks
 RIM ;Read Interrupt Masks
 NOP ;No Operation

Microprocessor understands the language of 0’s and 1’s only .This language is
called Machine Language

Assembly language it uses English like words to convey the

action/meaning called as MNEMONICS
for example MOV-MOVE; ADD-Addition, SUB-Subtract etc
*Assembly language is specific to a given processor
 Microprocessor cannot understand a program written in Assembly
language

Dr VP Dubey
  A program known as Assembler is used to convert a Assembly
language program to machine language

Assembly Language Assembler Machine

Program Program Language Code

The "assembly code" for a computer is a textual representation of the machine

code giving the individual instructions to the underlying machine

Assembly language programmes are usually written in a standard form so that they
can be easily translated to machine language by an assembler program (may be self
on cross assembler). In general, the assembly language statements have four
sectors in general known as fields

[Label:] [Mnemonic ] [ Operand [;Comment]

Label field: The first field of ALP statement is the label field. A label is a symbol
used to represent an address that is not specifically known or it is a name to be
assigned to an instruction’s location. The lebel field is usually ended with a colon
(:).

Mnemonic field: This field contains the mnemonic for the instruction to be
performed. Sometimes mnemonics are referred to as operation codes or opcode. It
may consist of pseudo mnemonics.

Operand field: Operand field consists of operand and operands - either constants
or variables with reference to the instruction in the mnemonic field. It may be any
register, data, or address on which the instruction is to be performed.

Comment field: A very important part of an ALP is the comment field. For most
assemblers, the comment field is started with a semicolon (;).

A simple Program

START: IN 00H ; Read Input Switches

OUT 01H ; turn on device according to switch position

Dr VP Dubey
 JMP START ; go back to beginning and read the switches again

An instruction is usually organized as below

 Instruction = Opcode + Operand
 Opcode is binary code that is used by the processor to understand the
instruction.
 Operand is the data item upon which processor has to perform operation, as dictated by
the Opcode.
 The Operand can be specified in a number of ways.
 Data Addressing Mode is actually the method by which an Operand is
specified in the instruction.

Data Addressing modes in 8085 microprocessor

An instruction may access data in variety of methods, called Data Addressing
Modes. Following are the supported addressing modes in 8085.

 Register Addressing.
 Immediate Addressing.
 Direct Addressing.
 Indirect Addressing.
 Implicit Addressing
Register Addressing
The designated data item is present in one of the general purpose register of 8085.
This mode is primarily used to specify variables.

e.g. MOV C, H

 Copy the content of register H into register C.

 The data item to be copied is present in a CPU register H.
 Hence, it is Register Addressing Mode.
 Execution of MOV C, H is explained next.

MOV RD, RS – Copy the content of Source Register (RS) into Destination Register
(RD).
 RS and RD can be any of the general purpose registers (A, B, C, D, E,
H, L).

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  Examples MOV A, D; MOV H, C; MOV A, A etc.
 49 such Opcodes are there for MOV RD, RS.
 This is a 1-byte instruction.
 Takes 1-Machine Cycle (Opcode Fetch) to execute.
 None of the Flags are affected.
Example: MOV RD, RS , ADD R, SUB R, ADC R, SBB R etc

A Simple program:

Register A has data 20H and Register D has data 30H. Write an 8085 ALP
(Assembly Language Program) that copies the data in A to Register E and data in
D to Register L.

MOV E, A ; Copy Register A into Register E.

MOV L, D ; Copy Register D into Register L.

HLT ; Stop

Immediate Addressing
The designated data item immediately follows the Opcode and hence the name
Immediate Addressing. This mode is used to specify the constant data.

e.g. MVI C, 12H

 Copy the 8-bit data 12H into register C.

 The data item (12H) to be copied is present immediately after the
Opcode MVI C.
 Hence, it is Immediate Addressing Mode.
 Execution of MVI C is explained next.
 Example: MVI R, DATA8;
A Simple program

Write an 8085 ALP (Assembly Language Program) that adds two data items 20H
and 30H and store the result in Register C and E.

MVI A, 20H ; Load 20H into Accumulator.

MVI B, 30H ; Load 30H into B.
ADD B ; Add the data items and store result in A.

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 MOV C, A ; Get result in C.
MOV E, A ; Get result in E.
HLT ; Stop.
Example: MVI DATA8 ;ADI DATA8; ACI DATA8; SUI DATA8; SBI DATA8; LXI
Rp

Direct Addressing
In this mode, the designated data item is stored in memory and the memory address
is specified directly in the instruction.

e.g. LDA 5000H, Load accumulator directly from the contents of memory
address 5000H.

A ← (5000H).

e.g. STA 5000H, Store accumulator directly at memory address 5000H.

A → (5000H).

A Simple program

Two data items are stored at locations 2050H and 2051H. Write an 8085 ALP
(Assembly Language Program) to copy these data at memory locations 2100H and
2101H.

LDA 2050H ; Get data from 2050H in A.

STA 2100H ; Store A at 2100.

LDA 2051H ; Get data from 2051H in A.

STA 2101H ; Store A at 2101.

HLT

Write an 8085 ALP to add two data items and store the result in memory.

MVI A, 20H; Load 1st Data in Accumulator.

MVI B, 30H ; Load 2nd Data in B.

Dr VP Dubey
 ADD B ; Add the data.

STA 2052H ; Store result in memory at 2052H.

HLT ; Stop.

LHLD and SHLD

 LHLD 5000H, Load HL Pair directly from memory address 5000H.

 L ← (5000H).

 H ← (5001H).

 SHLD 5000H, Store HL Pair directly at memory address 5000H.

 L → (5000H).

 H → (5001H).

Indirect Addressing
The designated data item is stored in memory and the memory address is specified
through a register pair (i.e. indirectly) in the instruction. This addressing mode is
most suitable for tabular processing.

e.g. MOV B, M

 Copy an 8-bit memory data indirectly into register B, where memory

address is specified by HL Pair.

 B ← ((HL)).

 Since memory address is not the part of instruction it is indirect

addressing.

MOV R, M

 Copy an 8-bit memory data indirectly into register R.

 R ← ((HL)).

MOV M, R

Dr VP Dubey
  Copy an 8-bit data indirectly into memory from register R.
 R  ((HL)).
 R can be any of the 8-bit general purpose registers (A, B, C, D, E, H,
L).
 14 Opcodes are there for both the MOVes.
 They are 1-byte instructions but take 2-Machine Cycles to execute.
 Execution of MOV M, B is explained next.

A Simple Program
Two data items are stored at locations 2500H and 2501H. Write an 8085 ALP to
add two data items stored in memory and store the result in memory at 2502H.
LXI H, 2500H ; Pointer to 1st Data in HL Pair.
MOV A, M ; Get 1st Data in A.
LXI H, 2501H ; Pointer to 2nd Data in HL Pair.
MOV B, M ; Get 2nd Data in B.
ADD B ; Add data.
LXI H, 2502H ; Pointer to Result in HL Pair.
MOV M, A ; Store result in memory at 2502H.
HLT ; Stop
Example: INX Rp ; DCX Rp; ADD M; ADC M; SUB M; SBB M; MVI M,
DATA8; LDAX Rp; STAX Rp

Implicit Addressing
The designated data item is stored in CPU registers or machine component but the
name of operand is not defined in the instruction.

e.g. XCHG, Exchange the content of HL Pair with DE Pair.

 HL  DE.

 Since operand names HL or DE is not specified in instruction it is

Implicit Addressing.

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Timing diagram of 8085 microprocessor
The 8085 microprocessor has 5 basic machine cycles. They are given as below

 Opcode fetch cycle (4T)

 Memory read cycle (3 T)
 Memory write cycle (3 T)
 I/O read cycle (3 T)
 I/O write cycle (3 T)

Opcode Fetch Machine Cycle

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Memory Read Machine Cycle Memory Write Machine Cycle

I/O Read Machine Cycle I/O Write Machine cycle

Timing diagram of INR M

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 Fetching the Opcode 34H from the memory 4105H. (OF cycle)
 Let the memory address (M) be 4250H. (MR cycle -To read Memory
address and data)
 Let the content of that memory is 12H.
 Increment the memory content from 12H to 13H. (MW machine cycle)

Stack and Subroutine:

STACK:
• The stack in an 8085 microprocessor is a set of memory locations in the
R/W memory.

• These memory location are used to store binary information(bytes)

temporarily during the execution of the program.

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 • Stack is defined in the program LXI SP, which loads the 16-bit memory
address in the stack pointer register.

• Stack is initialized at the highest available memory locations.

• Programmer and microprocessor shares the stack.

• Programmer can store and retrieve the contents of a register pair using
PUSH and POP instructions.

• The microprocessor automatically stores the contents of program counter

when a subroutine is called.

LXI SP, 16 bit -Load stack pointer

-load stack pointer register with 16 bit address
PUSH Reg. pair -Push register pair onto stack
-1 byte instruction

PUSH B -The contents of register pair are copied onto stack.

-SP is decremented and the contents of high-order
PUSH D registers (B, D, H, A) are copied into stack.
-SP is again decremented and the contents of low-
PUSH H order registers (C, E, L, Flags) are copied into stack.

PUSH SP

POP Reg. pair Pop stack to register pair

POP B -The contents of top of stack are copied into register

pair.
POP D -The contents of location pointed out by SP are copied
to the low-order register (C, E, L, Flags).
POP H -SP is incremented and the contents of location are
copied to the high-order register (B, D, H, A).
POP SP

• PUSH RP RP may be BC, DE or HL

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 – E.g. PUSH D

(SP-1) ← D
(SP-2) ← E
SP ← SP – 2
• PUSH PSW
(SP-1) ← A

(SP-2) ← FLAG

SP ← SP – 2

─ PUSH takes 3 machine cycles & 12 T-States for execution.

• POP RP RP may be BC, DE or HL

– E.g. POP B
C ← (SP)
B ← (SP+1)
SP ← (SP + 2)
• POP PSW
FLAG ← (SP)

A ← (SP+1)

SP ← SP + 2

─ POP takes 3 machine cycles & 10 T-States for execution.

Example of PUSH and POP

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 A
simple program
Write an 8085 ALP to set Flag Status as SF=1, ZF=0, AC=1, CY=0, and
PF=1

Solution:

Dr VP Dubey
FLAG: SF ZF X AC X PF X CY
1 0 0 1 0 1 0 0 = 94H
MVI B, 00H
MVI C, 94H
PUSH B
POP PSW
SUBROUTINE
• It is a group of instructions, which are written separately from the main
program
• Subroutines are called many times in main program

E.g. Delay programs

• CALL(call a subroutine) and RET(return to main program from a

subroutine) are two main instructions in 8085 to implement the subroutines.

• CALL instruction is used in main program to call a subroutine

• RET instruction is used at the end of the subroutine to return to main

program

CALL 16-bit memory address of a subroutine

; call subroutine unconditionally

• 3-byte instruction that transfers the program sequence to a subroutine
address
• Save the contents of the program counter on the stack
• Decrements the stack pointer register by two
• Jump unconditionally to the memory location specified by the second and
third bytes. The second byte specifies a line number and third bytes specifies
the page number
• This instruction is followed by a return instruction in the subroutine

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Dr VP Dubey