'-'commodore MPS

~ semlcanduct:ar group
6510
[K!J~@@ MICROPROCESSOR
WITH I/O

6510 MICROPROCESSOR WITH I/O

DESCRIPTION

The 651 0 is a low-cost microcomputer system capable of solving a broad range of small-systems
and peripheral-control problems at minimum cost to the user. ~
An 8-bit Bi-Directionall/O Port is located on-chip with the Output Register at ~d,d"Ls0,,000 and
the Data-Direction Register at Address 0 0 0 1. The I/O Port is bit-by-bit proQ(,erl1rf,\:b, .
\\~\\\\\r.\,\\, ., \.

The Three-State sixteen-bit Address Bus allows Direct Memory AC9~~~5'""g~D'~~ multi-
processor systems sharing a common memory. I

The internal processor architecture is identical to the MOS Technolo i~\ ide software
compatibility.

FEATURES OF THE 6510 ... PIN CONFIGURATION

RES 40 \lI2 'N

• 8-Bit Bi-Directional 1/0 Port (111 IN 39 RfW
• Single + 5 volt supply ,/',. iRa 38 DBo
• N channel, silicon gate, depletion lo~,. AEC 37 DB,
• Eight bit parallel processing vee 5 36 DB,
• 56 Instructions A" 6 35 DB,
• Decimal and binary arithrp A. 34 DB,
• Thirteen addressing ma A, 33 DB,
• True indexing capabi(rtY ). A, 9 32 DB.
• Programmable stack ~.)
'~~"11\;\~. ~ 'III;.. vi
l'F')·
#~
A, 10 6510 31 DB,

Variable length ",~{as;:k , "','''/",i

r
A, 11 30 Po
•
• Interrupt cap9·t5il!!~ )h~ 'e."",'" A, 12 29 p,

• 8 Bit Bi-Direcl4Qnal t'l!PtaJ311Ji A. 13 28 P,

• Address,t5,'[~~~,'J'~'
;0"',",\,,\,,!(ang6 of up to 65K bytes A, 14 27 P,

• Direct:t.m~,'~, cc sl:::apability A. 15 26 p,

• Bus c ' p~tro~ with 6800 A", 16 25 p,

• Pipeline;((hf{~ture A" 17 24 P.

• 1 MHz and~~.t7Z operation A., 18 23 P.

• Use with any type or speed memory A" 19 22 A"
vss 20 21 A"

2-36
 MPS
6510
DATA
DIRECTION
REGISTER

F
I
~ P,o
C
PERIPHERAL PERIPHERAL
OUTPUT INTERFACE
REGISTER
L----....I
L-___B_UF_F_E_R__-J~ P7
AEC

Ao
TID
INDEX

r
INTERRUPT
REG~TER
LOGIC
Al J

A2 --
A3 -
A4 - a:
w
u.
As - u.
:::::>
As - III

A7 _. ffia:
o
o
«
As - w
~
~ TIMING J
~CONTROL
As -- ~w
Alo - a:
J:
.....
1l,IN
All - PROCESSORJ
STATUS
0 2 1N

Au -- REGISTER

Al 3
IL....____.... RIW
Al 4 --
Al 5 ~

LEGEND

D=SBITLINE

I = 1 BIT LINE

6510 BLOCK DIAGRAM

2-37
 MPS

6510
6510 CHARACTERISTICS

MAXIMUM RATINGS
RATING
I SYMBOL
1 VALUE
1 UNIT

SUPPLY VOLTAGE Vee -0.3 to + 7.0 Vde This device contains Input protection against
-- damage due to high static voltages or
INPUT VOLTAGE Vln -0.3 to + 7.0 Vde electric fields; however, precautions should
be taken to avoid application of voltages
OPERATING TEMPERATURE TA o to + 70 'c higher than the maximum rating.

STORAGE TEMPERATURE TSTG -55 to + 150 'c

ELECTRICAL CHARACTERISTICS Nee = 5.0V :t 5%, Vss = 0, TA = 0 0

to + 70°C)
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT

Input High Voltage

VIH Vcc - 0.2 Vcc + 1.0V Vdc

Input High Voltage

RES, Po·P,IRQ, Data Vss + 2.0 Vdc
-.-..~-.-~ ~-~~.----I--------. -----+---------j---------I
Input Low Voltage

VIL Vss - 0.3 Vss + 0.2 Vdc

RES, Po'p, IRQ, Data Vss + 0.8 Vdc

-----

Input Leakage Current

(Vln = 0 to 5.25V, Vee = 5.25V)
Logic lin 2.5
0,,0'(in) 100
~---------------~--------+------- ------
Three State (Off State) Input Current
(Vln = 0.4 to 2.4V, Vcc = 5.25V)
Data Lines ITSI 10
-- --------I----~-.-

Output High Voltage

I (lOH = -100!iAdc, Vee = 4.75V)
Data, AO·A15, AMI, Poop, VOH Vss + 2.4 Vdc
~---------------------------------
---~ ---~--
··-r-- ---- - ---.---~---------+------
Out Low Voltage
(IOL = 1.6mAdc, Vcc = 4.75V)
Data, A().A15, AMI, Po'P' VOL Vss + 0.4 Vdc
-- --------~--- - . - - - - - - - - - I-----~--- - - - f - - - - -.----.........-.-----j-- -----------f---~----

Power Supply Current ICC 125 mA

~---------~---------.----------r---------~ I---------------I-~.--- .--...--.--r___----------t-~-----

Capacitance C pF
Vln = 0, TA = 25'C, f = 1MHz)
Logic, PooP, 10

Data 15
AO-A15, AMI Cout 12

0, 30 50
0, 50 80

2-38
 MPS
6510
CLOCK TIMING

~-----------------_--------TCYC------------_____________~

I
1 4 - - - - - - - - - PWHO, - . - -_ _ _ _~

VCC-O.2V VCC-O.2V

0,(ln)

0,(ln)

I. TRWS
THRW

2.0V

R/W

THA

ADDRESS
FROM 2.0V
MPU

O.BV

TADS

2.0V
DATA
FROM
MEMORY
O.BV --f\i;:::.-------1t---r
TDSU
TpDSU

PERIPHERAl.
DATA

AES

ADDRESS _
ENABLE
CONTROL
___________
.

f VCC.-02V

TIMING FOR READING DATA FROM

MEMORY OR PERIPHERALS

2-39
 MPS

6510
CLOCK TIMING

~1
------ PWH0. - - - - - l..

VCC-O.2V

I
I
I
0.(ln) _ _ _ _"" O.2V
I
--i TO
VCC-O.2V
~
I
I
I
0,(ln)
O.2V I

R/W

O.8V

ADDRESS
FROM 2.0V
MPU

O.8V

TAOS

DATA
TO
MEMORY

TMDS

PERIPHERAL
DATA

ADDRESS
ENABLE
CONTROL
f""'- .."

TIMING FOR WRITING DATA TO

MEMORY OR PERIPHERALS

2-40
 MPS
6510
AC CHARACTERISTICS

1 MHz TIMING 1 ,--I_ _2_M_H_z_T_IM_I_NG

_ _-----'

ELECTRICAL CHARACTERISTICS (VCC

CLOCK TIMING
CHARACTERISTIC

Cycle Time
= 5V ± 5%, VSS = OV, TA = 0° -70°C)
Minimum Clock Frequency = 50 KHz

SYMBOL

TCYC
MIN.

1000
TYP. MAX.
f----
MIN.

500
TYP. MAX. UNITS

ns
I
-----------+- ----+ , ' -

Clock Pulse Width 01 PWH01 430 215 ns

(Measured at vcc - 0.2V) 02 PWH02 470 235 ns
~---- -r------ ,--- ,--,-- ------I----~""- -------
Fall Time, Rise Time
(Measured from 0.2V to VCC - 0.2V) 25 15 ns
, ------ - - - - ----'------'------'--
Delay Time between Clocks

~~--
(Measured at 0.2V) ns
--

READIWRITE TIMING (LOAD =1TTL)

CHARACTERISTIC SYMBOL MIN. TYP. MAX. MIN. TYP. MAX. UNITS
"- t- , -
I--- ------- --
ReadlWrite Setup Time from 6508 TAWS 100 300 100 150 ns
----,--- 1--- -
Address Setup Time from 6508 TAOS 100 300 100 150 ns
--- ---
Memory Read Access Time TACC 575 300 ns
---,--- --t--
Data Stability Time Period TDSU 100 50 ns
1-------- - - - - - ,-----, f-------- - - - -
Data Hold Tlme·Read THA ns
1----'---- ----- t----- ------
Data Hold Tlme-Wrlte THW 10 30 10 30 ns
I----~- -------- ~,

Data Setup Time from 6510 TMDS 150 200 75 100 ns

--- ~---- ~~- ---~

Address Hold Time THA 10 30 10 30 ns

-- ----- -- ------
RIW Hold Time THAW 10 30 10 30 ns
-- t------ ~-----, ----
Delay Time, Address valid to
02 positive transition TAEW 180 ns
I---'~

~J
Delay Time, 02 negative transition
to Peripheral Data valid 1 0.5
TpDW
1--------- - - - , f-~--- 1--
Peripheral Data Setup Time TpDSU 300
1------- -f---- f------
Address Enable Setup Time 60 60 ns
TAES
'~ -_._---

2-41
 MPS

6510
SIGNAL DESCRIPTION

Clocks (0" O 2 )
The 6510 requires a two phase non-overlapping clock that runs at the Vcc voltage level.

Address Bus (Ao-A,5)

The three state outputs are TIL compatible, capable of driving one standard TIL load and 130 pf.

Data Bus (00 -0 7 )

Eight pins are used for the data bus. This is a Bi-Directional bus, transferring data to and from the device and
peripherals. The outputs are tri-state buffers capable of driving one standard TTL load and
130 pf.

Reset
This input is used to reset or start the microprocessor from a power down condition. During the time that this line
is held low, writing to or from the microprocessor is inhibited. When a positive edge is detected on the input, the
microprocessor will immediately begin the reset sequence.
After a system initialization time of six clock cycles, the mask interrupt flag will be set and the microprocessor
will load the program counter from the memory vector locations FFFC and FFFD. This is the start location for pro-
gram control.
After Vcc reaches 4.75 volts in a power up routine. reset must be held low for at least two clock cycles. At this
time the R/W signal will become valid.
When the reset signal goes high following these two clock cycles, the microprocessor will proceed with the nor-
mal reset procedure detailed above.

Interrupt Request (IRQ)

This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor
will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask
bit in the Status Code Register will be examined. If the interrupt mask flag is not set, the microprocessor will begin
an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The
microprocessor will then set the interrupt mask flag high so that no further interrupts may occur. At the end of this
cycle, the program counter low will be loaded from address FFFE, and program counter high from location FFFF,
therefore transferring program control to the memory vector located at these addresses.

Address Enable Control (AEC)

The Address Bus is valid only when the Address Enable Control line is high. When low, the Address Bus is in a
high-impedance state. This feature allows easy DMA and multiprocessor systems.

I/O Port (PO-P 7)

Eight pins are used for the peripheral port, which can transfer data to or from peripheral devices. The Output
Register is located in RAM at Address 0001, and the Data Direction Register is at Address 0000. The outputs are
capable at driving one standard TTL load and 130 pf.

Read/Write (R/W)
This signal is generated by the microprocessor to control the direction of data transfers on the Data Bus. This line
is high except when the microprocessor is writing to memory or a peripheral device.

2-42
 MPS

6510
ADDRESSING MODES
ACCUMULATOR ADDRESSING-This form of IMPLIED ADDRESSING-In the Implied ad-
addressing Is represented with a one byte dressing mode, the address containing the
Instruction, Implying an operation on the operand Is Implicitly stated In the operation code
accumulator. of the Instruction.
IMMEDIATE ADDRESSING-In Immediate ad·
dressing, the operand Is contained in the second RELATIVE ADDRESSING-Relative addressing

I
byte of the instruction, with no further memory is used only with branch Instructions and estab-
addressing required. lishes a destination for the conditional branch.

ABSOLUTE ADDRESSING-In absolute ad· The second byte of the Instruction becomes the
dressing, the second byte of the Instruction operand which Is an "Offset" added to the con-
specifies the eight low order bits of the effective tents of the lower eight bits of the program
address while the third byte specifies the eight counter when the counter Is set at the next in-
high order bits. Thus, the absolute addressing struction. The range of the offset is -128 to
mode allpws access to the entire 65K bytes of ad· + 127 bytes from the next instruction.
dressable memory.
INDEXED INDIRECT ADDRESSING-In indexed
ZERO PAGE ADDRESSING-The zero page in- indirect addressing (referred to as [Indirect, Xl),
structions allow for shorter code and execution the second byte of the instruction is added to the
times by only fetching the second byte of the in- contents of the X index register, discarding the
struction and assuming a zero high address byte. carry. The result of this addition points to a
Careful use of the zero page can result in signifi- memory location on page zero whose contents is
cant increase In code efficiency. the low order eight bits of the effective address.
The next memory location in page zero contains
INDEXED ZERO PAGE ADDRESSING-(X, Yin- the high order eight bits of the effective address.
dexing)-This form of addressing Is used in con- Both memory locations specifying the high and
junction with the index register and is referred to low order bytes of the effective address must be
as "Zero Page, X" or "Zero Page, Y." The effective In page zero.
address is calculated by adding the second byte
to the contents of the index register. Since this is INDIRECT INDEXED ADDRESSING-In indirect
a form of "Zero Page" addressing, the content of indexed addressing (referred to as [Indirect, Yl).
the second byte references a location in page the second byte of the instruction points to a
zero. Additionally, due to the "Zero Page" ad- memory location in page zero. The contents of
dressing nature of this mode, no carry is added to this memory location is added to the contents of
the high order 8 bits of memory and crossing of the Y index register, the result being the low order
page boundaries does not occur. eight bits of the effective address. The carry from
this addition is added to the contents of the next
INDEXED ABSOLUTE ADDRESSING-(X, Yin- page zero memory location, the result being the
doxing)-This form of addressing is used in con- high order eight bits of the effective address.
junction with X and Y index register and is re-
ferred to as "Absolute, X," and "Absolute, Y." The ABSOLUTE INDIRECT-The second byte of the
effective address is formed by adding the con- instruction contains the low order eight bits of a
tents of X and Y to the address contained in the memory location. The high order eight bits of that
second and third bytes of the instruction. This memory location is contained in the third byte of
mode allows the index register to contain the in- the instruction. The contents of the fully
dex or count value and the instruction to contain specified memory location is the low order byte
the base address. This type of indexing allows of the effective address. The next memory loca-
any location referencing and the index to modify tion contains the high order byte of the effective
multiple fields resulting in reduced coding and address which is loaded into the sixteen bits of
execution time. the program counter.

INSTRUCTION SET -ALPHABETIC SEQUENCE

ADC Add Memory to Accumulator with Carry LDA Load Accumulator with Memory
AND "AND·' Memory with Accumulator LDX Load Index X with Memory
ASL Shift left One Bit (Memory or Accumulator) LDY Load Index Y with Memory
BGC Branch on Carry Clear LSR Shift One Bit Right (Memory or Accumulator)
BeS Branch on Carry Set
BEQ Branch on Result Zero NOP No Operation
BIT Test Bits in Memory with Accumulator ORA "OR" Memory with Accumulator
BMI Branch on Result Minus
BNE Branch on Result not Zero PHA Push Accumulator on Stack
BPL Branch on Result Plus PHP Push Processor Status on Stack
BRK Force Break PLA Pull Accumulator from Stack
BVC Branch on Overflow Clear PLP Pull Processor Status from Stack
BVS Branch on Overflow Set
CLC Clear Carry Flag ROL Rotate One Bit Left (Memory or Accumulator)
CLD Clear Decimal Mode ROR Rotate One Bit Right (Memory or Accumulator)
RT! Return from Interrupt
CLI Clear Interrupt Disable Bit
RTS Return from Subroutine
CLV Clear Overflow Flag
CMP Compare Memory and Accumulator SBC Subtract Memory from Accumulator with Borrow
CPX Compare Memory and Index X SEC Set Carry Flag
CPY Compare Memory and Index Y SED Set DeCimal Mode
DEC Decrement Memory by One SEI Set Interrupt Disable Status
DEX Decrement Index X by One STA Store Accumulator in Memory
DEY Decrement Index Y by One STX Store Index X in Memory
STY Store Index Y in Memory
EaR "Exclusive·or" Memory with Accumulator
INC Increment Memory by One TAX Transfer Accumulator to Index X
INX Increment Index X by One TAY Transfer Accumulator to Index Y
INY Increment Index Y by One TSX Transfer Stack Pointer to Index X
TXA Transfer Index X to Accumulator
JMP Jump to New Location TXS Transfer Index X 10 Stack Register
JSB Jump to New Location Saving Return Address TYA Transfer Index Y to Accumulator

2-43
 MPS

6510
PROGRAMMING MODEL
7 0 o
L_A===:J ACCUMULATOR A NIV BI D liZ C PROCESSOR STATUS REG "P"
7 0
I Y I INDEX REGISTER Y

X INDEX REGISTER X CARRY 1 ~ TRUE

15 7 0 --.... ZERO 1 :i: RESULT ZERO
r l-~PC~H---+-----~
~_~1~ PCl _~J PROGRAM COUNTER "PC" IRQ DISABLE 1 = DISABLE
8 7 0 ' - - - - - . DECIMAL MODE 1 = TRUE
L:L_~ ~~~=~~==::J STACK POINTER "S" '---------.BRKCOMMANO

'------------.... OVERFlOW 1 = TRUE

~----------1..
~ NEGATIVE 1 = NEG

INSTRUCTION SET - OP CODES, Execution Time, Memory Requirements

....INo
C.-cr::::::J]-
MAHCHOMC-'
n'!&it
III
''104
'E e
t"'"
3 ... 2 ,A 21
~, . "

F' 2 2

3122

MAHCHON ... '

BRANCH ON N""
til
I~I
fOIl·
'il22
•
ISHFIQ II

MAMC;:HONV'" w If 22

.. -
foo'

u.

~~~~~----r;~+-r+~~~~~7b~-+-rr;~+-r+~+4~~~~+1-+~r;~~,~,-----
I I

~'IG·21JUU"IU8 ItII • a

I I
~ ,,
3'532
~~~·~=~~S~·_~'=~S~r;~+-r+~+4~~r+.~~-+~r;~+-r+~+1-r~~-r+1-+~-+-r+----~----
.... ,
.
W'..u. &-t.,..
9+1"5 Mr •

~
fiI

"
0

T
R

I
p(
ta.,., ..
_,

ISellFlg2J
::::n.,
MlllNe.
RTRNSUE
... ,
•• c ..-..-eo-.. "'''' • t 10 • • •112 t,t I·t N •

• • I
ST. 3 8S 3 '2
.. T • II • • • • •

. ~: :,
1'-"
aA'2 I

III ADO' TO N IF PAGE BOUNDARY IS CROSSED

(21 ADO I TO N IF BRANCH OCCURS TO SAME PAGE
ADO 2 TO N IF BRANCH OCCURS TO DIFFERENT PAGE

M MEMORV' P£R EFFEC1W[ ADDRESS M7 MEMORVall?

,4, IF IN DECIMAL MODE Z Fl.AG IS INVALID
loiS MEMORY PER STACK POINTER Me MEMORY BITe
ACCUMULATOR MUST BE CHECKED FOR ZERO RESULT

Note: Commodore Semiconductor Group cannot assume liability for the use of undefined OP Codes

2-44
C= ~~@@
MPS

6510
FFFF

1 V
ADDRESSABLE
EXTERNAL
MEMORY

f
I
.;'

0200
01FF STACK
01 FF . . . - - - - - POINTER
INITIALIZED

I
STACK

Page 1

0100
OOFF

I
0000
Page 0

OUTPUT REGISTER

DATA DIRECTION REGISTER

6510 MEMORY MAP

0001

0000 :=J
I----.---- Used For
Internal
I/O Port

APPLICATIONS NOTES

Locating the Output Register at the internal I/O Port in Page Zero enhances the powerful Zero Page
Addressing instructions of the 6510.

By assigning the 1/0 Pins as inputs (using the Data Direction Register) the user has the ability to change the con-
tents of address 0001 (the Output Register) using peripheral devices. The ability to change these contents using
peripheral inputs, together with Zero Page Indirect Addressing instructions, allows novel and versatile programming
techniques not possible earlier.

COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising at of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.

2-45