Q1: In 8-bit microprocessor, how many opcodes are present?

a) 246
b) 278
c) 250
d) 256

Q2: Which of the following addressing method does the instruction, MOV AX,[BX]
represent?
a) register indirect addressing mode
b) direct addressing mode
c) register addressing mode
d) register relative addressing mode

Q3: For how many times per instruction, the content of the program counter is placed
on the address bus?
a) One time
b) Two times
c) Depends on the memory capacity of the processor
d) Depends on the length of the instruction

Q4: Conditional instructions are independent of which of the following flag?

a) Z
b) AC
c) CY
d) P

Q5: Which of the following is the correct sequence of operations in a microprocessor?

a) Opcode fetch, memory read, memory write, I/O read, I/O write
b) Opcode fetch, memory write, memory read, I/O read, I/O write
c) I/O read, opcode fetch, memory read, memory write, I/O write
d) I/O read, opcode fetch, memory write, memory read, I/O write

Q6: Which of the following is not a property of TRAP interrupt in microprocessor?

a) It is a non-maskable interrupt
b) It is of highest priority
c) It uses edge-triggered signal
d) It is a vectored interrupt
Q7: Which of the following flag is used to mask INTR interrupt?
a) zero flag
b) auxiliary carry flag
c) interrupt flag
d) sign flag

Q8: Which of the following circuit is used as a special signal to demultiplex the address
bus and data bus?
a) Priority Encoder
b) Decoder
c) Address Latch Enable
d) Demultiplexer

Q9: How many flip-flops are there in a flag register of 8085 microprocessor?
a) 4
b) 5
c) 8
d) 10

Q10: Which of the following flag condition is used for BCD arithmetic operations in
microprocessor?
a) Sign flag
b) Auxiliary carry flag
c) Parity flag
d) Zero flag

Q 11: Which is used to store critical pieces of data during subroutines and interrupts?

a) Stack
b) Queue
c) Accumulator
d) Data register

Q12: What does a microprocessor understand after decoding opcode?

a) Perform ALU operation
b) Go to memory
c) Length of the instruction and number of operations
d) Go to the output device
Q13: Which causes the microprocessor to immediately terminate its present activity?
a) RESET signal
b) INTERUPT signal
c) Both
d) None of these

Q14: Which of the following is not a condition flag?

a) Trap flag
b) Auxiliary carry flag
c) Parity flag
d) Zero flag

Q15: In an 8085, what is the content of the Instruction Register (IR)?

a) Op-code for the instruction being executed
b) Operand for the instruction being executed
c) Op-code for the instruction to be executed next
d) Operand for the instruction to be executed next

Q16: READY signal in 8085 is useful when the CPU communicates with
a) A slow peripheral device
b) A fast peripheral device
c) A DMA controller chip
d) A PPI chip

Q17: A memory connected to a microprocessor has 20 address lines and 16 data lines.
What will be the memory capacity?
a) 8 KB
b) 2 MB
c) 16 MB
d) 64 KB

Q18: Which of the following is a non-vectored input?

a) TRAP
b) RST-7.5
c) RST-6.5
d) INTR
Q19: The power failure alarm must be connected to which one of the following inputs
of 8085?
a) INTR
b) TRAP
c) HOLD
d) RST7.5

Q20: In 8085, the DAA instruction is used for

a) Direct Address Accumulator
b) Double Add Accumulator
c) Decimal Adjust Accumulator
d) Direct Access Accumulator.

Q21: What is stored in the H & L general-purpose register?

a) Opcode
b) Address of memory
c) Address of next instruction
d) Temporary data

Q22: The 8085 has two registers known as primary data pointers. These are registers
a) B and C
b) D and E
c) H and L
d) C and D

Q23: Program Counter is made of _________ bits

a) 8
b) 16
c) 32
d) 20

Q24: Suppose registers ‘A’ and ‘B’ contain 50H and 40H respectively. After instruction
MOV A, B, what will be the contents of registers A and B?
a) 40H, 40H
b) 50H, 40H
c) 50H, 50H
d) 60H, 40H
Q25: A High on RESET OUT indicates that?

a) All the registers & counters are being reset

b) Processing can begin when the signal goes high
c) All registers & counters are being reset
d) All registers of CPU are being reset

Q26: In the 8085, which addressing mode is used for accessing the data stored in the
memory location pointed to by the contents of the HL register pair?
a) Immediate
b) Direct
c) Register
d) Register Indirect

Q27: The content of the accumulator after the execution of the following 8085
assembly language program, is:

MVI A, 42H
MVI B, 05H
ADD B
DCR B
JNZ
ADI 25H
HLT

a) 82H
b) 78H
c) 76H
d) 47H

Q28: A microprocessor with a 12-bit address bus will be able to

access

a) 1 K bytes
b) 4 K bytes
c) 8 K bytes
d) 10 K bytes

Q29: The data lines of 8085 microprocessor are multiplexed

with

a) higher order address lines

b) lower order address lines
c) status lines
d) none of the above

Q30: In order to reset the carry without affecting the

accumulator content one has to use,

a) SUB A
b) XRA A
c) ORA A
d) CMC

Q31: Let the content of accumulator and register B be 0000 0100 and 0100 0000
respectively before execution of instruction SUB B. The content of accumulator after
the execution of this instruction will be

a) 00000100
b) 01000000
c) 11000100
d) 010001000

Q32: Let the content of register C be 00000000 before the instruction DCR C is
executed. The content of register C after the after the execution of this instruction will
be

a) 00000000
b) 11111111
c) 00000001
d) None

Q33: The number of output pins in 8085 microprocessors are

a) 40
b) 27
c) 21
d) 19

Q34: The cycle required to fetch and execute an instruction in a 8085 microprocessor
is which one of the following?

a) Clock cycle
b) Memory cycle
c) Machine cycle
d) Instruction cycle

Q35: In an intel 8085A, which is the first machine cycle of an instruction?

a) An op-code fetch cycle
b) A memory read cycle
c) A memory write cycle
d) An I/O read cycle

Q36: During which T-state, contents of OP code from memory are loaded into IR
(Instruction Register)?

a) T1 Opcode fetch
b) T2 OP code fetch
c) T3 OP code fetch
d) T4 OP code fetch

Q37: Assuming LSB is at position 0 and MSB at position 7, which bit positions are not
used (Undefined) in flag register of an 8085 microprocessor?

a) 1, 3, 5
b) 2, 3, 5
c) 1, 2, 5
d) 1, 3, 4

Q38: At the beginning of a fetch cycle, the contents of the program counter are

a) incremented by one.
b) transferred to address bus.
c) transferred to memory address register
d) transferred to memory data register.

Q39: In 8085 microprocessors , let the accumulator contains the value 0AH and
register C contains the value 05H. After CMP C instruction is executed, the
a) zero and carry flags will be set
b) zero and carry flags will be reset
c) zero flag will be set and carry flag will be reset
d) zero flag will be reset and carry flag will be set

Q40: Which of the data transfer is not possible in microprocessor

a) memory to accumulator
b) accumulator to memory
c) memory to memory
d) I/O device to accumulator

(4 each)

Q29: Memory Read Machine Cycle of 8085

Q30: Memory Write Machine Cycle of 8085:

Q31: I/O Read Cycle of 8085

Q32: I/O Read Cycle of 8085

Q 33: Identify the addressing mode

a) MVI A,20H immediate LXI D,10FF H ; immediate

b) LDA 2000H direct SHLD 3000H direct

c) LDAX B indirect MOV M, A indirect

d) CMA implied RRC implied

(2 each)

Q27: List the four Instructions which control the Interrupt structure of 8085

DI ( Disable Interrupts )
EI ( Enable Interrupts )
RIM ( Read Interrupt Masks )
SIM ( Set Interrupt Masks

Q33: If the 8085 adds 87H and 79H, specify the contents of the accumulator and the
status of the S, Z, and CY flag?

Q34: What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing
the following 8085 program?
MVI L, 5DH
MVI L, 6BH
MOV A, H
ADD L

Q35: Write the status of control signals for each of the machine cycle given

Machine IO/M S1 S0 Control

cycle signal
Opcode 0 1 1 RD =0
fetch
M read 0 1 0 RD=0
M write 0 0 1 WR =0
I/O Read 1 1 0 RD=0
I/O write 1 0 1 WR= 0