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B Paper - Mid Term

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32 views2 pages

B Paper - Mid Term

Uploaded by

jsksjs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Department of Electronics and Communication Engineering

Islamic University of Science &Technology, Awantipora.

Midterm Examination (Spring 2024)


Subject: Microprocessor and Microcontroller (ECE 253C) SET B Max Marks: 30 Time: ½ hr
Roll No:______________________________ Students Signature:__________________________
Q 1 – Q20 carry 1 mark each
Q1: Length of the instruction POP D is
a) 1 byte b) 2 byte c) 3 byte d) 4 byte
Q2: Conditional instructions are independent of which of the following flag?
a) Z b) AC c) CY d) P
Q3: Which of the following is not a property of TRAP interrupt in microprocessor?
a) It is a non-maskable interrupt b) It is of highest priority
c) It uses edge-triggered signal d) It is a vectored interrupt
Q4: Which of the following circuit is used as a special signal to demux the address bus and data bus?
a) Priority Encoder b) Decoder c) Address Latch Enable d) Demultiplexer
Q5: Which of the following flag condition is used for BCD arithmetic operations in microprocessor?
a) Sign flag b) Auxiliary carry flag c) Parity flag d) Zero flag
Q6: What does a microprocessor understand after decoding opcode?
a) Perform ALU operation b) Go to memory
c) Length of the instruction and number of operations d) Go to the output device
Q7: Which of the following is not a condition flag?
a) Trap flag b) Auxiliary carry flag c) Parity flag d) Zero flag
Q8: READY signal in 8085 is useful when the CPU communicates with
a) A slow peripheral device b) A fast peripheral device
c) A DMA controller chip d) A PPI chip
Q9: Which of the following is a non-vectored input?
a) TRAP b) RST-7.5 c) RST-6.5 d) INTR
Q10: In 8085, the DAA instruction is used for
a) Direct Address Accumulator b) Double Add Accumulator
c) Decimal Adjust Accumulator d) Direct Access Accumulator.
Q11: The 8085 has two registers known as primary data pointers. These are registers
a) B and C b) D and E c) H and L d) C and D

Q12: Suppose registers ‘A’ and ‘B’ contain 50H and 40H respectively. After instruction MOV A, B,
what will be the contents of registers A and B?
a) 40H, 40H b) 50H, 40H c) 50H, 50H d) 60H, 40H
Q13: In the 8085, which addressing mode is used for accessing the data stored in the memory location
pointed to by the contents of the HL register pair?
a) Immediate b) Direct c ) Register d) Register Indirect

Q14: A microprocessor with a 12-bit address bus will be able to access


a) 1 K bytes b) 4 K bytes c) 8 K bytes d) 10 Kbytes
Q15: In order to reset the carry without affecting the accumulator contents one has to use
a) SUB A b) XRA A c) ORA A d) CMC

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First Floor, Academic Block III, One University Avenue, IUST, Awantipora, J & K 192122
Department of Electronics and Communication Engineering
Islamic University of Science &Technology, Awantipora.

Q16: Let the content of register C be 00000000 before the instruction DCR C is executed. The content
of register C after the after the execution of this instruction will be
a) 00000000 b) 11111111 c) 00000001 d) None

Q17: The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of
the following?
a) Clock cycle b) Memory cycle c) Machine cycle d) Instruction cycle

Q18: During which T-state, contents of OP code from memory are loaded into IR (Instruction
Register)?
a) T1 Opcode fetch b) T2 OP code fetch c) T3 OP code fetch d) T4 OP code fetch
Q19: At the beginning of a fetch cycle, the contents of the program counter are
a) incremented by one. b) transferred to address bus.
c) transferred to memory address register d) transferred to memory data register.
Q20: Which of the data transfer is not possible in microprocessor
a) memory to accumulator b) accumulator to memory
c) memory to memory d) I/O device to accumulator
Q21: List the four Instructions which control the Interrupt structure of 8085 (2marks)
______________________________________ _________________________________________
______________________________________ ________________________________________
Q22: If the 8085 adds 87H and 79H, specify the contents of the accumulator and the status of the S, Z,
and CY flag? (2marks)

Q23: Write the status of control signals for each of the machine cycle given (2marks)

Machine cycle IO/M S1 S0 Control signal


Opcode fetch
Memory write
I/O Read
Bus Idle

Q 24: Identify the addressing mode (4marks)


a) LXI D,10FF H _____________________________ b) SHLD 3000H ________________________
c) MOV M, A ________________________________d) RRC _______________________________

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First Floor, Academic Block III, One University Avenue, IUST, Awantipora, J & K 192122

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