M.Tech.

in Communication Engineering & Signal Processing

DIGITAL DESIGN THROUGH VERILOG

Course Code: 19EC2250 L P C

Prerequisites: Digital Logic Design.

Course outcomes: At the end of the course the student will be able to
CO1: Outline the basic concepts of Verilog language.
CO2: Design and develop different circuits in gate level modelling.
CO3: Develop circuits in data flow level modelling and switch level modelling.
CO4: Design different circuits in behavioral modelling using blocking and non-blocking
statements.
CO5: Design Finite state machines and comprehends concepts of functions, tasks, and
user defined primitives.

UNIT-I 10 Lectures
INTRODUCTION TO VERILOG
Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis,
Functional Verification, System Tasks, Programming Language Interface (PLI), Module,
Simulation and Synthesis Tools, Test Benches. Language Constructs and Conventions:
Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers,
Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Memory,
Operators. System Tasks, Functions, and Compiler Directives: Parameters, Path Delays,
Module Parameters, System Tasks and Functions, File-Based Tasks and Functions,
Compiler Directives, Hierarchical Access, General Observations.

Learning outcomes: At the end of this unit, the student will be able to
1. Summarize the levels of design description (L2)
2. Describe the basic language constructs in VERILOG (L2)
3. Develop Test Bench and verify using simulation (L6)

UNIT-II 10 Lectures
GATE LEVEL MODELING
Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative
Examples, Tri-State Gates, Array of Instances of Primitives, Additional Examples,
Design of Flip-flops with Gate Primitives, Delays, Strengths and Contention Resolution,
Net Types, Design of Basic Circuits.

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Learning outcomes: At the end of this unit, the student will be able to
1. Build Gate primitives with different examples (L6)
2. Design and Development of Flip-Flops with gate primitives (L6)
3. Describe Strengths and Net Types (L2)

UNIT-III 10 Lectures
DATA FLOW LEVEL and SWITCH LEVEL MODELING
Introduction, Continuous Assignment Structures, Delays and Continuous Assignments,
Assignment to Vectors, Operators. Switch Level Modeling Introduction, Basic Transistor
Switches, CMOS Switch, Bidirectional Gates, Time Delays with Switch Primitives,
Instantiations with Strengths and Delays, Strength Contention with Trireg Nets.

Learning outcomes: At the end of this unit, the student will be able to
1. Describe Continuous Assignment Structures and data flow modeling(L2)
2. Design different circuits using Data flow and switch level modeling (L6)
3. Develop switch level circuits (L6)

UNIT-IV 12 Lectures
BEHAVIORAL MODELING
Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct,
Always Construct, Examples, Assignments with Delays, Wait construct, Multiple Always
Blocks, Designs at Behavioral Level, Blocking and Non-blocking Assignments, The case
statement, Simulation Flow. If and if-else constructs, assign-deassign construct, repeat
construct, for loop, the disable construct, while loop, forever loop, parallel blocks,
force-release construct, Event.

Learning outcomes: At the end of this unit, the student will be able to
1. Design different circuits using behavioral modeling(L6)
2. Describe the concept of blocking and non-blocking (L2)
3. Develop different designs using loop constructs (L6)

UNIT-V 8 Lectures
FUNCTIONS, TASKS AND USER-DEFINED PRIMITIVES
Introduction, Function, recursive functions, Tasks, User Defined Primitives (UDP)-
combinational UDPs, sequential UDPs, FSM Design -Moore and Mealy Machines.

Learning outcomes: At the end of this unit, the student will be able to
1. Describe the language constructs like functions, tasks, UDP and FSM design
(L2)
2. Design different circuits using functions and UDP (L6)
3. Develop Moore and Mealy machines using FSM Design (L6)

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Text Books
1. T. R. Padmanabhan and B. Bala Tripura Sundari, Design through Verilog HDL,
WSE, IEEE Press, 2004
2. Bhasker, Jayaram. A Verilog HDL Primer, Star Galaxy Publishing, 1999.

References
1. Michael D. Ciletti, Advanced Digital Design with Verilog HDL, PHI, 2005.
2. John F. Wakerly, Digital Design Principles & Practices, PHI/Pearson Education
Asia, 3rd Ed., 2005.

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