Chapter Four

Processor Design &

Microprogramming

COA lect. Notes 1

Contents
• CPU Basics
• Processor design
• Data path implementation
• Control Unit
• Microprogramming

COA lect. Notes 2

 CPU basics
• The primary function of the CPU is to execute a set of instructions stored
in the computer’s memory.
• A simple CPU consists of a set of registers, an arithmetic logic unit (ALU),
and a control unit (CU).
• The ALU provides the circuitry needed to perform the arithmetic, logical
and shift operations demanded of the instruction set.
• The control unit controls the movement of data and instructions into and
out of the processor and controls the operation of the ALU.
• The CPU fetches instructions from memory, reads and writes data from
and to memory, and transfers data from and to input/output devices.
• A typical and simple execution cycle that a processor can do is:
 The next instruction to be executed, whose address is obtained from the PC,
is fetched from the memory and stored in the IR.
 The instruction is decoded.
 Operands are fetched from the memory and stored in CPU registers, if
needed.
 The instruction is executed.
 Results are transferred from CPU registers to the memory, if needed.

COA lect. Notes 3

CPU components

COA lect. Notes 4

 Processor design/Organization
Data path Implementation:
• The CPU can be divided into a data section and a control section.
• The data section also called data path contains the registers and the ALU.
• The data path is capable of performing certain operations on data items.
• The control section issues control signals to the data path.
• Internal data movements is via local buses and system bus used externally
• Internal data movement among registers and ALU may be carried out
using different organizations including one-bus, two-bus, or three-bus
organizations
• Dedicated data paths may also be used between components that transfer
data between themselves more frequently. For example, the contents of
the PC are transferred to the MAR to fetch a new instruction at the
beginning of each instruction cycle.
• Hence, a dedicated data path from the PC to the MAR could be useful in
speeding up this part of instruction execution.

COA lect. Notes 5

 One Bus CPU Design/Organization
• The CPU registers and the ALU use a single bus to
move outgoing and incoming data
• Since a bus can handle only a single data
movement within one clock cycle, two-operand
operations will need two cycles to fetch the
operands for the ALU.
• Additional registers may also be needed to buffer
data for the ALU.
• This bus organization is the simplest and least
expensive
• But it limits the amount of data transfer that can
be done in the same clock cycle, which will slow
down the overall performance.
COA lect. Notes 6
One bus Implementation

COA lect. Notes 7

 Two Bus Organization/Implementation
• A faster solution than one-bus organization.
• General- purpose registers are connected to both buses.
• Data can be transferred from two different registers to the
input point of the ALU at the same time.
• An additional buffer register may be needed to hold the
output of the ALU when the two buses are busy carrying
the two operands.
• One of the buses may be dedicated for moving data into
registers (in-bus), while the other is dedicated for
transferring data out of the registers (out-bus).
• In this case, the additional buffer register may be used, as
one of the ALU inputs, to hold one of the operands.
• The ALU output can be connected directly to the in-bus,
which will transfer the result into one of the registers.

COA lect. Notes 8

Two bus organization

COA lect. Notes 9

 Three bus Organization
• In a three-bus organization, two buses may be used as
source buses while the third is used as destination.
• The source buses move data out of registers (out-bus),
and destination bus moves data into a register (in-bus).
• Each of the two out-buses is connected to an ALU input
point. The output of the ALU is connected directly to
the in-bus.
• As can be expected, the more buses we have, the more
data we can move within a single clock cycle.
• However, increasing the number of buses will also
increase the complexity of the hardware.

COA lect. Notes 10

Three bus organization

COA lect. Notes 11

 Design of Control Unit (hardwired)
• The control unit directs the system operations by sending control
signals to the data path.
• These signals control the flow of data within the CPU and between
the CPU and external units such as memory and I/O.
• Control buses generally carry signals between the control unit and
other computer components in a clock-driven manner.
• The system clock produces a continuous sequence of pulses in a
specified duration and frequency.
• A sequence of steps (t0 , t1 , t2 , . . .) are used to execute a certain
instruction.
• The op-code field of a fetched instruction is decoded to provide the
control signal generator with information about the instruction to
be executed.
• Step information generated by a logic circuit module is used with
other inputs to generate control signals.
• The signal generator can be specified simply by a set of Boolean
equations for its output in terms of its inputs.
COA lect. Notes 12
COA lect. Notes 13
Example 1
Let us add contents of source registers R1 , R2 , and store the results in destination register R0.
Using the three-bus datapath.
Suppose that the op-code field of the current instruction was decoded to be Inst-x type. The
following table shows the needed step and the control sequence

COA lect. Notes 14

• In Fig below The AND gate ensures that these signals will be issued when the op-code is
decoded into Inst-x and during time period t0 .
•The signals (R1 out-bus 1), (R2 out-bus2), (R0 in-bus), and (Add) will select R1 as a
source on out-bus1, R2 as a source on outbus2, R0 as destination on in-bus, and select the
ALUs add function, respectively.

COA lect. Notes 15

Example 2
Consider previous example using one-bus datapath. Suppose that the op-
code field of the current instruction was decoded to be Inst-x type.
The following table shows the needed steps and the control sequence.

COA lect. Notes 16

•Figure 9 shows the signals generated to execute Inst-x during time periods t0 ,
t1 , and t2 .
• The AND gates ensure that the appropriate signals will be issued when the op-
code is decoded into Inst-x and during the appropriate time period.

COA lect. Notes 17

Example 3
Assume that the instruction set of a machine has three instructions: Inst-x, Inst-y, and Inst-z; and A, B, C,
D, E, F, G, and H are control lines. The following table shows the control lines that should be activated for
the three instructions at the three steps t0 , t1 , and t2 .

The Boolean expressions for control lines A, B, and C can be obtained as follows:

COA lect. Notes 18

COA lect. Notes 19
 Microprogrammed control
• There are mainly two different types of control units:
microprogrammed and hardwired.
• In microprogrammed control, the control signals associated are
stored in special memory units.
•A sequence of microinstructions is called a microprogram, which is
stored in a ROM or RAM called a control memory CM.
• In hardwired control, fixed logic circuits generate the control signals
• Clearly hardwired control is faster than microprogrammed control.
However, hardwired control could be very expensive and
complicated for complex systems.
•microprogrammed control adapts easily to changes in the system
design.
• We can easily add new instructions without changing hardware.
•Hardwired control will require a redesign of the entire systems in
the case of any change.

COA lect. Notes 20

 Microprogrammed control operation
• Microinstructions are fetched from CM the same way program
instructions are fetched from main memory.
• When an instruction is fetched from memory, the op-code field of
the instruction will determine which microprogram is to be
executed.
• Control variables are represented by 0’s and 1’s called control word
• After fetching each microinstruction, the appropriate control lines
will be enabled. Every control line that corresponds to a “1” bit
should be turned on. a “0” bit should be left off.
• Each control word contains a microinstruction, a sequence of
microinstructions constitutes a microprogram
• A microinstruction may specify one or more micro-operations that
will be activated simultaneously. Furthermore, when each control
bit in the microinstruction corresponds to exactly one control line,
the length of microinstruction could get bigger.
• The length of a microinstruction could be reduced if control lines
are coded in specific fields in the microinstruction.
• Decoders will be needed to map each field into the individual
control lines. Clearly, using the decoders will reduce the number of
control lines that can be activated simultaneously. (reduces
parallelism) COA lect. Notes 21
Control Memory

COA lect. Notes 22

 Microprogram Example
• Consider similar to a basic computer
• 20 bits microinstruction format are divided into four
functional parts, three fields F1, F2, F3 specify the
micro operations, and the CD field that selects status
bits
• The control memory has 128 words, hence the address
field is seven bits
• The micro operations divided into three fields with
each three bits specifying a total of 21 micro
operations
• No more than three micro operations can be chosen
for a microinstruction

COA lect. Notes 23

Microinstruction code format

COA lect. Notes 24

 Example
• A microinstruction can specify two
simultaneous microoperations from F2, F3 and
none from F1.
DRM[AR], with F2=100
PC PC+1 , with F3=101, and F1=000

COA lect. Notes 25

Symbols and Binary code for
microinstructions

COA lect. Notes 26

COA lect. Notes 27