Scribd
Upload
37 views4 pages

Unit 4

Uploaded by

akum40915
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
37 views4 pages

Unit 4

Uploaded by

akum40915
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Q1.

Intermediate code
Intermediate code is used to translate the source code into the machine code.
Intermediate code lies between the high-level language and the machine language.
• Using the intermediate code, the second phase of the compiler synthesis phase is
changed according to the target machine.
• If the compiler directly translates source code into the machine code without
generating intermediate code then a full native compiler is required for each new
machine.
• The intermediate code keeps the analysis portion same for all the compilers that's
why it doesn't need a full compiler for every unique machine.

Syntax Trees
A syntax tree is a graphical representation of the source program. Here the node
represents an operator and
children of the node represent operands. It is a hierarchical structure that can be
constructed by syntax rules.

Postfix Notation
Postfix notation is a linear representation of a syntax tree. This can be written by
traversing the tree in the
post order form. The edges in a syntax tree do not appear explicitly in postfix
notation;

Three address
Three address code is a type of intermediate code which is easy to generate and can
be easily converted to machine code. It makes use of at most three addresses and
one operator to represent an expression and the value computed at each instruction
is stored in temporary variable generated by compiler. The compiler decides the
order of operation given by three address code.

1. Quadruple – It is a structure which consists of 4 fields namely op, arg1, arg2 and
result. op denotes the operator and arg1 and arg2 denotes the two operands and
result is used to store the result of the expression.

2. Triples – This representation doesn’t make use of extra temporary variable to


represent a single operation instead when a reference to another triple’s value is
needed, a pointer to that triple is used. So, it consist of only three fields namely op,
arg1 and arg2.

3. Indirect Triples – This representation makes use of pointer to the listing of all
references to computations which is made separately and stored. Its similar in utility
as compared to quadruple representation but requires less space than it.
Temporaries are implicit and easier to rearrange code.

Q2. Directed Acyclic Graph :


The Directed Acyclic Graph (DAG) is used to represent the structure of basic blocks,
to visualize the flow of values between basic blocks, and to provide optimization
techniques in the basic block. To apply an optimization technique to a basic block, a
DAG is a three-address code that is generated as the result of an intermediate code
generation.

Directed acyclic graphs are a type of data structure and they are used to apply
transformations to basic blocks.
The Directed Acyclic Graph (DAG) facilitates the transformation of basic blocks.
DAG is an efficient method for identifying common sub-expressions.
It demonstrates how the statement’s computed value is used in subsequent
statements.

Q3. Backpatching
Backpatching is basically a process of fulfilling unspecified information. This
information is of labels. It basically uses the appropriate semantic actions during the
process of code generation. It may indicate the address of the Label in goto
statements while producing TACs for the given expressions. Here basically two
passes are used because assigning the positions of these label statements in one
pass is quite challenging. It can leave these addresses unidentified in the first pass
and then populate them in the second round. Backpatching is the process of filling
up gaps in incomplete transformations and information.

The main problem with generating code for boolean expressions and flow-of-control
statements in a single pass is that during one single pass we may not know the
labels that control must go to at the time the jump statements are generated.
Q4. CODE GENERATION
The final phase in compiler model is the code generator. It takes as input an
intermediaterepresentation of
the source program and produces as output an equivalent target program. Thecode
generation techniques presented below can be used whether or not an optimizing
phaseoccurs before code generation.

Issues In The Design Of A Code Generator


The following issues arise during the code generation phase:
1. Input to code generator
2. Target program
3. Memory management
4. Instruction selection
5. Register allocation

Q5. Registers allocation


Registers are the fastest locations in the memory hierarchy. But unfortunately, this
resource is limited. It comes under the most constrained resources of the target
processor. Register allocation is an NP-complete problem. However, this problem
can be reduced to graph coloring to achieve allocation and assignment. Therefore a
good register allocator computes an effective approximate solution to a hard
problem.
The register allocator determines which values will reside in the register and which
register will hold each of those values. It takes as its input a program with an
arbitrary number of registers and produces a program with a finite register set that
can fit into the target machine.
Q6. Peephole optimization
Peephole optimization is an optimization technique performed on a small set of
compiler-generated instructions; the small set is known as the peephole
optimization in compiler design or window.

Some important aspects regarding peephole optimization:


1. It is applied to the source code after it has been converted to the target code.

2. Peephole optimization comes under machine-dependent optimization. Machine-


dependent optimization occurs after the target code has been generated and
transformed to fit the target machine architecture. It makes use of CPU registers and
may make use of absolute memory references rather than relative memory
references.

It is applied to a small piece of code, repeatedly.


The objectives of peephole optimization are as follows:
•Improve performance
•Reduce memory footprint
•Reduce code size.

Q7. Flow graph


A basic block is a simple combination of statements. Except for entry and exit, the
basic blocks do not have any branches like in and out. It means that the flow of
control enters at the beginning and it always leaves at the end without any halt. The
execution of a set of instructions of a basic block always takes place in the form of a
sequence.

The first step is to divide a group of three-address codes into the basic block. The
new basic block always begins with the first instruction and continues to add
instructions until it reaches a jump or a label. If no jumps or labels are identified, the
control will flow from one instruction to the next in sequential order.

You might also like