i

MERIT 2016

User Manual
Version 1.0

December 1, 2016

By:

Dr. Mladen Kezunovic, Dr. Jinfeng Ren, Dr. Saeed Lotfifard

© 2016 Mladen Kezunovic, Jinfeng Ren, Saeed Lotfifard

All rights reserved.

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TABLE OF CONTENTS

Page

TABLE OF CONTENTS ............................................................................................ii

LIST OF FIGURES .................................................................................................... vi

LIST OF TABLES ................................................................................................. xxiii

1. INTRODUCTION .......................................................................................... 24

1.1 Scope..................................................................................... 24
1.2 Simulation Modules .............................................................. 24
1.3 System Platform.................................................................... 25

2. POWER SYSTEM FAULT ANALYSIS AND SHORT CIRCUIT

COMPUTATIONS ........................................................................................................... 26

2.1 Symmetrical Components ..................................................... 26

2.1.1 Software Modules ........................................................ 26
2.1.2 Exercises ...................................................................... 27
2.2 Short-Circuit Analysis .......................................................... 33
2.2.1 Software Modules ........................................................ 33
2.2.2 Exercises and Solutions ............................................... 35
2.3 Sequence Networks .............................................................. 43
2.3.1 Transmission Line........................................................ 43
2.3.2 Load ............................................................................. 67
2.3.3 Two-winding Transformer ........................................... 79
2.3.4 Synchronous Machine ................................................. 86
2.3.5 Induction Motor ........................................................... 94
2.4 Matrix Method for Short Circuit Calculation ..................... 103
2.4.1 Software Modules ...................................................... 103
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2.4.2 Exercises and Solutions ............................................. 105

3. BASICS OF PROTECTIVE RELAYING AND DESIGN PRINCIPLES ... 107

3.1 Overcurrent Relaying.......................................................... 107

3.1.1 Software Modules ...................................................... 107
3.1.2 Exercises .................................................................... 108
3.2 Impedance Relaying ........................................................... 116
3.2.1 Software Modules ...................................................... 116
3.2.2 Exercises .................................................................... 117
3.3 Differential Relaying .......................................................... 126
3.3.1 Software Modules ...................................................... 126
3.3.2 Exercises .................................................................... 127

4. MODELING OF DIGITAL RELAY AND POWER SYSTEM ................... 135

4.1 Software Modules for Modeling Elements Library ............ 135

4.1.1 Bias Characteristic ..................................................... 135
4.1.2 Basic Measurements .................................................. 136
4.1.3 Data Acquisition Board.............................................. 137
4.1.4 Directional Element ................................................... 140
4.1.5 Differential Equation based Impedance Measurement142
4.1.6 Digital Filter............................................................... 144
4.1.7 Digital Fourier Transform .......................................... 144
4.1.8 Orthogonal Components ............................................ 146
4.1.9 Symmetrical Components .......................................... 148
4.1.10 Triggering Element .................................................. 150
4.1.11 Universal Comparator .............................................. 151
4.1.12 Phase Selection ........................................................ 154
4.1.13 Vector Group Compensator for 2-Winding
Transformers 156
4.1.14 Zone Comparator ..................................................... 158
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4.2 Interfacing Power System and Relay Models ..................... 159

4.2.1 Analytical Generator .................................................. 159
4.2.2 Fault Signal Generator ............................................... 160
4.2.3 Phasor Generator ....................................................... 162
4.2.4 Spectrum Generator ................................................... 163
4.2.5 Three-phase Phasor Generator ................................... 165
4.3 GUI and Analysis Tools ...................................................... 167
4.3.1 Phasor Display ........................................................... 167

5. DESIGNING AND IMPLEMENTATION OF DIFFERENT

COMMUNICATION SCHEMES AND TRIP LOGIC .................................................. 169

5.1 Introduction......................................................................... 169

5.2 Communication Schemes ................................................... 169
5.2.1 Software Modules ...................................................... 169
5.2.2 Examples.................................................................... 170

6. DESIGNING AND IMPLEMENTATION OF OVERCURENT,

DISTANCE DIFFERENTIAL, AND PILOTPROTECTION SYSTEM ....................... 226

6.1 Line Protection System: Overcurrent Relaying .................. 226

6.1.1 Software Modules ...................................................... 226
6.1.2 Sample Examples....................................................... 227
6.2 Line protection system: differential relaying ...................... 235
6.2.1 Software modules ...................................................... 235
6.2.2 Examples.................................................................... 236
6.3 Line protection system: zone protection ............................. 239
6.3.1 Software modules ...................................................... 239
6.3.2 Examples.................................................................... 240
6.4 Line Protection System: Pilot Protection............................ 250
6.4.1 Software Modules ...................................................... 250
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6.4.2 Test Examples ............................................................ 251

7. DESIGNING AND IMPLEMENTATION OF TRANSFORMER, AND

BASBAR PROTECTION SYSTEM ............................................................................. 258

7.1 Transformer Protection Systems ......................................... 258

7.1.1 Software Modules ...................................................... 258
7.1.2 Examples.................................................................... 259
7.2 Busbar Protection Systems ................................................. 272
7.2.1 Software Modules ...................................................... 272
7.2.2 Sample Examples....................................................... 273
7.3 Summary ............................................................................. 277

8. TESTING OF DIGITAL PROTECTIVE RELAYS ..................................... 278

8.1 Closed-loop Relay Testing .................................................. 278

8.2 Lab Exercises ...................................................................... 280
8.3 Open-loop Relaying Testing ............................................... 292
8.4 Closed-loop and Open-loop Analysis ................................. 294
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LIST OF FIGURES

Page

Figure 1.1 Closed-loop impedance relay testing model ............................................ 25

Figure 2.1 Main interface for symmetrical components - Module 1......................... 26

Figure 2.2 Main interface for symmetrical components - Module 2......................... 26

Figure 2.4 The data entry for the fault model in short-circuit analysis module. ....... 34

Figure 2.5 Exercise 1: The phase voltages at the fault point. .................................... 37

Figure 2.6 Exercise 1: The fault currents .................................................................. 37

Figure 2.7 Exercise 1: Phasors for the voltages at the fault point ............................. 38

Figure 2.8 Exercise 2: The phase voltages at the fault point ..................................... 39

Figure 2.9 Exercise 2: The fault currents .................................................................. 39

Figure 2.10 Exercise 2: Phasors for the fault voltages .............................................. 40

Figure 2.11 Exercise 3: The phase voltages at the fault point ................................... 40

Figure 2.12 Exercise 3: The fault currents ................................................................ 41

Figure 2.13 Exercise 4: The phase voltages at the fault point ................................... 42

Figure 2.14 Exercise 4: The fault currents ................................................................ 42

Figure 2.15 Exerises 5: The network in the abc domain with b-c fault .................... 43

Figure 2.16 Exerises 5: The sequence networks modified for the b-c fault .............. 44

Figure 2.17 Exerises 5: The phase voltages at the fault point ................................... 44

Figure 2.18 Exerises 5: Phasors for the phase voltages at the fault point ................. 45
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Figure 2.19 Simulink model of transposed transmission line (2 rotations)............... 45

Figure 2.20 Simulink model for unsymmetrical transmission line (rotation & twist)46

Figure 2.21 Models of the parallel transmission lines in the abc and symmetrical
components domains ........................................................................................................ 49

Figure 2.22. Model of the parallel transmission lines ............................................... 51

Figure 2.23. Parameters of one branch of zero sequence network ............................ 53

Figure 2.24 The synthesized and measured currents ................................................. 53

Figure 2.25 Zero-sequence network .......................................................................... 54

Figure 2.26 Synthesized and measured currents ....................................................... 55

Figure 2.27 Zero-sequence network .......................................................................... 56

Figure 2.28 Parameters of series impedance in the zero-sequence network ............. 56

Figure 2.29 Parameters of the impedance of line # 2 in zero-sequence network ...... 57

Figure 2.30 Synthesized and measured currents ....................................................... 57

Figure 2.31 Transmission line with wye load ........................................................... 58

Figure 2.32 Transmission line with delta load .......................................................... 59

Figure 2.33 Phase currents into transmission lines ................................................... 62

Figure 2.34 Currents into the wye load ..................................................................... 62

Figure 2.35 Phase currents (asymmetrical generator) ............................................... 63

Figure 2.36 Currents into wye load (asymmetrical generator) .................................. 64

Figure 2.37 Phase currents for delta load .................................................................. 65

Figure 2.38 Currents into delta load .......................................................................... 65

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Figure 2.39 Phase currents for the delta load with asymmetrical generator ............. 66

Figure 2.40 Currents into the delta load with asymmetrical generator ..................... 66

Figure 2.41 Simulink model for the symmetrical wye-connected load .................... 68

Figure 2.42 Measured and synthesized currents ....................................................... 69

Figure 2.43 Model of Symmetrical wye-grounded connected load .......................... 70

Figure 2.44 Measured and synthesized currents ....................................................... 70

Figure 2.45 Model of wye-grounded connected load with ground impedance ......... 71

Figure 2.46 Measured and synthesized currents ....................................................... 72

Figure 2.47 Model of the delta connected load ......................................................... 73

Figure 2.48. Measured and synthesized currents ...................................................... 73

Figure 2.49 Model for the unsymmetrical ungrounded wye-connected load............ 75

Figure 2.50 Model for the unsymmetrical grounded wye-connected load................ 76

Figure 2.51 Model for the unsymmetrical wye-connected load with ground
impedance......................................................................................................................... 77

Figure 2.52 Model for the unsymmetrical delta-connected load............................... 78

Figure 2.53 Yg-∆, ∆-Yg and Yg-Y transformers....................................................... 79

Figure 2.54 Yg-∆ transformer and its sequence networks ........................................ 81

Figure 2.55 The ideal positive transformer of Yg-∆ transformer .............................. 82

Figure 2.56 A power system verifying the sequence networks of the Yg-∆
transformer ....................................................................................................................... 83

Figure 2.57 The Yg-Y transformer and its sequence networks ................................. 84
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Figure 2.58 A power system verifying the sequence networks of the Yg-Y
transformer ....................................................................................................................... 85

Figure 2.59 The ∆-Yg transformer and its sequence networks ................................. 85

Figure 2.60 A power system verifying the sequence networks of the Yg-∆
transformer ....................................................................................................................... 86

Figure 2.61 Positive sequence network ..................................................................... 87

Figure 2.62 Negative Sequence network ................................................................... 88

Figure 2.63 Steady state sequence networks for the synchronous machine.............. 89

Figure 2.64 Positive sequence current waveforms .................................................... 90

Figure 2.65 Negative sequence current waveforms .................................................. 91

Figure 2.66 Positive sequence current waveforms .................................................... 92

Figure 2.67 Negative sequence current waveforms .................................................. 93

Figure 2.68 Steady state unsymmetrical current waveform ...................................... 94

Figure 2.69 Model in abc domain and symmetrical networks for the induction
motor ................................................................................................................................ 95

Figure 2.70 Three-phase stator currents obtained from induction motor and
currents obtained by using sequence networks ................................................................ 96

Figure 2.71 The 3-phase stator currents obtained from induction motor and
currents obtained by using sequence networks ................................................................ 98

Figure 2.72 The simulation module for induction motor .......................................... 99

Figure 2.73 3-phase stator currents obtained from induction motor ....................... 100

Figure 2.74 The model used for Exercise 4 ............................................................. 102

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Figure 2.75 Stator current (phase-c) obtained by from induction motor................. 103

Figure 2.76. Admittance approach to short circuit studies ...................................... 104

Figure 2.77 Impedance approach to short circuit studies ........................................ 104

Figure 3.1. A sample radial network with overcurrent relays. ................................ 107

Figure 3.2. Load current and bus voltage for Exercise 1. ....................................... 109

Figure 3.3 Fault current at F-3 (secondary A at CT-3) ............................................ 110

Figure 3.4 Voltage and current waveforms for Exercise 3 ...................................... 112

Figure 3.5 Voltage and current waveforms for Exercise 4 ...................................... 113

Figure 3.6 Voltage and current waveforms for Exercise 5 ...................................... 114

Figure 3.7 Voltage and current waveforms for Exercise 6 ...................................... 115

Figure 3.8 Current at CT-1 during the fault in the middle of the line 2 (secondary
A). ................................................................................................................................... 116

Figure 3.9. Simple transmission network with impedance relays ........................... 117

Figure 3.10 Current at CT-1 during a fault on the line 1 at 40% of its length......... 121

Figure 3.11 Voltage at bus 1 during a fault on the line 1 at 40% of its length ........ 121

Figure 3.12 Current at CT-2 during a fault on the line 1 at 40% of its length......... 122

Figure 3.13 Voltage at bus 2 during a fault on the line 1 at 40% of its length ........ 122

Figure 3.14 Current at CT-3 during a fault on the line 2 at 10% of its length......... 123

Figure 3.15 Current at CT-4 during a fault on the line 2 at 10% of its length......... 123

Figure 3.16 Current at CT-4 during a fault on the line 2 at 10% of its length......... 124

Figure 3.17 Current at CT-1 during a fault on the line 2 at 10% of its length......... 124
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Figure 3.18 Current at CT-1 during a fault at the bus 2 .......................................... 125

Figure 3.19 Current at CT-4 during a fault at the bus 2 .......................................... 125

Figure 3.20. A simple transmission network with impedance relays ...................... 127

Figure 3.21 Current at CT-3 (secondary) during a fault on the line 2 ..................... 130

Figure 3.22 Current at CT-4 (secondary) during a fault on the line 2 ..................... 130

Figure 3.23 Current at CT-1 (secondary) during a fault on the line 2 ..................... 130

Figure 3.24 Current at CT-2 (secondary) during a fault on the line 2 ..................... 131

Figure 3.25 Current at CT-1 (secondary) during a fault on the line 1 ..................... 131

Figure 3.26 Current at CT-2 (secondary) during a fault on the line 1 ..................... 132

Figure 3.27 Current at CT-3 (secondary) during a fault on the line 1 ..................... 132

Figure 3.28 Current at CT-4 (secondary) during a fault on the line 1 ..................... 132

Figure 3.29 Current at CT-1 (secondary) during a fault on the line 1 with the 152 Ω
fault resistance ................................................................................................................ 133

Figure 3.30 Current at CT-2 (secondary) during a fault on the line 1 with the 152 Ω
fault resistance ................................................................................................................ 133

Figure 4.1 Example for the Bias Characteristic block............................................. 135

Figure 4.2 Operating and Restraining signals ......................................................... 136

Figure 4.3 Output of the block ................................................................................ 136

Figure 4.4 Example for the BM block ..................................................................... 138

Figure 4.5 Simulation results for BMea.mdl ........................................................... 138

Figure 4.6 Data Acquisition Block .......................................................................... 139

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Figure 4.7 Example for the Data Acquisition Block (dabex.mdl) ........................... 139

Figure 4.8 Input and output signals for dabex.mdl.................................................. 140

Figure 4.9 Example for the DE_1 block (DE_1ex.mdl).......................................... 141

Figure 4.10 Simulation results for Dele.mdl ........................................................... 141

Figure 4.11 Example for the DEIM block ............................................................... 142

Figure 4.12 Simulation results for deimex.mdl (Mean post-filtering) .................... 143

Figure 4.13 Simulation results for deimex.mdl (No post-filtering) ........................ 143

Figure 4.14 Example for the DF block (dfex.mdl) .................................................. 144

Figure 4.15 Simulation results for dfttex.mdl ......................................................... 145

Figure 4.16 Example for the DFT block ................................................................. 146

Figure 4.17 Example for the OC block (ocex.mdl) ................................................. 147

Figure 4.18 Simulation of ocex.mdl (magnitude of the signal)............................... 147

Figure 4.19 Simulation of ocex.mdl (angle of the signal) ....................................... 148

Figure 4.20 Example for the SC block (scex.mdl) .................................................. 149

Figure 4.21 Simulation results for scex.mdl............................................................ 149

Figure 4.22 Example for the TR block (trex.mdl) ................................................... 151

Figure 4.23 Simulation result for trex.mdl .............................................................. 151

Figure 4.24 Example 1 for the UC block (ucex1.mdl) ............................................ 152

Figure 4.25 Input-Output plot for simulation of ucex1.mdl .................................... 153

Figure 4.26 Example 2 for the UC block (ucex2.mdl) ............................................ 153

Figure 4.27 Input-Output plot for ucex2.mdl .......................................................... 154

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Figure 4.28 Example for the phase selection block (psex.mdl) .............................. 155

Figure 4.29 Calculation of the orthogonal components of phase voltages in Figure

4.28 ................................................................................................................................. 155

Figure 4.30 Calculation of the orthogonal components of phase currents in Figure

4.28 ................................................................................................................................. 156

Figure 4.31 Example for the VG-2 block (vg2ex.mdl) ........................................... 157

Figure 4.32 Differential currents ............................................................................. 157

Figure 4.33 Restraining currents ............................................................................. 158

Figure 4.34 Example for the Zone Comparator block............................................. 159

Figure 4.35 Example for the Analytical Generator (AGex.mdl) ............................. 160

Figure 4.36 AGex.mdl simulation results................................................................ 160

Figure 4.37 Model for the FSG example (FSGex.mdl)........................................... 162

Figure 4.38 FSGex.mdl Simulation results ............................................................. 162

Figure 4.39 Example for the Phase Generator (PGex.mdl)..................................... 163

Figure 4.40 Simulation results for PGex.mdl .......................................................... 163

Figure 4.41 Example for the Spectrum Generator (SGex.mdl)............................... 165

Figure 4.42 Simulation results for SGex.mdl .......................................................... 165

Figure 4.43 Example for the Three-phase Generator (TPGex.mdl) ........................ 166

Figure 4.44 Simulation results for TPGex.mdl ....................................................... 167

Figure 4.45 Example for a PD block ....................................................................... 168

Figure 4.46 Phasor Display ..................................................................................... 168

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Figure 5.2 Trip and internal signals of relays at both line ends for internal fault at
0.2 p.u. ......................................................................................................................... 171

Figure 5.3 Trip and internal signals of relays at both ends of line for internal fault
at 0.5 p.u. ........................................................................................................................ 172

Figure 5.4 Trip and internal signals of relays at both ends of line for internal fault
at 0.9 p.u. ........................................................................................................................ 173

Figure 5.5 Trip and internal signals of relays at both ends of line for an external
fault at 1.1 p.u. ................................................................................................................ 174

Figure 5.6 Trip and internal signals of relays at both ends of line for internal fault
at 1.5 p.u. ........................................................................................................................ 175

Figure 5.7 Trip and internal signals of relays at both ends of line for internal fault
at 2.1 p.u. ........................................................................................................................ 176

Figure 5.8 Trip and internal signals of relays at both ends of line for internal fault
at 5.0 p.u. ........................................................................................................................ 177

Figure 5.9 Trip and internal signals of relays at both ends of line for internal fault
at -0.5 p.u. ....................................................................................................................... 178

Figure 5.10 Trip and internal signals of relays at both ends of line for internal fault
at 0.2 p.u. ........................................................................................................................ 179

Figure 5.11 Trip and internal signals of relays at both ends of line for internal fault
at 0.2 p.u. ........................................................................................................................ 180

Figure 5.12 Trip and internal signals of relays at both ends of line for internal fault
at -0.5 p.u. ....................................................................................................................... 181

Figure 5.13 Trip and internal signals of relays at both ends of line for internal fault
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at -0.5 p.u. ....................................................................................................................... 182

Figure 5.14 Trip and internal signals of the relays at both ends of line for internal
fault at 2.1 p.u. ................................................................................................................ 183

Figure 5.15 Trip and internal signals of relays at both ends of line for internal
fault at 2.1 p.u. ................................................................................................................ 184

Figure 5.16 Trip and internal signals of relays at both ends of line for internal fault
at 4.2 p.u. ........................................................................................................................ 185

Figure 5.17 Trip and internal signals of relays at both ends of line for internal fault
at 4.2 p.u. ........................................................................................................................ 186

Figure 5.18 Results for fault at x=0.5, zone 1 operates for both relays .................. 188

Figure 5.19 Results for fault at x=1.5, zone 1 operates for Relay A and overreach
for Relay B ..................................................................................................................... 189

Figure 5.20 Results for fault at x=0.8, zone 2 operates for Relay A ....................... 190

Figure 5.21 Results for fault at x=2.2, zone 3 operates for Relay A ....................... 192

Figure 5.22 Results for fault at x=-0.3, starter region operation for Relay A ......... 193

Figure 5.23 Results for fault at x=0.5, one communication channel disabled ........ 195

Figure 5.24 Results for fault at x=0.2, one communication channel disabled ........ 196

Figure 5.25 Plot of relay A and B trip signals (fault location = 0.6) ....................... 198

Figure 5.26 Plot of relay A and B trip signals (fault location =1.2) ........................ 198

Figure 5.27 Plot of relay A and B trip signals (fault location = 1.5) ....................... 199

Figure 5.28 Plot of relay A and B trip signal (fault location = 1.9)......................... 200

Figure 5.29 Plot of relay A and B trip signals (fault location = 2.3) ....................... 200
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Figure 5.30 Plot of relay A and B trip signal (fault location = 2.8)......................... 201

Figure 5.31 Plot of relay A and B trip signals (fault location = 0.6) with failure of
both communication channels. ....................................................................................... 202

Figure 5.32 Plot of relay A and B trip signal (fault location = -0.1) with failure of
both communication channels. ....................................................................................... 203

Figure 5.33 Plot of relay A and B trip signals (fault location = 1.1) with both
communication channels failure..................................................................................... 203

Figure 5.34 Trip signals ........................................................................................... 204

Figure 5.35 Trip signals ........................................................................................... 204

Figure 5.36 Trip signals ........................................................................................... 205

Figure 5.37 Trip signals ........................................................................................... 205

Figure 5.38 Trip signals ........................................................................................... 206

Figure 5.39 Trip signals ........................................................................................... 207

Figure 5.40 Trip signals ........................................................................................... 207

The fault location is set as 0.9, i.e. 90% length of the whole line from the left side.
The relays trip the same as shown .................................................................................. 208

Figure 5.41 Trip signals ........................................................................................... 208

Figure 5.42 Trip and block signal ............................................................................ 209

Figure 5.43 Tripp and block signals ........................................................................ 210

Figure 5.44 Trip and block signals (Example 3) ..................................................... 211

Figure 5.45 Trip and block signals (Example 4) ..................................................... 212

Figure 5.46 The trip and block signals (Example 5) ............................................... 213
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Figure 5.47 Trip and block signals (Example 6) ..................................................... 214

Figure 5.48 Trip signals and block signals (Example 7) ......................................... 215

Figure 5.49 Trip and block signals (Example 8) ..................................................... 216

Figure 5.50 Trip and block signals (Example 9) ..................................................... 217

Figure 5.51 The trip time of the relays in Exercise 1 .............................................. 219

Figure 5.52 The trip time of the relays in Exercise 2 .............................................. 220

Figure 5.53 The trip time of the relays in Exercise 3 .............................................. 220

Figure 5.54 The trip time of the relays in Exercise 4 .............................................. 221

Figure 5.55 The trip time of the relays in Exercise 5 .............................................. 222

Figure 5.56 The trip time of the relays in Exercise 6 .............................................. 222

Figure 5.57 The trip time of the relays in Exercise 7 .............................................. 223

Figure 5.58 The trip time of the relays in Exercise 8 .............................................. 224

Figure 5.59 The trip time of the relays in Exercise 9 .............................................. 224

Figure 5.60 The trip time of the relays in Exercise 10 ............................................ 225

Figure 6.1 Block diagram of the implemented Power System ................................ 226

Figure 6.2 Settings for each protective relay........................................................... 227

Figure 6.3 Results for normal operation. ................................................................. 229

Figure 6.4 Some results for single-phase-to ground fault. ...................................... 230

Figure 6.5 Results for phase-phase fault. ................................................................ 232

Figure 6.6 Results for phase-phase-to ground fault. ............................................... 233

Figure 6.7 Results for three-phase fault. ................................................................. 235

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Figure 6.8 Protection system model in MATLAB .................................................. 236

Figure 6.9 Internal AG fault trip signal ................................................................... 237

Figure 6.10 Protection Scheme of Differential Relay ............................................. 237

Figure 6.11 Internal ag fault trip signal with primary protection out of service ..... 238

Figure 6.12 External ag Fault Trip Signal ............................................................... 238

Figure 6.13 Protection System Overall Structure .................................................... 240

Figure 6.14 Five-zone elements of distance relay ................................................... 241

Figure 6.15 Fault detection ...................................................................................... 242

Figure 6.16 Required parameters for setting a zone ................................................ 242

Figure 6.17 Power swing blocking elements........................................................... 243

Figure 6.18 Line protection system for internal fault.............................................. 244

Figure 6.19 Line protection systems for backward fault ......................................... 245

Figure 6.20 Settings of the relay ............................................................................. 246

Figure 6.21 Magnitude and angle of the measured impedance ............................... 246

Figure 6.22 The trip signal issued by zone1 and zone2 .......................................... 247

Figure 6.23. Directional and CS signals issued by the memory polarization block
and backward zone respectively ..................................................................................... 247

Figure 6.24. The trip signal of zone I and zone II ................................................... 248

Figure 6.25. Impedance and the directional signal .................................................. 248

Figure 6.26. Memory voltage and fault voltage used in memory polarization. ...... 249

Figure 6.27. CS signal for test four. ........................................................................ 250

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Figure 6.28. Distance Relay Scheme....................................................................... 251

Figure 6.29 Phasor testing circuit ............................................................................ 252

Figure 6.30 Phasor testing circuit - replaying waveform from files ....................... 253

Figure 6.31 Transient testing - Two terminal 500kV Line Protection system ......... 254

Figure 6.32 Transmission line model and settings .................................................. 255

Figure 6.33 Communication channel: a) Block diagram; b) Block mask ............... 256

Figure 6.34 Model of the line to generate fault signals ........................................... 257

Figure 6.35 Offline testing of the protection system ............................................... 257

Figure 7.1 Design Diagram of Transformer Protection System .............................. 258

Figure 7.2 Transformer relaying test system ........................................................... 259

Figure 7.3 Current Measurement............................................................................. 260

Figure 7.4 Voltage Measurement ............................................................................. 260

Figure 7.5 Transformer connection (wye-delta-11)................................................. 261

Figure 7.6 Transformer dialog menu ....................................................................... 262

Figure 7.7 Fault dialog menu .................................................................................. 262

Figure 7.8 Differential Relay................................................................................... 263

Figure 7.9 Restricted earth protection relay ............................................................ 263

Figure 7.10 Inverse-time overcurrent relay ............................................................. 264

Figure 7.11 Six-element impedance relay ............................................................... 264

Figure 7.12. Differential relay trip signals .............................................................. 265

Figure 7.13 Differential relay trip signal ................................................................. 266

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Figure 7.14 Differential relay trip signal ................................................................. 266

Figure 7.15 Restricted earth Protection with zero sequence differential trip signal 267

Figure 7.16 Restricted earth protection with inverse-time overcurrent relay trip
signal .............................................................................................................................. 267

Figure 7.17 Six-element impedance relay trip signal .............................................. 268

Figure 7.18 Differential relay trip signal ................................................................. 268

Figure 7.19 Restricted earth protection with inverse-time overcurrent relay trip
signal .............................................................................................................................. 269

Figure 7.20 Differential relay trip signal ................................................................. 269

Figure 7.21 Restricted Earth Protection with Zero sequence differential trip signal269

Figure 7.22 Inverse-time Overcurrent Relay Restricted Earth Protection trip signal270

Figure 7.23 Differential relay trip signal ................................................................. 270

Figure 7.24 Differential relay trip signal ................................................................. 270

Figure 7.25 Differential relay trip signal ................................................................. 271

Figure 7.26 Restricted Earth Protection with Zero sequence differential trip signal271

Figure 7.27 Six-element impedance Relay trip signal ............................................ 271

Figure 7.28 Differential relay trip signal ................................................................. 272

Figure 7.29 Bus Differential Protection System ..................................................... 273

Figure 7.30 Bus protection test System. .................................................................. 274

Figure 7.31 Three-phase Current Transformer ........................................................ 275

Figure 7.32 Fault currents flow through the CT #1 ................................................. 275

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Figure 7.33 Trip signal ............................................................................................ 276

Figure 7.34 Fault currents flow through the CT #4 ................................................. 276

Figure 7.35 Trip and Pickup signals ........................................................................ 277

Figure 8.1 Main menu of overcurrent relay test model ........................................... 278

Figure 8.2 Main menu of impedance relay test model ............................................ 279

Figure 8.3 Closed-loop overcurrent relay test model .............................................. 279

Figure 8.4 Closed-loop impedance relay test model ............................................... 280

Figure 8.5 Relay OR-3 trip signal ........................................................................... 281

Figure 8.6 Fault current at CT-3 (secondary A) ...................................................... 282

Figure 8.7 Relay OR-2 trip signal ........................................................................... 283

Figure 8.8 Fault current at CT-2 (secondary A) ...................................................... 283

Figure 8.9 Relay OR-1 trip signal ........................................................................... 284

Figure 8.10 Fault current at CT-1 (secondary A) .................................................... 285

Figure 8.11 Relay OR-2 trip signal ......................................................................... 286

Figure 8.12 Fault current at CT-2 (secondary A) .................................................... 286

Figure 8.13 Relay ZR-1 trip signal .......................................................................... 287

Figure 8.14 Fault current at CT-1 (secondary A) .................................................... 288

Figure 8.15 Relay ZR-1 trip signal .......................................................................... 289

Figure 8.16 Fault current at CT-1 (secondary A) .................................................... 289

Figure 8.17 Relay ZR-2 trip signal .......................................................................... 290

Figure 8.18 Fault current at CT-2 (secondary A) .................................................... 291

 xxii

Figure 8.19 Relay ZR-1 trip signal .......................................................................... 292

Figure 8.20 Fault current at CT-1 (secondary A) .................................................... 292

Figure 8.21 Open-loop overcurrent relay testing model ......................................... 293

Figure 8.22 Open-loop impedance relay testing model .......................................... 293

 xxiii

LIST OF TABLES

Page

Table 4.1 Oscillatory components ........................................................................... 161

Table 4.2 Signal harmonics ..................................................................................... 164

Table 4.3 Parameters of phase signals ..................................................................... 166

 24

1. INTRODUCTION

1.1 Scope

In this manual, supplement materials for the accompanying book “Design,

Modeling and Evaluation of Protective Relays: Hands-on Experience” are provided.
Additional examples and exercises are to enable the reader to further understand and
practice the concept of protection design, application and validation.

1.2 Simulation Modules

An example of the closed-loop relay testing is described to introduce the concept

of closed-loop relay testing. Figure 1.1 shows a predefined SIMULINK model to
practice the implementation of distance relay for protecting an EHV electric power
network. This file is OIRT.mdl (On-line Analysis). The application performance of the
protection schemes can be verified in a simple way that places disturbances on
transmission lines with various conditions. In this model:

• A three-phase impedance relay model is used to protect a transmission line.

• The 238 kV transmission network is modeled.

• Instrument transformers are used to scale down the voltages and currents for
relays.

• Circuit breakers are connected to the trip outputs of corresponding relays.

• Output display elements are used as indicators of status changes.

The exercise consists of

• Configure the impedance relays to implement three-zone (or four-zone)

protection scheme.

• Place faults at different locations (with different type, resistance, inception

angle) to study the relay operating characteristics and verify the protection
 25

scheme.

• Simulate some disturbances occurring in real power system that may confuse
the relay, such as switching operation, power swing and load encroachment.
Observe the relay behavior and recommend the relay settings.

• Simulate external faults for verifying the back-up protection. Understand idea
of the relay coordination and learn the method of coordinating settings.

From this example, one can learn 1) relay design and application issues; 2) relay
configurations and settings; 3) testing methods for verifying the relay design and
protection scheme.

Figure 1.1 Closed-loop impedance relay testing model

1.3 System Platform

The minimum requirement for a computer to run the provided software package is
understanding MATLAB/SIMULINK (which is not provided in the package). The
installation of the SimPowerSystem in SIMULINK is required. The MATLAB version
needed is 2015 or newer.
 26

2. POWER SYSTEM FAULT ANALYSIS AND SHORT CIRCUIT

COMPUTATIONS

2.1 Symmetrical Components

2.1.1 Software Modules

Two software simulation modules SCo1.mdl and SCo2.mdl are available for
unbalanced networks. Their interfaces are shown in Figure 2.1 and Figure 2.2
respectively. Both modules demonstrate the use of the symmetrical components for
analysis of unbalanced networks. In the first module, a system with an unbalanced
source is analyzed; in the second module a system with a single line-to-ground fault is
analyzed.

Figure 2.1 Main interface for symmetrical components - Module 1

Figure 2.2 Main interface for symmetrical components - Module 2

 27

Follow the steps below to active the procedure to execute the models:

1) Open MATLAB.
2) Type SCo1 or SCo2 to run the first or second module, respectively.

In each case, a new window will appear in the screen. To run simulation, just click
on the run button of the top bar.

Two MATLAB scripts named abc2pnz.m and pnz2abc.m are available as well for
converting phasors between the three-phase domain and three-sequence domains. The
practical tips for editing are:

• To view and edit parameters of the network (such as an impedance), double

click on the corresponding icon. A dialog menu will be displayed. Enter the
required parameters and close the window.
• To copy and paste an element, use the common sequence CTRL+C, CTRL+V.
• To connect two elements, draw a line between their terminals,
• For the electric part of the model (power system and sequence networks), use
busbars if more than two terminals are to be connected.

2.1.2 Exercises

Exercise 1

1) Open the case SCo1.mdl.

2) The default values for this example are:

Voltage source:

Va=1∠00

Vb=0.8∠-1100

Vc=1.1∠1600

Line impedance: Za=Zb=Zc=0.0347+j0.1970 pu

 28

Load impedance: Zla=Zlab=Zlc=0.1736+j0.9848 pu.

Zg=0.0695+j0.3939 pu.

3) Initiate the simulation with these values and display phasor for Iabc in the original
network.

The phasor display for this case shows the following results:

4) Initiate the simulation with these values and display phasor for Vabc in the original
network.

The phasor display for this case shows the following results:
 29

5) Enter the values of the sequence components of the voltages obtained in the
previous step in the option “Network with source decomposed in symmetrical
components”. Run the simulation.

From the display in the previous step we have V a+ , V a− , V a0 . The other sequence

values can be obtained as follows:

Vb+ = a 2Va+ = 0.92∠(17.8 −120)

Vc+ = aVa+ = 0.92∠(17.8 + 120)

Vb− = aVa− = 0.27∠(−34.8 + 120)

Vc− = a 2Va− = 0.27∠(−34.8 − 120)

Vb0 = Vc0 = Va0 = 0.16∠ − 129.3

It can be noted that the results match with the ones obtained in the original
three-phase network, therefore this representation is equivalent.

6) Enter the values for the sequence voltages obtained in step 4), in the positive,
negative and zero sequence networks as well as in the connected symmetrical
networks. Run the simulation.

If the voltages and currents in abc domain obtained in the block named
"Connected sequence networks" are compared with the ones obtained with the original
three-phase system, it can be observed that the results match. Therefore, it can be
concluded that the sequence networks can be used to analyze unbalanced systems.

Exercise 2

1) Open the case SCo2.mdl.

2) The default values for this example are:

Voltage source:
 30

Va=1∠00

Vb=1∠-1200

Vc=1∠1200

Line impedance: Za=Zb=Zc=0.0347+j0.1970 pu

Load impedance: Zla=Zlab=Zlc=0.1736+j0.9848 pu.

Zg=0.0695+j0.3939 pu.

Zf= 0.0174+j 0.0985 pu.

3) Obtain the phasors for abc and sequence domain for the voltages at the fault using
the phasor display. Enable the phasor display for the Vabc phasors and disable the
rest of the phasor displays, then run the simulation.

The phasor display shows the following results:

4) Obtain the phasors for abc and sequence domain for the fault currents. Enable the
 31

phasor display for the Ifabc phasors and disable the rest of the phasor displays, then
run the simulation.

The phasor display shows the following results:

5) Enter the values for the fault currents in abc-domain obtained in the previous step
in the option named “fault connection in symmetrical components”. Run the
simulation and observe the results.

We know that:

I b+ = a 2 I a+ = 0.29∠(−80 − 120)

I c+ = aIa+ = 0.29∠(−80 + 120)

I b− = aIa− = 0.29∠(−80 + 120)

I c− = a 2 I a− = 0.29∠(−80 − 120)

I b0 = I c0 = I a0 = 0.29∠ − 80
 32

Compare the measured voltage and current phasor measurements obtained in the
original network and in the block named "fault connection in symmetrical
components”. It can be noted that the results from both networks match, therefore both
circuits are equivalent.

6) Enter the values of the symmetrical components of the fault currents obtained
before, in the positive, negative and zero sequence networks as well as in the
connected symmetrical networks. Run the simulation and observe the results.

The values for the sources for the negative and zero sequence are zero as the
source of the original sequence is balanced. The value for the positive sequence
voltage source is 1∠00.

Compare the measured voltage and current phasor measurements obtained in the
original network and in the positive, negative and zero sequence networks, as well as
in the block named "fault connection in symmetrical components”. Since the results
match, it can be concluded that the sequence networks can be used to analyze
unbalanced systems.

Exercises

1. Repeat Exercise 1, with the values shown below. Report your results.

Voltage source:

Va=1∠00

Vb=0.7∠-1150

Vc=1.2∠1700

Line impedance: Za=Zb=Zc=0.0347+j0.1970 pu

Load impedance: Zla=Zlab=Zlc=0.1736+j0.9848 pu.

Zg=0.0695+j0.3939 pu.
 33

2. Repeat Exercise 2, with the values shown below. Report the solutions that you
obtained.

Voltage source:

Va=1∠00

Vb=1∠-1200

Vc=1∠1200

Line impedance: Za=Zb=Zc=0.05+j0.2 pu

Load impedance: Zla=Zlab=Zlc=0.2+j1 pu.

Zg=0.0950+j0.4 pu.

Zf= 0.0274+j 0.0985 pu.

2.2 Short-Circuit Analysis

2.2.1 Software Modules

A software module for short-circuit analysis interface is shown in

Figure 2.3. This module provides two options. The option on the left hand side is a
simple three-phase one-machine power system model. Three ideal voltage sources
supply the load via two three-phase impedances connected in series. A fault point is
created between the two impedances. The voltage source works as an ungrounded Y,
while the load works as a grounded Y. A Single-Line-to-Ground (SLG) fault is placed
in the system. The voltages in all three phases at the fault point are measured and
displayed. The values of the voltages can be viewed in the time domain and in the
phasor domain. In the latter case, the abc-phasors are displayed in a figure at the end of
the simulation; the corresponding symmetrical components are also displayed.
 34

Figure 2.3 Main interface for short-circuit analysis

To execute the module for short-circuit analysis simply run MATLAB and type
SCo3. The models can be edited in a very easy and convenient way. The practical tips
for editing are:

• To open the display window double click on the scope icon,

• To view and edit parameters of the element (such as the impedance) double
click on the element’s icon; Figure 2.4 presents an example of the fault model.
Two parameters may be entered here, the fault resistance and incidence time;
note that the mathematical expressions are allowed in the data entry windows,
• To copy and paste an element use the common sequence CRTL+C, CRTL+V,
• To connect two elements draw a line between their terminals,
• For the electric part of the model (power system and sequence networks) use
busbars if more than two terminals are to be connected.

Figure 2.4 The data entry for the fault model in short-circuit analysis module.
 35

2.2.2 Exercises and Solutions

Exercise 1:

Analyze the original network. Explain the configuration, parameters and the
connections of the sequence networks. Run the case. Observe the signals in the time
and phasor domain in the original network and in the sequence networks. Do the
measured and synthesized voltages and currents match?

The voltage source in the positive sequence network corresponds to the generator
in the phase a of the original three-phase network. Thus, the appropriate data are
copied to the driving force block in the positive sequence symmetrical network. The
impedance in the network between the driving force and the fault point should match
the positive sequence impedance of the original network, and therefore, 0.01 + j0.05 is
entered. The impedance on the right hand side from the fault point reflects the line and
the load in the three-phase system, and therefore, the following is entered (0.01+0.72)
+ j(0.05+0.54). The negative sequence network is composed in the same way. Since
the three-phase source is completely symmetrical, there is no negative sequence
driving force in the negative sequence network. The zero-sequence network does not
contain the driving force for the same reason. In addition, the groundings of both the
source and the load in the original system must be reflected in the zero-sequence
network. Therefore, the loop on the left hand side of this network is not closed.

A SLG fault is modeled. The sequence networks are connected in series. The loop
is closed by the fault resistance equal to three times the original fault resistance.

The current flowing in the connected symmetrical networks corresponds to the real
fault current if multiplied by three (the gain element included).

Figure 2.5 presents the measured and synthesized values of the phase voltages at
 36

the fault location in time domain. The synthesized values are obtained by connecting a
block that performs the conversion from sequence domain to phase domain to the
results obtained from the sequence networks. Figure 2.6 displays the fault current: the
value in the three-phase system and the value from the sequence networks. Figure 2.7
shows the phasors for the voltages at the fault point. The phasors for the zero, positive
and negative-sequence voltages are obtained graphically in the display shown, as
follows:

The zero-sequence voltage is one third of the vector sum of the voltage phasors for
phases a, b and c. The positive-sequence phasor is one third of the vector sum of the
phasor in phase a, plus the phasor in phase b, rotated by 120 degrees, plus the phasor in
phase c, rotated by another 120 degrees. Finally, the negative-sequence phasor is one
third of the vector sum of voltage in phase a, plus the phasor in phase b, rotated by 120
degrees, plus the phasor in phase c, rotated by another 120 degrees.

Both the voltages and the currents match perfectly. This illustrates the following:

• Instead of a three-phase system one may analyze three simple one-phase

networks,
• Instead of computing phase voltages and currents one may compute the
symmetrical values and then convert them to the phase signals,
• Both the parameters and the connections of the symmetrical components must
match the original system data.
 37

Figure 2.5 Exercise 1: The phase voltages at the fault point.

Figure 2.6 Exercise 1: The fault currents

Exercise 2:

Assume the load is grounded via a 1 p.u. resistance. Modify both the model of the
three-phase network and the sequence networks to reflect this situation. Check your
solution by simulations.

To edit the original network model, move away the grounding icon in the load
model. Click on the connection between the load busbar and the grounding icon and
remove the connection by pressing the del key. Copy one of the impedance icons (click
to mark, CRTL+C, CRTL+V) and connect it between the unconnected terminal of the
 38

busbar and the grounding icon. Double click on the grounding impedance and enter the
required data.

Figure 2.7 Exercise 1: Phasors for the voltages at the fault point

The change in the grounding of the load affects only the zero-sequence network.
The new value of the grounding resistance (3 times 1) adds to the right hand side
impedance in the zero-sequence network (change the parameter to 0.01+0.72+3*1).

Figure 2.8 and Figure 2.9 display the phase voltages and fault currents from the
original three-phase network and from the sequence components model. They match
confirming the above solution. The phasors for the voltages at the fault location are
shown in Figure 2.10.
 39

Figure 2.8 Exercise 2: The phase voltages at the fault point

Figure 2.9 Exercise 2: The fault currents

Exercise 3:

Assume the generator in the three-phase network is grounded via 0.2 p.u. fault
reactance. Modify the original network and sequence networks to reflect this situation.
Prove your solution by simulation.

The change affects only the zero-sequence network. Since the generator is
grounded the sequence network will be closed on the left hand side. Again, the
grounding impedance multiplied by 3 will be inserted there. Thus, modify the left hand
side impedance in the zero-sequence network to be 0.01+j (0.05+3*0.2).
 40

Figure 2.10 Exercise 2: Phasors for the fault voltages

Figure 2.11 and Figure 2.12 display the phase voltages and fault currents from the
original three-phase network and sequence network model respectively. They match
confirming the above solution is correct.

Figure 2.11 Exercise 3: The phase voltages at the fault point

 41

Figure 2.12 Exercise 3: The fault currents

Exercise 4:

"Revert" to the original configuration. Assume the generator produces the

following voltages: Va = 1.0 / 0 deg; Vb = 1.1 / -115 deg and Vc = 0.8 / 127 deg. Enter
this data. Modify the sequence networks to reflect this situation. Check your solution
by simulation.

The generator’s voltages should be transformed into the symmetrical components.

This step gives: V0 = 0.121 / -81.48 deg; V1 = 0.965 / 3.83 deg and V2 = 0.058 / 71.07
deg. Note that in this case the voltages sources for the negative and zero sequence are
nonzero. The zero-sequence source, however, does not matter since the network is
open due to the ungrounded neutral point of the generator. Figure 2.13 and Figure 2.14
prove the solution is correct.
 42

Figure 2.13 Exercise 4: The phase voltages at the fault point

Figure 2.14 Exercise 4: The fault currents

Exercise 5:

Revert” to the original configuration. Simulate a LLG fault (b-c) with the
resistance of 0.001 p.u.. Arrange the sequence networks. Check your solution by
simulation.

Figure 2.15 displays the correct connection in abc domain and Figure 2.16 shows
the connections in the symmetrical networks. The fault resistance in the sequence
networks equals the actual fault resistance. The zero-sequence network is disconnected.
Figure 2.17 compares the phase voltages. The steady state values (phasors) match. In
 43

the transient state, there are some differences that result from the conversion 012 ->
abc. The phasor voltages at the fault point are shown in Figure 2.18.

Figure 2.15 Exerises 5: The network in the abc domain with b-c fault

2.3 Sequence Networks

2.3.1 Transmission Line

2.3.1.1.Transposed and Rotated Lines

Software Modules

Two modules of the symmetrical networks for a three-phase transmission line are
shown in Figure 2.19 (lineTran.mdl)and in Figure 2.20 (lineTwist.mdl). The first
module shows the model of a transposed transmission line (two rotations) and may be
used to model a fully symmetrical as well as an unsymmetrical line. The second
module describes a transmission line with one rotation and one twist. This model can
be used to model an unsymmetrical line only.
 44

Figure 2.16 Exerises 5: The sequence networks modified for the b-c fault

Figure 2.17 Exerises 5: The phase voltages at the fault point

 45

Figure 2.18 Exerises 5: Phasors for the phase voltages at the fault point

Figure 2.19 Simulink model of transposed transmission line (2 rotations)

 46

Figure 2.20 Simulink model for unsymmetrical transmission line (rotation & twist)

Each model consists of:

• Symmetrical 3-phase voltage source at node A,

• Unsymmetrical 3-phase voltage source at node B,
• Three independent sections of transmission line.

The parameters of every element described above are stored in the ASCII file
data.txt (the format of the data is described in the MATLAB script files: “lineTw.m”
and “lineTr.m”). The user can change the values of the parameters by simply
modifying the file data.txt. Originally, the file “data.txt” contains parameters of a 69
kV, 40 miles length transmission line.

To run the simulation, first it is necessary to calculate all parameters that are going
to be used by the Simulink model. These calculations are done using the MATLAB
 47

scripts: “lineTr.m” and “lineTw.m”, for transposed line and rotated/twisted line
respectively. After all needed calculations are completed these scripts create the output
files with the results of the computations and the execution of the corresponding
simulation. The ASCII files generated are outputtransp.txt and outputtwist.txt. The
format for the input data is shown below:

Raa Xaa - self impedances in Ohm per mile

Rbb Xbb

Rcc Xcc

Rab Xab - mutual impedances in Ohm per mile

Rbc Xbc

Rac Xac

s1 s2 s3 - length of line sections in miles

EA angEA – magnitude [V] and angle [0] of symmetrical voltage source A

EBa angEBa - magnitude and angle [0] of unsymmetrical source B-phase a

EBb angEBb - magnitude and angle [0] of unsymmetrical source B - phase b

EBc angEBc - magnitude and angle [0] of unsymmetrical source B - phase c

Exercises and Solutions

Exercise 1:

Symmetrical transposed line. Assume that length of all the sections is equal, and
the voltage source at bus B is balanced.

Exercise 2:

Symmetrical transposed line. Assume that the length of all the sections is equal,
 48

and the voltage source at bus B is unbalanced (different magnitudes and angles in each
phase).

Exercise 3:

Repeat Examples 1 and 2 for different lengths for the line sections (e.g. in ratio 0.2:
0.3: 0.5).

Exercise 4:

Symmetrical rotated and twisted line. Assume that the lengths of all the sections
are equal, and the voltage source at bus B is balanced.

Exercise 5:

Unsymmetrical rotated and twisted line. Assume that length of each section is
equal to each other, and the voltage source at bus B is unbalanced (different
magnitudes and angles).

Exercise 6:

Repeat Examples 4 and 5 for different lengths of line sections (e.g. in ratio 0.2: 0.3:
0.5).

Exercise 7:

Repeat Exercise 4 and 5 for different type of twist (1-3-2, 3-2-1, 2-1-3). Which
case does provide the smallest unbalanced of the line?

Exercise 1-7:

In every example (1-7), the synthesized line currents and measured currents should
match very well. Obviously there are small differences because of numerical properties
of using the solving method. For example, errors are smaller when iteration step is
short, but in this case the simulation time becomes very long. Also the choice of the
 49

solving method influences the accuracy of the computations. It can be checked in the
models that the differential currents are very small.

2.3.1.2.Parallel Lines

Software Modules

The Simulink model used for the demonstration of symmetrical components of

parallel lines is shown in Figure 2.21(paralines_2.mdl).

Figure 2.21 Models of the parallel transmission lines in the abc and symmetrical
components domains

The model of the parallel lines in abc domain has three groups of ideal three-phase
voltage sources connected via two parallel three-phase transmission lines. The three
 50

phase voltage sources on the left side of the transmission lines are unbalanced, and the
other two are balanced voltage sources. The phase currents of the two lines are
measured and displayed.

The voltage sources have Y-grounded connection. Their parameters are:

Source 1 (Unbalanced):
Phase a: 10.0 V∠00 / 60 Hz,
Phase b: 10.0 V∠1800 / 60 Hz,
Phase c: 10.0 V∠900 / 60 Hz.
Source 2 (balanced):
Phase a: 8.0 V∠200 / 60 Hz.
Source 3 (balanced):
Phase a: 8.0 V∠-200 / 60 Hz.
The parameters for both parallel lines are:
R=1e-3 ohms,
L=0.5 / (2*pi*60) H
M1=0.1 / (2*pi*60) H
M2=0.01 / (2*pi*60) H
M1: mutual coupling between the phases in the same line
M2: mutual coupling between the phase in one line and the phase in another
line

The model of the symmetrical components domain consists of three independent

networks (as there is no fault). The voltage sources of the positive, negative and zero
sequence sources that correspond to the voltage source to the left of the transmission
lines are nonzero, as the source is unbalanced. As the other two sources are balanced,
they are nonzero only for the positive network. The symmetrical branch currents (I+, I,
I0) are measured and converted to the phase currents (Ia, Ib, Ic) to display, in order to
compare with the currents measured in the abc model.

The model of the parallel lines is shown in Figure 2.22 . It is divided in the
impedance of each line and the mutual coupling between the two lines. Both lines are
symmetrical.
 51

Figure 2.22. Model of the parallel transmission lines

Exercises and Solutions

Exercise 1:

Analyze the original system in Figure 2.21 (paralines_2.mdl). Explain the

configuration, parameters and the connections of the symmetrical networks. Check the
displayed currents. Perform a check to confirm whether the measured and synthesized
currents match?

Because there is no fault here, the sequence networks are independent. The voltage
source in the positive sequence network corresponds to the generator in the phase a of
the original system. So, the data in original source can be copied to the positive
sequence network. Since the source at the left hand side is unbalanced, there are
nonzero voltage sources in the positive, negative and zero sequence networks. The
transformation used is shown below:

1 −1
V120 = A V abc
3
 52

Therefore,

10
V1 = ( 3 + 1)∠ − 30 0
3
10
V2 = ( 3 − 1)∠30 0
3
10
Vo = ∠90 0
3

Note that the two sources at the right hand side of the network are balanced
sources, so they do not appear in the negative and zero sequence networks.

The grounding of the sources in the original system must be reflected in the
zero-sequence network. Therefore the zero-sequence network is closed.

Input the data of the model in abc domain:

Only the way of entering the parameters of line model parameters is explained
here. By double clicking the block of “parallel transmission lines”, we can see the
internal model in Figure 2.22.

Double click the Z0-Z1 model named “Line #1” and “Line #2”, enter the

parameters L positive , Lzero ... according to the equations. Then double click in the block

named "mutual inductances between lines". Enter the value of the inductance in ohms.

Input the data of the sequence networks:

Double click in the block for each sequence network. In each sequence circuit,
there are two parallel branches, which are the symmetrical sequence model of the two
lines. Input the parameters of each branch according to the values calculated previously.
For example, in the zero sequence circuit, double click in the upper branch impedance
block, which represents the zero impedance of the Line #1. We have
 53

L0 = Ll 0 + M = (0.7 + 0.03) /(2πf ) H and R0 = 1e −3 ohms (See the Figure 2.23).

Figure 2.23. Parameters of one branch of zero sequence network

Run the simulation program

Figure 2.24 The synthesized and measured currents

 54

The values in the original system and the values in the sequence networks match
well, as shown in Figure 2.24

The currents match perfectly. They illustrate the following:

• Instead of a three-phase system one may analyze three simple one-phase

networks.
• Instead of calculating the phase voltages and currents one may compute the
symmetrical values and then convert them to the phase signals.
• Both the parameters and the connections of symmetrical components must
match the original system data.

Exercise 2:

Assume one voltage source on the right hand side works as an ungrounded Y.
Modify the model to reflect this situation, and check solutions by simulation.

Because the source is ungrounded Y, the loop in the upper side branch of the zero
sequence network is not closed (See Figure 2.25). And there is no change in the
positive and negative sequence network. To edit the original system, select the
grounding icon of the source, and then delete it by pressing the delete key. The
results of simulation are displayed in Figure 2.26. The phase currents measured and
synthesized match well.

Figure 2.25 Zero-sequence network

 55

Figure 2.26 Synthesized and measured currents

Exercise 3:

Based on Exercise 1, change L2 = 1.0 /( 2πf ) H , and M 1 = 0.2 /( 2πf ) H . Modify the

parameters of sequence networks. Check the solution by simulation.

Convert the model to the system in Exercise 1. The parameters changed in line #2
will only influence the zero-sequence model. And we have got this model, see the
Figure 2.27. We have

L' 0 = L' l 0 − M = (0.7 − 0.03) /(2πf )H ,

And
 56

L'' 0 = L'' l 0 − M = (1.4 − 0.03) /(2πf )H ,

which is the parameter of two parallel branches. Lm = 0.03 /(2πf ) H is the parameter

of the branch that is connected in series in the circuit. Simulate this model and compare
the currents. We can see the results of two systems match well.

Figure 2.27 Zero-sequence network

Figure 2.28 Parameters of series impedance in the zero-sequence network

 57

Figure 2.29 Parameters of the impedance of line # 2 in zero-sequence network

Figure 2.30 Synthesized and measured currents

 58

2.3.1.3.Symmetrical Line with Tap Loads

Software Modules

Four modules are available to show the symmetrical components model of a line
with a tap with a load of delta or wye type. These Simulink models for wye and delta
load are shown in Figure 2.31 (linetap1.mdl) and Figure 2.32 (linetap3.mdl). The two
models are divided in two parts, the model inbc domain and the model in symmetrical
components domain.

Figure 2.31 Transmission line with wye load

 59

Figure 2.32 Transmission line with delta load

The first part of the both figures shows is a simple three-phase transmission line.
The line is symmetrical with a tap and a wye and delta load, respectively. One end of
the transmission lines is connected to a grounded Y voltage source, and the other end is
short-circuited. Currents supplied to the transmission lines and voltages at the tap point
for all three phases are measured and displayed.

The system parameters are:

Voltage sources (phase a): 1.0 p.u./0 deg/60 Hz
Line impedance
- positive sequence: 0.01 + j0.05 p.u.
- zero sequence: 0.02 + j0.1 p.u.
Load impedance: 0.72 + j0.54 p.u.
Grounding impedance (wye connection only): 1 p.u resistance
 60

Since the transmission lines are tapped, we divide the line impedance
corresponding to the location of the tap. For this model, it is assumed that the tap is
located at 0.3 times the length of the transmission line from the generator. Thus, the
line impedance to the left of the tap becomes 0.3*(0.01 + j0.05) = 0.003 + j0.015 p.u
for the positive sequence impedance, and 0.3*(0.02 + j0.1) = 0.06 + j0.03 p.u for the
zero sequence. And, to the right of the tap point, it becomes 0.7*(0.01 + j0.05) = 0.007
+ j0.035 p.u. and 0.7*(0.02 + j0.1) = 0.014 + j0.07 p.u for the positive and zero
sequence respectively.

The second part consists of three symmetrical networks for the system shown in
the first part. Currents coming out of the voltage sources and voltages at the tap
locations are measured and supplied to a 012 -> abc converter and displayed for
comparison with the corresponding currents and voltages in the original system.

Exercises and Solutions

Exercise 1:

Analyze the original system. Explain the configuration, parameters, and

connections of the symmetrical networks. Run the software module and observe if the
measured and synthesized currents and voltages match.

First, consider the positive sequence network. The voltage source corresponds to
the generator in the phase a of the three-phase system. Thus, use the data of that
particular generator (i.e. 1.0 p.u / 0 0 / 60 Hz). As for the line impedance, from the
generator to the tap point, use the value corresponding to the positive sequence
impedance of the line in the three-phase system (0.003 + j0.015 p.u). Similar procedure
is applied to the line impedance between the tap point and the shorted end of the
transmission lines (0.007 + j0.035 p.u). For the load, the value corresponds to that of
one leg of the wye load. Thus, 0.72 + j0.54 p.u is entered.
 61

The negative sequence network is built the same way as the positive sequence one.
Since the three-phase system is symmetrical, there is no negative driving force in the
negative network (i.e. set voltage amplitude and phase to 0).

The zero-sequence network is somewhat different than the other networks. For the
line impedance values, use the zero sequence impedance from the three-phase system.
Therefore, the line impedance between the generator and tap point is 0.006 + j0.03 p.u,
and 0.014 + j0.07 p.u between tap point and shorted end of the lines. For this network,
the load at tap point becomes the impedance at one leg plus three times the resistance
to the ground. Thus the value of (0.72+3*1) + j(0.54) p.u is entered. Due to
symmetrical nature of the system, the zero-sequence network also does not have a
driving force.

The above symmetrical network is expected to perform the same way as the
original three-phase system. By running the simulation, the following figures are
obtained. Figure 2.33 is the comparison between phase currents coming into the
transmission line from the generator for both measured and synthesized cases. Signals
for both cases are plotted together to show how they match. Similarly, Figure 2.34
displays the currents going to the wye load for both cases. We can see from these
figures that the synthesized signals match the measured ones perfectly. One exception
is in the transient state, where there are differences due to the 012->abc conversion.
However, it can be concluded that one can analyze three-phase system by computing
and analyzing the corresponding symmetrical network.

Exercise 2:

Assume that the generator supplies the following voltages:

Va = 1.0 / 00; Vb = 1.1 / -1300; and Vc = 0.8 / 1100.

 62

Modify the sequence network to reflect this situation. Check your solution by
simulation.

Figure 2.33 Phase currents into transmission lines

Figure 2.34 Currents into the wye load

First of all, convert the generator voltages into their corresponding symmetrical
 63

voltages.

Consider the relation: V012 = A-1 Vabc

where:

, and a = 1∠120°
1 1 1 
A = 1 a 2 a 
 
1 a a 
2

Thus, equation 1 can be written as:

Va 0  1 1 1  Va 
V  = 1 a
1
a 2  Vb 
 a1  3   
Va 2  1 a a  Vc 
2

By plugging in the appropriate values to equation 2, we get: V0 = 0.031 / -780,V1 =

0.963 / -6.560; and V2 = 0.145 / 75.410. Then, put these voltages into the sequence
networks. Figure 2.35 and Figure 2.36 show the current signals match perfectly,
confirming the solution.

Figure 2.35 Phase currents (asymmetrical generator)

 64

Figure 2.36 Currents into wye load (asymmetrical generator)

Exercise 3:

Assume that the tap load is of the delta type. Modify the original system and
sequence network to reflect this situation Prove your solution by simulation.

First, rearrange the load in the original system from a wye to a delta type, while
maintaining the load impedance values of each leg. In this case, the load is not
grounded. Therefore, remove the ground and the resistance that were in the original
system.

Adjust the sequence network to accommodate these changes. A delta load is seen
by each phase in a three-phase system as a load with the impedance one third of the
actual impedance. So, for the symmetrical network, divide the value of the load in each
sequence network by three.

Now, confirm the solution by running the simulation for the new model. The phase
currents and voltages from the modified three-phase network and symmetrical
component model should match each other as shown in Figure 2.37 and Figure 2.38.
 65

Figure 2.37 Phase currents for delta load

Figure 2.38 Currents into delta load

Exercise 4:

Using the configuration in Exercise 3 for the delta load, assume that the generator
supplies asymmetrical voltages as in Exercise 2. Modify the sequence network to
reflect this situation. Check your solution by simulation.

In Exercise 2, we found the symmetrical components: V0 = 0.031 / -780, V1 =

 66

0.963 / -6.560; and V2 = 0.145 / 75.410. Again, we put these values into the sequence
networks for the delta load in Exercise 3. Figure 2.39 and Figure 2.40 show the
matching signals.

Figure 2.39 Phase currents for the delta load with asymmetrical generator

Figure 2.40 Currents into the delta load with asymmetrical generator
 67

2.3.2 Load

Software Modules

Four different models of load are presented in this section. They are:

• Wye-ungrounded
• Wye-grounded
• Wye-grounded with an impedance to ground
• Delta

Also, symmetrical and unsymmetrical loads are modeled.

In each model, a simple three-phase network is included along with its three
symmetrical component networks. The method of symmetrical components is a tool
for dealing with unsymmetrical problems that may occur in poly-phase system. In the
case of three-phase system, there are 3 symmetrical components involved.

They are:

• Positive-sequence component
• Negative-sequence component
• Zero-sequence component

The sequence voltages are able to find from these following equations:
V0 = (1/3)(VA+VB+VC) (1)
V1 = (1/3)(VA+aVB+a2VC) (2)
V2 = (1/3)(VA+ a2VB+aVC) (3)

where

a = (-0.5+j0.866)
VA, VB, VC are phase voltages,
V0, V1, V2 are voltages of zero-sequence, positive-sequence, and
negative-sequence, respectively.
 68

Exercises and Solutions

a. Symmetrical Connected Loads

Exercise 1:

Analyze the system given in model load5.mdl. The load in this system is
wye-ungrounded. The parameters of the systems in the abc domain are:
Voltage source: Va = 1.0 / 00; Vb = 0 / 00; and Vc = 0 / 00 pu
Load impedance, Z=0.1+j0.2 p.u. per phase

Obtain the parameters for the positive, negative and zero sequence networks
(voltage sources and impedances) and find out if the values shown in the model and in
your calculations match. Explain the configuration in the symmetrical components
domain. Run the simulation. Do the measured and synthesized currents match?

Figure 2.41 Simulink model for the symmetrical wye-connected load

 69

The loads are linked to three ideal voltage sources that have a wye-ungrounded
connection. The voltage sources for the zero, positive, and negative-sequence
components in the models can be found from equations 1 to 3. Therefore, we have:
V0 = 1/3 /00
V1 =1/3 / 00
V2 =1/3 / 00

Since the system is symmetrical, ZA = ZB = ZC = 0.1+j0.2 p.u., then Z0 = Z1 = Z2 =

(1/3)(ZA+ZB+ZC).

In this case, there is no zero-sequence current due to ungrounded load.

Figure 2.42 Measured and synthesized currents

Exercise 2:

Repeat Exercise 1, but connect the load to ground. Make the appropriate changes
to the symmetrical networks. The corresponding model is named load8.mdl.

The voltages and impedance for the sequence networks are the same as for the
previous Example. In this case, there is zero-sequence current, as there is a return path
for the zero sequence current. The synthesized and measured currents are shown in the
Figure 2.44. Note that the phase currents in phase b and c are zero.
 70

Figure 2.43 Model of Symmetrical wye-grounded connected load

Figure 2.44 Measured and synthesized currents

 71

Exercise 3:

Repeat Exercise 2, but now connect the load through impedance. Assume that its
value is ZN = j0.1 p.u.. Reflect this change in the symmetrical networks. The
corresponding model is named load7.mdl.

Figure 2.45 shows the three-phase system and the model.

Figure 2.45 Model of wye-grounded connected load with ground impedance

In this case, there is another impedance added between the neutral and ground of
the wye-connected load as shown in Figure 2.45. Its value is ZN = j0.1 p.u. Hence,
impedance of 3ZN is placed between the neutral and ground in the zero-sequence
component.
 72

Figure 2.46 Measured and synthesized currents

Exercise 4:

In the given system, change the connection of the load to delta. Make the values
for each branch of the delta: ZA =ZB =ZC= 0.3+j0.3 p.u.. Obtain the positive, negative
and zero-sequence networks. The corresponding model is named load6.mdl.

Figure 2.47 shows the three-phase system and the model.

In the case of delta connected load, there is no return path provided, which offers
infinite impedance to the zero-sequence current. But the zero-sequence current can be
flowing inside the triangle of delta. Also, the way to find impedance value for each
sequence is different. The delta-connected load should be transformed to a
wye-connected load. Then the Z0 = Z1 = Z2 = (1/3)(ZA). Let ZA= 0.3+j0.3 p.u. then, Z0
= Z1 = Z2 = 0.1+j0.1 p.u. The sequence voltage sources have the same values as for the
previous examples.

The measured and synthesized currents are shown in the following Figure 2.48. It
can be seen that they match very closely.
 73

Figure 2.47 Model of the delta connected load

Figure 2.48. Measured and synthesized currents

 74

b. Asymmetrical Connected Loads

Exercise 5:

Repeat Exercise 1, but change the load parameters in the abc domain as follows:
ZA 0.1+j0.3 p.u.
ZB 0.1+j0.4 p.u.
ZC 0.1+j0.4 p.u.

The corresponding model is named load1.mdl.

The voltage sources for the zero, positive, and negative-sequence components in
the models can be found from equations 1 to 3. Therefore, V1 = 1, and V0 = V2 = 0 p.u.
Since the system is unsymmetrical, Z0, Z1, and Z2 should be found from Z012 =
A-1ZabcA.
−1
 Z 0  1 1 1  Za 0 0  1 1 1
 Z  = 1 a 2 a  0 Zb 0  1 a 2 a 
 1  
 Z 2  1 a a 2   0 0 Zc  1 a a 2 

If we substitute the values of Za, Zb and Zc, we have:

−1
 Z 0  1 1 1 0.1 + 0.3i 0 0  1 1 1
 Z  = 1 a 2 a   0 0.1 + 0.4i 0  1 a 2 a 
 1   
 Z 2  1 a a 2   0 0 0.1 + 0.4i  1 a a 2 

Z 0  0.1 + j 0.3666 − j 0.0333 − j 0.0333 

 Z  =  − j 0.0333 0.1 + j 0.3666 − j 0.0333 
 1 
Z 2   − j 0.0333 − j 0.0333 0.1 + j 0.3666

The model is shown in Figure 2.49.

 75

Figure 2.49 Model for the unsymmetrical ungrounded wye-connected load

We can note that the unsymmetrical load in the abc domain becomes mutual
impedances between the sequence networks. In this case there is no zero sequence
current as there is no return path.

Exercise 6:

Repeat Exercise 2, but change the load parameters in the abc domain as follows:

ZA 0.1+j0.3 p.u.
ZB 0.1+j0.4 p.u.
ZC 0.1+j0.5 p.u.

The corresponding model is named SNe6.mdl.

The model for this Example is shown in Figure 2.50. The corresponding model is
named load4.mdl.
 76

Figure 2.50 Model for the unsymmetrical grounded wye-connected load

The voltage sources for the zero, positive, and negative-sequence components in
the models can be found from equations 1 to 3. Therefore, V1 = 1, and V0 = V2 = 0 p.u.
Since the system is unsymmetrical, Z0, Z1, and Z2 should be found from Z012 =
A-1ZABCA. Therefore, we have:
−1
 Z 0  1 1 1 0.1 + 0.3i 0 0  1 1 1
 Z  = 1 a 2 a   0 0.1 + 0.4i 0  1 a 2 a 
 1   
 Z 2  1 a a 2   0 0 0.1 + 0.5i  1 a a 2 

Z 0   0.0289 − j 0.05 − 0.0289 − j 0.05 0.0289 − j 0.05 

 Z  =  − j 0.0333 0.1 + j 0.4 − 0.0289 − j 0.05
 1 
Z 2  − 0.0289 − j 0.05 − j 0.0333 0.0289 − j 0.05 

It can be checked in the model that the measured and synthetized values match
very well.
 77

Exercise 7:

Repeat Exercise 6, but in this case connect the load to ground through and
impedance of value Zn=j0.1 p.u.. The corresponding model is named load3.mdl.

The values for the impedances of the sequence networks are equal to the ones
obtained in the previous Exercise. But in this case, an impedance of value 3Zn
connects the zero-sequence network to ground.

Figure 2.51 Model for the unsymmetrical wye-connected load with ground impedance

The synthesized and measured currents should match very well.

 78

Exercise 8:

Repeat Exercise 4, but in this case the impedances of the delta-connected load are:

ZAB 0.3+j p.u.

ZAC 0.3+j p.u.
ZBC 0.29+j1.33 p.u.

The corresponding model is named load2.mdl.

Figure 2.52 shows the three-phase system and the model.

Figure 2.52 Model for the unsymmetrical delta-connected load

The load impedance has to be transformed to wye in order to find the sequence
impedances. The delta-wye transformation expression is the following:
 79

Z a  Z CA 0 0   Z AB  0.1 + j 0.3
Z  = 1  0 Z AB 0  ⋅ Z BC  = 0.1 + j 0.4
 b Z +Z +Z 
 Z c  AB BC CA
 0 0 Z BC   Z CA  0.1 + j 0.4

Where:

ZAB 0.3+j p.u.

ZAC 0.3+j p.u.
ZBC 0.29+j1.33 p.u.

We can observe that, after the transformation, the system becomes the same as the
one in Exercise 5, so the values of the impedances for the sequence networks are the
same.

2.3.3 Two-winding Transformer

Simulation Modules

In this part, symmetrical component networks for three-phase two-winding

transformers will be studied, including the types: Yg − ∆ , ∆ − Yg , and Yg − Y . The

MATLAB models for the transformers with these connections are shown in
Figure 2.53. Note that all these transformers are composed of three independent
single-phase transformers.

Figure 2.53 Yg-∆, ∆-Yg and Yg-Y transformers

 80

Regardless of the connection method, the positive and negative sequence networks
of a three-phase transformer have the same impedance as a single-phase transformer
that makes up the three-phase transformer. However, the zero sequence impedance
depends on the connection. Generally speaking, the delta connection side provides a
loop for the zero sequence current that flows inside the transformer windings. The
grounded-wye connection side provides a path for the zero sequence current to the
ground. The ungrounded-wye side does not provide a path for the zero sequence
current. Another point to be noted is that there is a phase shift for both the positive and
negative sequence components for transformers of the types wye-delta and delta-wye,
no matter if the wye side is grounded or ungrounded. So appropriate phase shifts need
to be considered in building the sequence networks.

Exercises and Solutions

Exercise 1:

Find the positive, negative, and zero sequence networks for the Yg − ∆

transformers as shown in Figure 2.53. This transformer has the parameters as follows:
Three-phase rated power (MVA): 300
Frequency (Hz): 60

Winding 1:
Phase-Phase Voltage (Vrms): 315 kV
[R(pu) X(pu)] : [0.01 0.1]

Winding 2:
Phase-Phase Voltage (Vrms): 13800
[R(pu) X(pu)] : [0.01 0.1]
Magnetizing branch: [Rm(pu) Xm(pu)] : [500 500 ].

Open the model called SNe9.mdl. In order to test the sequence impedance of the
transformers his model has two three-phase sources. The source on the right-hand side
 81

is a balanced source with: Va= 11268 V/-200. The source on the left-hand side is
unbalanced with: Va=257.2 kV/00, Vb=257.2 kV/-800, Vc=257.2 kV/600. Obtain the
sources for the sequence circuits and compare your results with the ones shown in the
model. Run the model and check if the currents obtained with the symmetrical
networks and the three-phase system match.

Figure 2.54 Yg-∆ transformer and its sequence networks

The positive, negative, and zero sequence networks for the Yg − D transformer is

illustrated in Figure 2.54. The zero sequence resistance is 0.01*(315^2/300)*2 Ohms

and zero sequence inductance is 0.1*(315^2/300)/(2*pi*60)*2 H. The positive and
negative sequence impedances are the equal, with resistance 0.01*(13.8^2/300)*2
Ohms and inductance 0.1*(13.8^2/300)/(2*pi*60)*2 H.
 82

Figure 2.55 The ideal positive transformer of Yg-∆ transformer

Figure 2.55 shows the subsystem for the positive sequence of the transformer. The
secondary side voltage is obtained by delaying the primary side voltage by 30 degrees
and the primary side current is obtained by leading the secondary side current by 30
degrees. The positive sequence impedance is lumped to the secondary side as shown in
Figure 2.54. The negative sequence network is built similarly except that the phase
shift is opposite to the positive sequence network.

Figure 2.56 (Trans1.mdl)depicts a system for verifying the designed sequence

networks for the Yg − ∆ connection. Note that in the figure, the secondary side of

the transformer is connected to the ground directly. The currents through the primary
side and the secondary side of the original transformer are compared with those
synthesized from the sequence networks. A large grounded resistor is added in the
zero-sequence network to avoid the error message “current measurement has an open
side”. This certainly does not affect the measurements.

It is clearly shown that the directly obtained currents match with those synthesized
 83

from the sequence networks. There is a very little discrepancy in the simulation due to
numerical approximations. This verifies that the sequence networks are correct.

Figure 2.56 A power system verifying the sequence networks of the Yg-∆ transformer

Exercise 2:

Repeat Exercise 1 with a Yg-Y transformer. Use model Trans2.mdl for this
Exercise.

The Yg − Y transformer and its sequence networks are shown in Figure 2.57. The

parameters for the sequence impedances are:

Zero sequence resistance: (500+0.01)*(315^2/300)*2 Ohms
Zero sequence inductance: (500+0.1)*(315^2/300)/(2*pi*60)*2 H.
Positive sequence resistance: 0.01*(13.8^2/300)*2 Ohms.
Positive sequence inductance: 0.1*(13.8^2/300)/(2*pi*60)*2 H.
 84

Negative sequence resistance: 0.01*(13.8^2/300)*2 Ohms.

Negative sequence inductance: 0.1*(13.8^2/300)/(2*pi*60)*2 H.

Figure 2.57 The Yg-Y transformer and its sequence networks

The system verifying the sequence networks for the Yg − Y transformer is shown

in the model Trans1.mdl (See Figure 2.58).

Exercise 3:

Repeat Exercise 1 with a ∆ −Yg transformer. Use model Trans3.mdl for this

Exercise. The sequence networks for the ∆ −Yg transformer are shown in Figure 2.59.

The sequence impedances shown in Figure 2.60are:

Sequence resistance: 0.01*(13.8^2/300)*2 Ohms
Sequence inductance: 0.1*(13.8^2/300)/(2*pi*60)*2 H.

The system verifying the sequence networks of ∆ − Yg transformer is shown in

Figure 2.60. Note that a large grounded resistor is added in the zero-sequence network
for the convenience of measuring the primary side zero sequence current, which is
essentially zero.
 85

Figure 2.58 A power system verifying the sequence networks of the Yg-Y
transformer

Figure 2.59 The ∆-Yg transformer and its sequence networks

 86

Figure 2.60 A power system verifying the sequence networks of the Yg-∆ transformer

2.3.4 Synchronous Machine

Simulation Modules

Three Simulink models are available for the symmetrical components of the
synchronous machine. The first model, shown in Figure 2.61, demonstrates the
sub-transient, transient and steady state positive sequence impedance for the
Synchronous machine. In this case it is used as a generator. In the second model
(Figure 2.62), the negative sequence impedance of the synchronous machine in steady
state is demonstrated. In this case the synchronous machine is functioning as a motor.
Finally, in the third case (Figure 2.63), the modeling of the three sequence networks
are tested in a system where an unbalanced source feed the synchronous machine.
 87

a. Positive sequence network model (Positive.mdl)

A three-phase fault is placed at the machine terminals. The positive sequence

current is measured and compared with the currents of symmetrical networks. Because
the fault happens at t=0.64s, transport delay blocks are used. There is also a delay in
Clock.

The pre-fault values of E”, E’ and E are calculated by the following formulas:

E " = Va + jIa * Xd " = Ua 2 + ( Ia * Xd " ) 2

E ' = Va + jIa * Xd ' = Ua 2 + ( Ia * Xd ' ) 2

E = Va + jIa * Xd = Ua 2 + ( Ia * Xd ) 2

Figure 2.61 Positive sequence network

 88

b. Negative sequence network (Negative.mdl)

A synchronous machine is connected with a negative sequence voltage source.

This model is used to prove the negative sequence reactance.

Figure 2.62 Negative Sequence network

c. Sequence networks in steady state (zero.mdl)

In this model the sequence parameters of the synchronous machine in steady state
are shown.
 89

Figure 2.63 Steady state sequence networks for the synchronous machine

Exercises and Solutions

Exercise 1:

Analyze the original system given in Positive.mdl. Explain the configuration and
the connections of the symmetrical networks. Obtain the parameters for the positive
sequence network. Run the simulation. Observe the signals. Do the measured and
synthesized voltages and currents match?

The parameters of the synchronous machine are the following:

SN = 12000 VA
VN = 400*(√3) V (rms)
 90

IN = SN/(√3)*VN) = 12000/(3*400) = 10 A (rms)

ZB = 400 / 10 = 40 Ohm
Xd" = 0.252 (pu)
Xd' = 0.296 (pu)
Xd = 1.305 (pu)
Xq" = 0.252 (pu)
Xq = 1.305 (pu)

Converting the reactances to the SI units:

Xd" = 0.252 * ZB = 10.08 Ohm
Xd' = 0.296 * ZB = 11.84 Ohm
Xd = 1.305 * ZB = 52.2 Ohm

Calculating the pre-fault values of internal voltages:

E = Va + jIa * Xd = Va2 + (Ia * Xd) 2 = (500/ 2) 2 + (6 / 2 * 52.2) 2 = 417.19V (rms)

E" = Va + jIa * Xd" = Va2 + (Ia * Xd") 2 = (500/ 2) 2 + (6 / 2 *10.08) 2 = 356.13V (rms)

E' = Va + jIa* Xd' = Va2 + (Ia * Xd' ) 2 = (500/ 2) 2 + (6 / 2 *11.84) 2 = 357.1V (rms)
Note: Va and Ia can be measured from the pre-fault conditions.

Figure 2.64 shows the waveforms.

Figure 2.64 Positive sequence current waveforms

 91

There is a phase difference between the two values. Because in the model of
synchronous machine in MATLAB, the inertia is not infinite, so the frequency of the
synchronous machine is not constant. In short circuit studies, we are more interested
about the magnitude rather than the phase angle.

Exercise 2:

Obtain the negative sequence reactance of the synchronous machine and run the
model Negative.mdl. Do the measured and synthesized voltages and currents match?

The negative sequence reactance of synchronous machine is dependent of the fault

types. For simplification, we can use (Xd"+Xq")/2 as the negative sequence reactance.

In Figure 2.65, we can see the results we can see the negative sequence current
obtained from the sequence network and from the model of the synchronous machine
match.

Figure 2.65 Negative sequence current waveforms

 92

Exercise 3:

Assume the Xd" and Xq" of the synchronous machine are 0.2. Modify the model
and the sequence networks to reflect the situation. Check your solution by running the
models SSMP.mdl and SSMN.mdl.

Change the value of X" in Positive.mdl to 0.2, and run the simulation. The result is
shown in Figure 2.66.

Figure 2.66 Positive sequence current waveforms

Change the value of X2 in Negative.mdl to 0.2, and run the simulation again. The
result is shown in Figure 2.67.
 93

Figure 2.67 Negative sequence current waveforms

Exercise 4:

An unbalanced load (Va= 400 /00 V, Vb= 400 /00 Vc= 400 /-1000) is connected to
the terminals of the synchronous machine . Obtain V0,V1 and V2 and run the simulation.
Do the measured and synthesized voltages and currents match?

The parameters of V1, V2, and V0 can be calculated using the following formulae:

V0  1 1 1  Va  1 1 1   400∠0  276.6597∠ − 28.3345

V  = 1 1 α α 2  V  = 1 1 α α 2   400∠0  =  204.2785∠100 
 1 3  b  3     
V2  1 α 2
α  Vc  1 α 2 α  400∠ − 100  204.2785∠ − 20 

The result is shown in Figure 2.68.

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Figure 2.68 Steady state unsymmetrical current waveform

The values are not exactly the same, but they are close. The simulation of the
sequence networks is run after the transients of the synchronous machine have died (at
t-=2 s).

Note that the synchronous machine in the Power Systems Blockset is not
connected to ground by its neutral point. Therefore zero sequence network is open. To
simulate this fact in the zero-sequence network, a very large resistance is used.

2.3.5 Induction Motor

Simulation Modules

A Simulink model illustrating the symmetrical networks for the three-phase

induction machine is available. The model consists of an ideal three-phase voltage
source connected to the induction motor. The Simulink model can be seen in
Figure 2.69 (Indmot1.mdl.).
 95

Figure 2.69 Model in abc domain and symmetrical networks for the induction motor

The model is divided in two major parts. In the upper half of the Simulink diagram,
a simple three-phase power system (including one induction machine) can be seen. The
symmetrical networks for this simple three-phase power system are derived and
implemented in the lower half of the block diagram.

Exercises and Solutions

Exercise 1:

Analyze the Simulink model Indmot1.mdl. Look at the parameters in the abc
domain and in the sequence networks. Explain the connections of the symmetrical
networks, run the case, and then observe the signals. Finally, check if the measured and
synthesized currents match or not? Assume that the source is balanced.
 96

The 3-phase system, which includes an induction machine and its equivalent three
symmetrical networks, are shown in Figure 2.70 for the case where generator is
balanced. Since we have a balanced voltage source, the zero sequence and negative
sequence voltages are zero. Therefore, in Figure 2.69, no voltage source takes place in
these two circuits. So the voltage source in the positive sequence network corresponds
to the phase a of the generator of original three-phase system.

In summary, we just have positive sequence current for this case. In other words,
the zero sequence and negative sequence currents are zero as a result of having a
3-phase balanced source in the original system.

After running the simulation we get the following results for the phase currents
obtained from both induction motor and from sequence network.

Figure 2.70 Three-phase stator currents obtained from induction motor and currents
obtained by using sequence networks

As seen in Figure 2.70, the measured and synthesized values match perfectly.
This illustrates that:

• Instead of computing phase currents one may compute the symmetrical values
and then convert them into phase signals,
 97

• Both parameters and the connections of the symmetrical components must

match the original system data.
Exercise 2:

Repeat the Exercise 1 with an unbalanced 3-phase source. What is the basic
difference between these two cases? Use Indmot2.mdl for this example.

In this case, together with positive sequence we also have voltage sources for both
negative and zero sequences due to the unbalanced source. Actually having a non-zero
voltage source at zero-sequence network does not have any effect on overall system,
since it is an open circuit. Therefore, in this case, we have both positive and negative
sequence currents.

Before starting simulations, the corresponding value of generators in sequence

domain should be found. Here the unbalanced voltage source has the same amplitude,
but the phase angles cause the unbalanced situation.

The voltages for the three-phase source of the original 3-phase system as well as
for the sequence networks are as follows:
Va=220/√2 ∠30°
Vb=220/√2 ∠-70°
Vc=220/√2 ∠145°

Va0=21.3275∠18.99°
Va1= 152.8115 ∠ 34.9614°
Va2= 19.8439∠ -122.5572°

By entering these values in the symmetrical networks and running simulation we

get the results shown in Figure 2.71.
 98

Figure 2.71 The 3-phase stator currents obtained from induction motor and currents
obtained by using sequence networks

For the unbalanced source case, the stator currents obtained from original 3-phase
system and the ones obtained by using sequence networks match again except for a
slight difference during the starting transients' period.

Exercise 3:

Run the simulation by using balanced source first, and then after reaching
steady-state switch the balanced source to an unbalanced one, and observe the effect of
this switching action? Do the measured and synthesized voltages still match? Use
Indmot3.mdl for this example.

In this case simulation is started with a balanced voltage source like in Exercise 1,
and continued until the starting transients have died. As soon as steady state is reached
(roughly say at t=2) the set of balanced source is switched off, and instead an
unbalanced source (like in Exercise 2) is connected.

The generator values both in balanced and unbalanced cases are kept as same as
the previous examples. So the balanced voltage sources and their equivalents in
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sequence domain are replaced at time t=2 by the unbalanced voltage sources and their
sequence domain equivalents. This switching action and corresponding Simulink block
diagram can be seen in Figure 2.72.

Figure 2.72 The simulation module for induction motor

After running the system, which is shown in Figure 2.72, one can obtain the
following results for the phase currents obtained from both induction motor and the
ones from sequence network.

As seen in Figure 2.73, the results match perfectly, except at the time where the
transients take place due the generator switching. More severe transients take place in
three-phase system than in sequence networks, as expected.
 100

Figure 2.73 3-phase stator currents obtained from induction motor

and currents obtained by using sequence networks

Exercise 4:

Consider the case when a fault takes place in one of the lines that connects the
generator to the induction motor, and due to this fault one of the phases of the voltage
source is taken out at time t=t0. Observe the effect of this situation on symmetrical
components. Do the measured and synthesized voltages still match? Use Indmot4.mdl
for this example.

In this case, one of the phases of the source is taken out at a certain time in the
 101

three-phase original system, it causes that the original system becomes an unbalanced
system, and so it affects the sequence networks. In other words, at time where the fault
takes place, the voltage sources in the sequence networks should be updated. Although,
at the beginning we do not have any voltage source in the negative sequence network,
after that time where the original system becomes unbalanced, both generator values in
the positive and negative sequence networks are changed. This task is performed by a
switching action in the Simulink. Phase voltages before and after the fault time are as
follows:

Phase voltages in the original 3-phase system before the fault:

Va=220/√2 ∠0°

Vb=220/√2 ∠-120°

Vc=220/√2 ∠120°

Phase voltages in the original 3-phase system after the fault: Va=0, the other two
phases remain the same.

Generator values in sequence networks before the fault:

Va0 = 0

Va1 = Va =220/√2 ∠0°

Va2 = 0

Generator values in sequence networks after the fault:

Va0 = 51.8545∠180°

Va1 = 103.709∠0°

Va2 = 51.8545∠180°
 102

The corresponding Simulink block diagram can be seen in Figure 2.74, and
simulation results are shown in Figure 2.75.

Figure 2.74 The model used for Exercise 4

After looking at the Figure 2.74, it can be said that, the results match perfectly.
The only difference between the results obtained from three-phase original system and
the symmetrical networks is that the phase-a value of the armature current is zero after
the fault point, while the current value (phase-a) obtained from symmetrical networks
is non-zero.
 103

Figure 2.75 Stator current (phase-c) obtained by from induction motor

and the one obtained by using sequence networks.

2.4 Matrix Method for Short Circuit Calculation

The admittance matrix as well as the impedance matrix can be used to compute the
fault currents in a power system. The characteristics of each of these matrices are
described in exercises. The exercises illustrate admittance and impedance approaches
to the short circuit studies. After completion of this exercise one will have an
understanding of these approaches. The admittance and impedance approaches are
explained in the following paragraphs.

2.4.1 Software Modules

The Simulink model for an admittance approach is shown in Figure 2.76

(admittance.mdl). Typing
 104

“admittance” in MATLAB command line is to open the model. Then pressing the
"play" button to simulation is performed.

Figure 2.76. Admittance approach to short circuit studies

The Simulink model for an impedance approach is shown in Figure 2.77

(admittance.mdl).Typing “impedance” in MATLAB command line is to open the
model. Then pressing the "play" button to simulation is performed.

Figure 2.77 Impedance approach to short circuit studies

 105

2.4.2 Exercises and Solutions

Exercise1:

By using the two models find all entries of admittance Y and impedance Z
matrices of IEEE 6-bus network. To obtain the Y matrix, place the voltage source in
node 1 and connect to ground the rest of the nodes. Run the model. The displays will
give the following results:
• Y1 will display the value of element Y11 of the impedance matrix.
• Y2 will display the value of element Y12 of the admittance matrix.
• Y3 will display the value of element Y13 of the admittance matrix.
• Y4 will display the value of element Y14 of the admittance matrix.
• Y5 will display the value of element Y15 of the admittance matrix.
• Y6 will display the value of element Y16 of the admittance matrix.

Repeat the same procedure for node 3, 4, 5 and 6. The Y matrix will be formed this
way.

The process to obtain the impedance matrix is analogous to the one for the Y
matrix. For this case, we have a current source instead of a voltage source. And the
nodes that are not connected to the source are not grounded.

After obtaining both matrices indicated above, observe whether they are
symmetrical or not. Calculate the values of the Y and Z matrices by using MATLAB
and check if they match. Which of the two matrices is sparse?

Exercise2:

Modify the network by adding a new branch e.g. between node 2 and 4. Run the
simulation and observe the effect of adding branch. Which elements change in the Z
matrix and which in the Y matrix?

The elements of matrices Z and Y match with the ones obtained using MATLAB.
 106

There are small discrepancies, but they are acceptable (the errors are caused by
simulation error, numerical accuracy, etc.). It can be noted that Z and Y matrices are
fully symmetrical. Y matrix is sparse (This can be seen more clearly in a network of
several nodes). On the other hand, as Z is the inverse of Y (Z=Y-1), it is a full matrix.
 107

3. BASICS OF PROTECTIVE RELAYING AND DESIGN PRINCIPLES

3.1 Overcurrent Relaying

3.1.1 Software Modules

The software modules provided in this section can be used to learn to protect a
radial network using definite-time overcurrent relays. Particularly, the following issues
are re-enforced: load flow and short-circuit calculations, selecting the protective
equipment, setting and coordinating overcurrent relays, relay sensitivity check,
analysis of the network operation under variety of conditions including faults and
equipment mal-operations.

Load1 Load2 Load4

BUS-1 BUS-2 BUS-3

Load3
F-0 F-1 F-2 F-3
CT1 CB1 CT2 CB2 CT3 CB3
Line 1 Line 2

OR-1 OR-2 OR-3

Figure 3.1. A sample radial network with overcurrent relays.

The module “OCRe.mdl” contains the network models shown in Figure 3.1. To
use the model put the file into the default working directory of MATLAB (typically
MATLAB/BIN), run MATLAB and type "OCRe".

The following are useful hints on how to use the model:

* Double-click on an element to change its parameters or see what is inside the
element.
* Double-click on a scope to open it and see the plot.
* Use the zooming buttons of the plot to zoom in or out.
 108

* Highlight (click-on) and press DEL to delete a given connection between two
blocks.
* Draw a line between the terminals to connect the elements.

Default Data:

The model has been developed with the following data:

* System voltage: 158kV (114% of 138kV)
* System impedance: 1 + j10 Ω
* Line 1 impedance: 2 + j20 Ω, fault location 0.5
* Line 2 impedance: 2 + j20 Ω, fault location 0.5
* Load 1: 138kV, 100MW, 30MVAr
* Load 2: 138kV, 100MW, 30MVAr
* Load 3: 138kV, 50MW, 15MVAr
* Load 4: 138kV, 50MW, 15MVAr
* Fault: 0 Ω, inception time 20 msec.
* CB-1 operating time: 15 msec
* CB-2 operating time: 20 msec
* CB-3 operating time: 25 msec
* CT-1: 1600/1A
* CT-2: 1000/1A
* CT-3: 500/1A
* OR-1: pick-up 1.134A, delay 90 msec
* OR-2: pick-up 0.907A, delay 50 msec
* OR-3: pick-up 0.907A, delay 5 msec.

Note: the time data are re-scaled to speed-up the simulation. The actual values
would be approximately 10 times higher.

3.1.2 Exercises

Exercise 1

Disconnect the fault and run simulation for the sound system. Observe the currents
and voltages. Check if they match your calculations.

Figure 3.2 (a) shows the current of the load 3. The magnitude of the current reads
0.685 A (secondary) instead of 0.756 A (secondary). The difference is caused by the
 109

fact that the voltage at the busbar 3 differs from the rated value. Since the load model
maintains the power, thus, if the voltage is not the rated one (90.6V secondary instead
of 100V secondary - see Figure 3.2 (b)), then neither the current is.

Figure 3.2 (c) shows the current at the CT-2. The magnitude of the current reads
0.685 A (secondary) instead of 0.756 A (secondary). The difference is caused by the
same factor as above.

Similar relation holds true for the current at CT-1 although the load 1 operates at
the voltage above the rated value - 105.5 V secondary (Figure 3.2 (d)).

The simulation validates our calculations. The differences result from the fact that
the rated voltage was assumed for all the loads in the system when calculating the load
currents. Certainly, the simulated values are more accurate.

(a) (b)

(c) (d)

Figure 3.2. Load current and bus voltage for Exercise 1.

 110

Exercise 2

Place the fault at F-3 and disconnect all the relays so that the fault is not cleared.
Observe the fault current. Check if it matches your calculations.

Figure 3.3 displays the fault current. The current shows significant DC component
decaying after about 4 cycles. The steady-state magnitude reads 5.82 A (secondary at
CT-3), while the calculated value is 6.28 A. The difference results from the load current
superimposed on the fault current (our short-circuit calculations neglected the load
current according to the common and reasonable approach).

Figure 3.3 Fault current at F-3 (secondary A at CT-3)

Exercise 3

Reconnect the trip signals of the relays. Observe the system and explain its
behavior. What is the fault clearing time?

Figure 3.4 (a) shows the current at CT-3 while Figure 3.4 (b) the voltage at the bus
3. The fault is cleared by OR-3. The relay operates after 6 msec and the fault is finally
cleared 34 msec after the fault. The voltage drops to zero during the fault and then
rebuilds once the fault is cleared.

Figure 3.4 (c) shows the current at CT-2. The current jumps from the normal load
value to the fault value and then drops after the fault is cleared by OR-3. The post fault
 111

magnitude is lower because the faulted load 3 is disconnected. The relay OR-2 does
not trip (correct behavior). The busbar 2 voltage behaves similarly to the voltage at the
bus 3.

Figure 3.4 (d) shows the current at CT-1. As for the current at CT-2, the current
measured by OR-1 jumps from the normal load value to the fault value and then drops
after the fault is cleared by OR-3. The post fault magnitude is lower since the faulted
load 3 is disconnected. The relay OR-1 does not trip (correct behavior). The busbar 1
voltage behaves similarly to the voltage at the bus 3, however the voltage drop is much
lower since the fault is quite distant (Figure 3.4 (e)).

(a) (b)

(d)
(c)
 112

(e)

Figure 3.4 Voltage and current waveforms for Exercise 3

Exercise 4

Place the fault in the middle of the line 2. Observe the system and explain its
behavior. What is the fault clearing time?

Figure 3.5 (a) shows the current at CT-2. The fault is cleared by OR-2. The relay
operates after 52 msec and the fault is finally cleared 76 msec after the fault. The bus 2
voltage drops during the fault and then rebuilds once the fault is cleared (Figure 3.5
(b)). The relay OR-3 does not operate because it does not measure any fault current
(Figure 3.5 (c)).

Figure 3.5 (d) shows the current at CT-1. The current jumps from the normal load
value to the fault value and then drops after the fault is cleared by OR-2. The post fault
magnitude is lower since the loads 3 and 4 are disconnected. The relay OR-1 does not
trip (correct behavior).
 113

(a) (b)

(c) (d)

Figure 3.5 Voltage and current waveforms for Exercise 4

The protection system behaves correctly. Since the line 2 suffers a fault, this line
must be disconnected by OR-2. Since the loads 3 and 4 can be fed only by the line 2,
those loads are left out of service due to the fault. The rest of the system is in service
(line 1, loads 1 and 2).

Exercise 5

Place the fault in the middle of the line 1. Observe the system and explain its
behavior. What is the fault clearing time?

Figure 3.6 (a) shows the current at CT-1. The fault is cleared by OR-1. The relay
operates in 92 msec and the fault is finally cleared 109 msec after the fault. The bus 1
voltage drops during the fault and then rebuilds once the fault is cleared (Figure 3.6
(b)). The relays downstream (OR-2 and OR-3) do not operate because they do not
 114

measure any fault current.

(a) (b)

Figure 3.6 Voltage and current waveforms for Exercise 5

The protection system behaves correctly. Since the line 1 suffers a fault, this line
must be disconnected by OR-1. Since the loads 2, 3 and 4 can be fed only by the line 1,
those loads are left out of service due to the fault. The rest of the system is in service
(load 1).

Exercise 6

Place the fault at the load 3. Disconnect OR-3 from the CB-3 to simulate
relay/breaker maloperation. Observe the system and explain its behavior. What is the
fault clearing time?

The relay OR-3 operates after 6 msec (compare to exercise 3), and the fault should
be cleared 25 msec after the relay operation. However, the trip signal is not relayed to
the circuit breaker (broken wire) or the CB-3 fails to operate and the fault is not cleared.
This is an example of the fault situation combined with the malfunction of the
protection/switching equipment. In order to provide system protection in such cases
one needs at least one extra level of back-up protection. In the case of the overcurrent
relaying, the next relay upstream acts as a back-up element. The OR-2 picks-up during
this fault and operates after 52 msec. The CB-2 opens 76 msec after the fault. As a
 115

result of this sequence of events, the line 2 gets removed from service and the load 4 is
disconnected. However, since there is a fault at the load 3 and the CB-3 fails to trip, to
operate CB-2 is the only way to clear this fault. The action is optimal even though
more loads are left out of service.

The relay upstream (OR-1) also picks-up but does not trip since the fault gets
cleared by OR-2 and CB-2. But if the latter fail as well, OR-1 will trip taking out both
the lines 1 and 2.

(a) (b)

Figure 3.7 Voltage and current waveforms for Exercise 6

Exercise 7

Place the fault in the middle of the line 2. Disconnect OR-2 from the CB-2 to
simulate relay/breaker maloperation. Observe the system and explain its behavior.
What is the fault clearing time?

As in the previous exercise, the primary line 2 relay (OR-2) operates but the CB-2
fails to open the circuit and the fault is not cleared. The back-up relay upstream (OR-1)
picks-up and since the fault lasts too long (beyond the time delay of OR-1), the relay
trips (93 msec after the fault) breaking the supply through the line 1 109 msec after the
fault (Figure 3.8). As a result of this sequence of events, the line 1 gets removed from
service and the load 2 is disconnected. However, since there is a fault on the line 2 and
 116

the CB-2 fails to trip, the only way to clear this fault is to operate CB-1. The action is
optimal even though more loads are taken out of service.

Figure 3.8 Current at CT-1 during the fault in the middle of the line 2 (secondary A).

Exercise 8

Place faults at different locations with different fault resistances and check if the
protection system works correctly. Include maloperation of the relays and/or breakers.

Repeat the calculations and simulations described in section 4 for the following
data:
* System voltage: 158kV (114% of 138kV)
* System impedance: 1.5 + j8 Ω
* Line 1 impedance: 2.2 + j20 Ω
* Line 2 impedance: 1.8 + j21 Ω
* Load 1: 138kV, 75MW, 32MVAr
* Load 2: 138kV, 90MW, 25MVAr
* Load 3: 138kV, 40MW, 15MVAr
* Load 4: 138kV, 30MW, 12MVAr
* CB-1 operating time: 17 msec
* CB-2 operating time: 21 msec
* CB-3 operating time: 15 msec
* OR-3: delay 15msec.

3.2 Impedance Relaying

3.2.1 Software Modules

 117

The software modules provided in this section can be used to learn to protect a
transmission network using impedance relays. Particularly, the following issues are
elaborated: setting and coordinating multi-zone impedance relays, and analysis of the
network operation under variety of conditions including faults and protective
equipment mal-operations.

Load1 Load2 Load3

BUS-1 BUS-2 BUS-3

CT1 CB1 CB2 CT2 CT3 CB3 CB4 CT4

A Line 2
B
Line 1

ZR-1 ZR-2 ZR-3 ZR-4

VT1 VT2 VT3

Figure 3.9. Simple transmission network with impedance relays

The module “ImRe.mdl” contains the network models shown in Figure 3.9. To use
the model put the file into the default working directory of MATLAB (typically
MATLAB/BIN), run MATLAB and type "ImRe".

The following are useful hints on how to use the model:

• Double-click on an element to change its parameters or see what is inside the
element.
• Double-click on a scope to open it and see the plot.
• Use the zooming buttons of the plot to zoom in or out.
• Highlight (click-on) and press DEL to delete a given connection between two
blocks.
• Draw a line between the terminals to connect the elements.

3.2.2 Exercises

Exercise 1

Disconnect the fault and run simulation for the sound system. Read and explain
 118

the values of impedances measured by all four relays (to read the impedance, open a
given relay). Do the relays behave correctly?

The ZR-1 measures 39.06 + j13.46 (Ω secondary). This value results from the
existing bus voltage (close to the rated value) and the load current at CT-1. The
impedance is far away from the ZR-1 zones and the relay does not trip (correct
operation). Both the reactance and the resistance measured by ZR-1 are positive which
means that both the active and reactive power flow from the bus 1 towards the bus 2
(bus 1 is exporting the power through the line 1).

The ZR-2 measures -38.48 - j7.44 (Ω secondary). This value results from the
existing bus voltage (close to the rated value) and the load current at CT-2 (same as at
CT-1 but in opposite direction - that is why the values have inverted sign). The
impedance is far away from the ZR-2 zone and the relay does not trip (correct
operation). Both the reactance and resistance measured by ZR-2 are negative which
means that both the active and reactive powers flow from the bus 1 towards the bus 2
(bus 2 is importing power through the line 1).

The ZR-3 measures 143.1 - j12.2 (Ω secondary). This value results from the
existing bus voltage (close to the rated value) and the load current at CT-3. The
impedance is far away from the ZR-3 zone and the relay does not trip (correct
operation). The resistance measured by ZR-3 is positive meaning the active power
flows from the bus 2 towards the bus 3, the reactance is negative meaning the reactive
power is imported from the bus 3.

The ZR-4 measures -142.6 + j18.2 (Ω secondary). This value results from the
existing bus voltage (close to the rated value) and the load current at CT-4. The
impedance is far away from the ZR-4 zone and the relay does not trip (correct
operation). The resistance measured by ZR-4 is negative meaning the active power
 119

flows from the bus 2 towards the bus 3, the reactance is positive meaning the reactive
power is exported by the bus 3.

Exercise 2

Place the fault with zero fault resistance in the middle of the line 1, disconnect the
trip signal of all the relays and run simulation. Read and explain the values of
impedances measured by all four relays.

The ZR-1 measures 0.239 + j2.47 (Ω secondary). The portion of the line 1
impedance between the fault and relay location is (2+j20) x 0.4 / 3.45 = 0.232 + j2.32
(Ω secondary). Observe that both the resistance and the reactance measured by ZR-1
are proportional to the distance between the relay and the fault (the small differences
result from the fault model incorporating some small series reactance). The measured
value falls into the first zone of ZR-1, and the relay trips after 19 msec. The fault is not
cleared since the trip signal from ZR-1 to CB-1 is disconnected.

The ZR-2 measures 0.32 + j3.70 (Ω secondary). The portion of the line 1
impedance between the fault and relay location is (2+j20) x (1 - 0.4) / 3.45 = 0.348 +
j3.48 (Ω secondary). Observe, that both the resistance and reactance measured by ZR-2
are proportional to the distance between the relay and the fault (the small differences
result from the fault model incorporating some small series reactance). The measured
value falls into the first zone of ZR-2, and the relay trips after 24 msec. The fault is not
cleared since the trip signal from ZR-2 to CB-2 is disconnected.

The ZR-3 measures -0.54 - j3.57 (Ω secondary). Observe that both the resistance
and reactance measured by ZR-3 are negative meaning the fault in the backward
direction. The zones 1 and 2 of ZR-2 do not operate (correct behavior).

The ZR-4 measures 1.13 + j9.59 (Ω secondary). Observe, that both the resistance
 120

and reactance measured by ZR-4 are positive indicating that the fault in the forward
direction. The measured value does not fall into the second zone, but it will in the third
zone. ZR-4 would trip for this fault as back-up protection.

Exercise 3

Repeat exercise 2 but for a fault resistance of 75 Ω. Observe and explain the
impedances measured by ZR-1.

The ZR-1 measures 17.52 + j3.58 (Ω secondary). The portion of the line 1
impedance between the fault and ZR-1 is (2+j20) x 0.4 / 3.45 = 0.232 + j2.32 (Ω
secondary). Observe that the resistance is not a measure of the distance to the fault.
The reactance also got significantly corrupted: instead of 2.32, the relay sees 3.58. This
means that the fault actually located at 40% of the line is seen at 3.58/5.80 x 100% =
62% of the line length. This phenomenon is called ‘underreaching’ and may cause the
relay to fail to operate for internal faults located close to the far end busbar.

Exercise 4

Repeat exercise 3 but for the source A voltage of 138kV (opposite power flow
direction). Observe and explain the impedances measured by ZR-1.

The ZR-1 measures 17.52 + j1.13 (Ω secondary). The portion of the line 1
impedance between the fault and location of ZR-1 is (2+j20) x 0.4 / 3.45 = 0.232 +
j2.32 (Ω secondary). Observe, that the reactance got significantly corrupted but in the
opposite direction comparing with the previous situation: instead of 2.32, the relay sees
1.13. This means that the fault actually located at 40% of the line is seen 1.13/5.80 x
100% = 19% of the line length. This phenomenon is called overreaching and may
cause the relay to operate falsely for external faults located close to the far end busbar.
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Exercise 5

Set the system A voltage back to 158kV, connect the relays to their CBs and apply
zero fault resistance. Observe the system and explain its behavior. What is the fault
clearing time?

The ZR-1 sees the fault in the first zone and operates after 18 msec. The CB-1
interrupts the fault current (Figure 3.10) and the fault is cleared 34 msec after the fault.
The bus 1 voltage drops during the fault and recovers as the faulted line gets
disconnected (Figure 3.11).

Figure 3.10 Current at CT-1 during a fault on the line 1 at 40% of its length

Figure 3.11 Voltage at bus 1 during a fault on the line 1 at 40% of its length
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The ZR-2 also sees the fault in the first zone and operates after 24 msec. The CB-2
interrupts the fault current (Figure 3.12) and the fault is cleared 44 msec after the fault.
The bus 2 voltage drops during the fault and recovers as the faulted line gets
disconnected (Figure 3.13).

The relays ZR-3 and ZR-4 do not operate (correct behavior).

The protection system works properly - the faulted line got disconnected and the
loads are supplied through the healthy lines.

Figure 3.12 Current at CT-2 during a fault on the line 1 at 40% of its length

Figure 3.13 Voltage at bus 2 during a fault on the line 1 at 40% of its length

Exercise 6

Place the fault at 10% of the line 2. Observe the system and explain its behavior.
What is the fault clearing time?
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The ZR-3 sees the fault in its first zone and operates after 18 msec. The trip signal
of ZR-3 gets transferred to CB-4 and both CB-3 and CB-4 open (Figure 3.14 and
Figure 3.15). ZR-4 normally would see this fault in the second zone and operate with a
delay. Due to the communication scheme the fault is cleared fast from both the ends of
the line 2. ZR-4 does not operate at all because the fault is cleared before the zone 2
time delay elapses. The relays ZR-1 and ZR-2 do not operate (correct behavior).

Figure 3.14 Current at CT-3 during a fault on the line 2 at 10% of its length

Figure 3.15 Current at CT-4 during a fault on the line 2 at 10% of its length

The protection system works properly - the faulted line got disconnected and the
loads are supplied through the healthy lines.

Exercise 7

Repeat the previous exercise but disconnect the control signal of CB-3 to simulate the
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breaker failure. Observe the system and explain its behavior. What is the fault clearing
time?

The ZR-3 sees this fault in the first zone and trips immediately. The trip signal is
transferred to the opposite end CB and the faulted line is disconnected from the system
B (Figure 3.16). However, CB-3 fails to operate and the fault is not cleared. ZR-1 sees
this fault in its second zone and operates by opening CB-1 (Figure 3.17). The fault gets
disconnected from the system A but the healthy line 1 is lost and the load 2 is left
without a supply.

Figure 3.16 Current at CT-4 during a fault on the line 2 at 10% of its length

Figure 3.17 Current at CT-1 during a fault on the line 2 at 10% of its length

The protection system operates correctly. ZR-1 trips as a back-up relay. The fault
is cleared after in 80 msec.
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Exercise 8

Reconnect the control signal to CB-3. Place the fault at the bus 2 and predict
behavior of the protection system. Observe and comment the impedance measured by
ZR-2 and ZR-3.

Since the bus 2 does not have any protection modeled, the fault is not cleared.
However, ZR-1 and ZR-4 see this fault in their second zones and operate the breakers
CB-1 and CB-4 respectively acting as back-up protection (Figure 3.18 and
Figure 3.19).

Figure 3.18 Current at CT-1 during a fault at the bus 2

Figure 3.19 Current at CT-4 during a fault at the bus 2

For both ZR-2 and ZR-3, the fault in the backward direction, but located at the distance
0. Therefore, they measure very small negative values of the resistance and reactance.
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In practice, the measured impedance may accidentally fall into the first zone causing
false trips. The actual impedance relays must be thus equipped with a special
directional element that would sense the direction and block the relay in the backward
direction.

Exercises

Repeat the calculations and simulations described in above sections for the
following data:
* System A voltage: 150kV, 0 deg.
* System A impedance: 1.2 + j8 Ω
* System B voltage: 138kV, -18 deg
* System B impedance: 0.8 + j11 Ω
* Line 1 impedance: 2 + j17 Ω
* Line 2 impedance: 2 + j25 Ω
* Load 1: 138kV, 100MW, 20MVAr
* Load 2: 138kV, 90MW, 30MVAr
* Load 3: 138kV, 110MW, 20MVAr
* CB-1 operating time: 25 msec
* CB-2 operating time: 37 msec
* CB-3 operating time: 25 msec
* CB-4 operating time: 20 msec
* CT-1, CT-2, CT-3, CT-4: 1500/5A
* VT-1, VT-2, VT-3: 138kV/100V

3.3 Differential Relaying

3.3.1 Software Modules

The software modules provided in this section help to learn how to protect a
transmission network using differential relays. Particularly, the following issues are
elaborated: setting differential relays and analysis of the network and relay operation
under variety of loading and fault conditions.
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Load1 Load2 Load3

BUS-1 BUS-2 BUS-3

CT1 CB1 CB2 CT2 CT3 CB3 CB4 CT4

A Line 2
B
Line 1

DR-1 DR-2

Figure 3.20. A simple transmission network with impedance relays

The module “DiRe.mdl” contains the network models shown in Figure 3.20. To
use the model put the file into the default working directory of MATLAB (typically
MATLAB/BIN), run MATLAB and type "DiRe".

The following are useful hints on how to use the model:

• Double-click on an element to change its parameters or see what is inside the
element.
• Double-click on a scope to open it and see the plot.
• Use the zooming buttons of the plot to zoom in or out.
• Highlight (click-on) and press DEL to delete a given connection between two
blocks.
• Draw a line between the terminals to connect the elements.

3.3.2 Exercises

Exercise 1

Disconnect the fault and run simulation for the sound system. Read and explain the
values of differential and restraining currents measured by DR-1 and DR-2 (to read the
currents, open the block of a given relay). Do the relays behave correctly?

The current flowing through the line 1 is 1.05kA (primary). This current measured
at CT-1 reads 2.625 A (secondary) and measured at CT-2 reads 0.525 A (secondary).
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The i-1 current is re-scaled by the DR-1 and the value of 2.625 A x 0.2 = 0.525 A is
used when forming the differential and restraining currents of the DR-1. Consequently,
the differential current of DR-1 reads practically zero while the restraining current is
1.045 A (secondary). The later value is the load current doubled. The DR-1 does not
trip (correct behavior).

The current flowing through the line 2 is 286 A (primary). This current measured
at CT-3 reads 0.715 A (secondary) and measured at CT-4 reads 0.715 A (secondary).
The i-1 current is re-scaled by the DR-2 and the value of 0.715 A x 1 = 0.715 A is used
when forming the differential and restraining currents of the DR-2. Consequently, the
differential current of DR-2 reads practically zero while the restraining current is 1.431
A (secondary). The later value is the load current doubled. The DR-2 does not trip
(correct behavior).

Exercise 2

Repeat the previous case but model a 10% inaccuracy of the CT-1 by changing its
rated secondary current from 5A to 4.5A. Read and explain the values of differential
and restraining currents measured by the DR-1. Does the relay behave correctly?

The current flowing through the line 1 is 1.05kA (primary). But now, this current
measured at CT-1 reads 2.36 A (secondary) instead of 2.625 A (secondary). This
secondary current gets re-scaled to 2.36 A x 0.2 = 0.472 A (secondary). The secondary
current measured at CT-1 is still 0.525 A (secondary). Consequently, the differential
current of the DR-1 is 0.525 - 0.472 = 0.053 A (secondary). The restraining current is
0.525 + 0.472 = 0.997 A (secondary). Note that the differential current is still low and
the restraining current basically reflects the load current. The DR-1 operates correctly:
the differential current is below the pick-up threshold and the relay does not trip.
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Exercise 3

Repeat the previous case but place the fault on the line 2 at 20% from the bus 2.
Disconnect the trip signals of DR-2 in order to model a permanent fault. Read and
explain the values of differential and restraining currents measured by DR-1 and DR-2.
Do the relays behave correctly?

The current flowing through the line 1 is 4.46 kA (primary). This value seen
through the CT-2 is about 2.23 A (secondary) and through the CT-1 as 4.46 / 2 x 4.5 =
10.04 A (secondary). The mismatch results in the false differential signal of the
magnitude of 0.21 A. This value overruns the pick-up threshold (0.2A) and the DR-1 is
active. The restraining current, however, is about 4.1 A (fault current doubled through
the line 1). The bias is 0.3 x 4.1 A = 1.23 A which is much higher than the differential
current (0.21A), and consequently, the DR-1 does not trip (correct behavior).

The current flowing through the line 2 at CT-3 is 4.4 kA (primary). This value seen
through the CT-3 is about 11 A (secondary). The current at CT-4 is 5.44 kA (primary)
and is seen through the CT-4 as 13.6 A (secondary). The differential current is 23.62 A
(secondary) which forces DR-2 to pick-up. The bias is 3.76 A x 0.3 = 1.13 A which is
far less than 23.62 A and the DR-2 trips immediately (correct behavior).

Exercise 4

Repeat the previous case but re-connect the trip signals of DR-2. Observe
operation of the relays. Do the relays behave correctly?

The DR-2 trips immediately, the fault is cleared after the time delay of the CB-3
and CB-4. The faulty line no. 2 gets removed from service (Figure 3.21 and
Figure 3.22). The relay DR-1 does not trip and the sound line 1 keeps operating
supplying the load 2 (Figure 3.23and Figure 3.24). The relays behave correctly.
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Figure 3.21 Current at CT-3 (secondary) during a fault on the line 2

Figure 3.22 Current at CT-4 (secondary) during a fault on the line 2

Figure 3.23 Current at CT-1 (secondary) during a fault on the line 2

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Figure 3.24 Current at CT-2 (secondary) during a fault on the line 2

Exercise 5

Place the fault in the middle of the line 1. Observe operation of the relays. Do the
relays behave correctly?

The DR-1 trips immediately. The fault is cleared after the operating time of the
CB-1 and CB-2 has expired. The faulty line no. 1 gets removed from service
(Figure 3.25 and Figure 3.26). The relay DR-2 does not trip and the sound line 2 keeps
operating supplying the load 2 (Figure 3.27 and Figure 3.28). The relays behave
correctly.

Figure 3.25 Current at CT-1 (secondary) during a fault on the line 1

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Figure 3.26 Current at CT-2 (secondary) during a fault on the line 1

Figure 3.27 Current at CT-3 (secondary) during a fault on the line 1

Figure 3.28 Current at CT-4 (secondary) during a fault on the line 1

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Exercise 6

Repeat the previous simulation for various fault resistances and find the maximum
fault resistance under which the DR-1 operates.

The DR-1 operates for the fault in the middle of the line 1 with resistance up to
about 152 Ω (Figure 3.29and Figure 3.30). This shows that although fast and very
robust, the differential principle has its limitations too.

Figure 3.29 Current at CT-1 (secondary) during a fault on the line 1 with the 152 Ω
fault resistance

Figure 3.30 Current at CT-2 (secondary) during a fault on the line 1 with the 152 Ω
fault resistance
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Exercises

Repeat the calculations and simulations described in section 4 for the following
data:
• System A voltage: 158kV (114% of 138kV), 0 deg.
• System A impedance: 1 + j10 Ω
• System B voltage: 138kV, -15 deg.
• System B impedance: 1 + j10 Ω
• Line 1 impedance: 2 + j20 Ω, fault location 0.5
• Line 2 impedance: 2 + j20 Ω, fault location 0.5
• Load 1: 138kV, 100MW, 30MVAr
• Load 2: 138kV, 100MW, 30MVAr
• Load 3: 138kV, 100MW, 30MVAr
• Fault: 0 Ω, inception time 20 msec.
• CB-1 operating time: 15 msec
• CB-2 operating time: 25 msec
• CB-3 operating time: 18 msec
• CB-4 operating time: 21 msec
• CT-1: 1600/1A
• CT-2: 1600/5A
• CT-3: 1500/1A
• CT-4: 2000/1A
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4. MODELING OF DIGITAL RELAY AND POWER SYSTEM

4.1 Software Modules for Modeling Elements Library

4.1.1 Bias Characteristic

This element compares two input signals using a bias characteristic. Two inputs
feed this block. The first is the operating and the second is the restraining signal. Both
signals are given in instantaneous values. The output of this block is the result of the
comparison using the bias characteristic. Its value is one if the operating signal is
greater than the bias characteristic at the given restraining, otherwise it is zero.

The module “BCex.mdl” is available for this function. Figure 4.1 shows an
example of the bias characteristic block. In simulation, Ode45 (Dormand-Prince) is
recommended. There is no need for time step for this solver. The discrete solver can
also be used.

Figure 4.1 Example for the Bias Characteristic block

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Example 1

In the following example, the Bias characteristic block has the following bias
characteristic: [0 0; 15 15; 30 0]. The operating signal is a sinusoidal signal of
amplitude 5 and a DC component of 5 as shown in Figure 4.2. The output is given in
Figure 4.3.

Figure 4.2 Operating and Restraining signals

Figure 4.3 Output of the block

4.1.2 Basic Measurements

This module givens the current and voltage signals in the orthogonal form,
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computes their amplitudes, as well as the active and reactive power and impedance
components. The orthogonal components take the voltage and current at the present
sampling time, and obtain the magnitude of the current and voltage as well as the
complex power and impedance. The outputs may be filtered. Two types of filters, mean
and median, are implemented. All filters may have different length of their data
windows.

The module “bmex.mdl” is available for this function. Figure 4.4 shows an
example of the BM block. This block has discrete states only, so the discrete solver can
be used if there is no need to use the DAB. In this case the time step should be selected
so that all the harmonics of the signal can be detected. If the model uses the DAB, as in
the example shown below, the ode-45 (Dormand-Prince) solver is recommended. For
this solver a time step does not need to be specified.

Example 2

An example with this block is shown in Figure 4.4. The results are shown in
Figure 4.5. The voltage signal in this case goes from a magnitude of 7 to a magnitude
of 4 when the fault occurs. Note that in block BM1 there is no post-filtering, while in
BM2 median post-filtering was used. For that reason, BM2, filters out the high
frequency noise signal, though there is a delay added to the signal. This delay is caused
by the post-filtering method. The window size used for both blocks is 40.

4.1.3 Data Acquisition Board

This module performs analog filtering, signal conditioning and sampling. The
input of this block is a single analog signal. The output of this block is a buffer with the
input signal samples.
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Figure 4.4 Example for the BM block

Figure 4.5 Simulation results for BMea.mdl

This block enables modeling and simulation of the analog anti-aliasing filter,
analog signal conditioner, and Analog to Digital converter (A/D). The components of
this block are shown in Figure 4.6. The module “dabex.mdl” is available for the DA
 139

function. Figure 4.7 shows an example of the DA block. In simulation the ode-45
(Dormand-Prince) solver is recommended. For this solver a time step does not need to
be specified.

Input Analog Signal Analog/Digital Data

Buffer
signal Filter Conditioner Converter Window

DATA ACQUISITION BOARD

Figure 4.6 Data Acquisition Block

Example 3

The following diagram shows an example of the use of the DAB. In this example a
fault signal is feed into the DAB. The sampling rate is 20 samples/cycle of the
fundamental frequency of 60 Hz. Second order Bessel approximation is used for the
analog filter. The cut-off frequency is 200 Hz and the vertical resolution used is 12 bits.
The analog input and digital output for this example are shown in Figure 4.7.

Figure 4.7 Example for the Data Acquisition Block (dabex.mdl)

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Figure 4.8 Input and output signals for dabex.mdl

4.1.4 Directional Element

This module implements a function of a directional element. The operating

characteristic is defined by two angles. It has two phasor inputs: voltage and current;
and one output. Its value is one when the current phasor falls into the operating
characteristic and zero otherwise.

The module “DE_1ex.mdl” is provided for this function. Figure 4.9 shows an
example of the direction element block.

Example 4

The following example shows how the DE_1 block works. Figure 4.9 shows the
block diagram for the example. In this case, α= 10o, β=170o and the input voltage
phasor is 1∠0°. The current phasor, on the other hand has a constant magnitude of one,
but its phase increases. In Figure 2, the results of the simulation are shown. Note that
the output is zero, whenever the difference between the voltage and current phases is in
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the ranges 0-10o and 170-360o. The output is one whenever the relative angle is in the
range 10-170o.

Figure 4.9 Example for the DE_1 block (DE_1ex.mdl)

Angle between V and I (degrees)

400

300

200

100

0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (seconds)

0.8

0.6
output

0.4

0.2

0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (seconds)

Figure 4.10 Simulation results for Dele.mdl

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4.1.5 Differential Equation based Impedance Measurement

This module measures the impedance based on the differential equation approach.
It takes samples of the instantaneous value of the voltage and current signals as input
while outputs resistance and reactance signals calculated by the block. The module
“deimex.mdl” is provided for this function. Figure 4.11 an example of the DEIM
block.

Example 5

The following example shows the operation of the DEIM block. The impedance
components are shown for the cases with median filtering and with no post-filtering.
Note that the transients in both signals are greatly reduced when post-filtering is used.

Figure 4.11 Example for the DEIM block

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Impedance Components (Median post-filtering)

12

10

-2
0 0.02 0.04 0.06 0.08 0.1
Time (seconds)

Figure 4.12 Simulation results for deimex.mdl (Mean post-filtering)

Impedance Components (No post-filtering)

12

10

-2

-4
0 0.02 0.04 0.06 0.08 0.1
Time (seconds)

Figure 4.13 Simulation results for deimex.mdl (No post-filtering)

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4.1.6 Digital Filter

This module provides basic functions of a digital filter. Input includes data
window of a sampled signal. It outputs data window which contains the filtered signal.
The module “dfex.mdl” provides the filtering function. Figure 4.14 shows an example
of a filter block.

Example 6

In the following example a discrete signal with frequency components at 60 Hz

and 120 Hz is filtered using the filter block. The fundamental frequency is 60 Hz and
the input data window length is 20 samples. The length of output data window is one
sample.

Figure 4.14 Example for the DF block (dfex.mdl)

4.1.7 Digital Fourier Transform

This module computes phasors of up to 5 selected harmonics of the input signal. It

takes a data window which contains samples of a continuous signal as input while it
outputs the magnitude and phase of the harmonics components of the input signal
 145

specified in the dialog menu. The module “dfttex.mdl” provides this function.
Figure 4.16 shows an example of DFT block. In simulation the Ode 45
(Dormant-Prince) can be used if the DAB is used. No time step is needed for this case.
If only discrete signals are used in the model, the discrete solver can be used.

Input and Output signals

2

1.5

0.5

-0.5

-1

-1.5

-2
0 0.01 0.02 0.03 0.04 0.05 0.06
Time (seconds)

Figure 4.15 Simulation results for dfttex.mdl

Example 7

In the following example a signal composed by a DC component, the fundamental

frequency and the third harmonic is applied to the DFT block. The analytical
expression for the input signal is the following:

F(tx)= 5+10*cos(2*pi*60*tx)+30*cos(3*2*pi*60*tx-pi/180*150)

The multiples of the fundamental frequency requested are: 0, 1, 2, 3, 4. It can be

noted from the figure that the harmonics that are not zero are the DC, fundamental and
third components.
 146

Figure 4.16 Example for the DFT block

4.1.8 Orthogonal Components

This module captures the data window of the sampled signal and computes
magnitude and phase angles of the signal using the orthogonal components of the
signal (i.e. cosine and sine components). It takes a data window of a sampled signal as
input while outputs the orthogonal components of the signal which include amplitude
and angle (in degrees). The module “ocex.mdl” provides the OC function. Figure 4.17
shows an example of the OC block.

Example 8

In the following model the OC block is used to obtain the phase angles of a
sinusoidal signal of amplitude one and a phase of zero degrees. The fundamental
frequency is 60 Hz and the sampling frequency is 60 samples/cycle.
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Figure 4.17 Example for the OC block (ocex.mdl)

Input signal and Estimated magnitude

1.5

0.5

-0.5

-1

-1.5
0 0.02 0.04 0.06 0.08 0.1
Time (seconds)

Figure 4.18 Simulation of ocex.mdl (magnitude of the signal)

 148

Angle of the signal (Degrees)

200

150

100

50

-50

-100

-150

-200
0 0.02 0.04 0.06 0.08 0.1
Time (seconds)

Figure 4.19 Simulation of ocex.mdl (angle of the signal)

4.1.9 Symmetrical Components

This module computes the symmetrical components from three phase signals. The
inputs are the three-phase signals. They can be given in instantaneous form (3 inputs)
or in orthogonal form (6 inputs) given in polar representation (phase in degrees). The
outputs are given in instantaneous or orthogonal form depending of the form selected
for the inputs. There will be three outputs if the instantaneous form or six outputs if the
orthogonal form is selected.

The module “scex.mdl” provides the computational function of symmetrical

components. Figure 4.20 shows an example of the SC block. The recommended solver
is Ode-45 (Dormand-Prince) solver, as this block usually requires the DAB. For this
solver a time step does not need to be specified.

Example 9

The following model obtains the symmetrical components from a three-phase

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balanced signal of amplitude one.

Figure 4.20 Example for the SC block (scex.mdl)

-15 Symmetrical Components
x 10
2
Zero sequence

0 0.01 0.02 0.03 0.04 0.05 0.06

1
Positive sequence

-1
0 0.01 0.02 0.03 0.04 0.05 0.06
Negative sequence

0.4

0.2

0
0 0.01 0.02 0.03 0.04 0.05 0.06

Figure 4.21 Simulation results for scex.mdl

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4.1.10 Triggering Element

This module functions as a fault detector. The input is an array with the most
recent sample and n-1 previous samples of a signal. Where n is the size of the data
window. A signal that goes from low to high after there is a sudden change in the
magnitude of the input signal and the activating counter reaches its pre-set value. The
output goes again to low after the magnitude of the input signal is stable and the
deactivating counter reaches its pre-set value.

The module “trex.mdl” provides the fault triggering function. Figure 4.22 shows an
example of the TR block. This block has discrete states only, so the discrete solver can
be used if there is no need to use the DAB. In this case the time step should be selected
so that all the harmonics of the signal can be detected. If the model uses the DAB, as in
the example shown below, the Ode-45 (Dormand-Prince) solver is recommended. For
this solver a time step does not need to be specified.

Example 10

In the following example a fault occurs at t= 0.03 seconds and the magnitude of
the input signal goes from 1 to 2 at that time. There are high frequency components
added due to the fault. The DAB filters these components and feeds the TR block with
a data window of size 20. The triggering element uses a cycle to cycle comparison
method. The threshold is 0.5, the activating counter is 2 and the deactivating counter is
5. It can be noted in Figure 2 that the triggering signal goes to high short after the fault
occurs (the delay is given by the activating counter) and goes to low again at around t=
0.11 seconds. Note that after that time the difference of the sample at the present time
and the sample of one cycle before is less than the threshold specified in the
parameters i.e. the fault is stable.
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Figure 4.22 Example for the TR block (trex.mdl)

Figure 4.23 Simulation result for trex.mdl

4.1.11 Universal Comparator

This module performs signal comparisons of three types: signal-to-signal,

signal-to-threshold and signal-to-time. If the signal-signal comparison option is
selected, two inputs feed this block. Otherwise the block needs only one input. In all
cases the signals are given in instantaneous form. If the signal-to-signal or
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signal-threshold comparison is selected, the output is one if the comparison specified

in the dialog menu is true and zero otherwise. If the signal-time comparison is selected,
the output is one or zero depending of the location of the input signal in the signal–
time characteristic selected and of the I-t emulation method.

The module “ucex1.mdl” provides the function. Figure 4.24 shows an example of
the UC block.

Example 11

In the following example the UC is used to compare a signal against a threshold.

The sign of the comparison is >, the threshold is 0.8, and the ratio of reset to pickup is
0.5.

Figure 4.24 Example 1 for the UC block (ucex1.mdl)

The corresponding input-output plot is shown in the Figure 4.25.

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Figure 4.25 Input-Output plot for simulation of ucex1.mdl

Another example using the UC block is shown below. The options are: signal-time
comparison, type of time dependency: standard inverse, pick-up value: 1, ratio of reset
to pick-up: 1, I-t emulation method: integration and time parameter of 0.1 seconds.
Note that the input signal goes to zero at t= 0.7 s and back to one at t=0.72 s. This reset
the UC block and delays the operating time.

Figure 4.26 Example 2 for the UC block (ucex2.mdl)

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Figure 4.27 Input-Output plot for ucex2.mdl

4.1.12 Phase Selection

This module functions as a fault classification algorithm. The inputs of this block
are the three phase voltage and currents in phasor form i.e. magnitude and angle (in
degrees). There is only one output. It is a number that identifies the type of fault
detected. If there is no fault, the output is zero.

The module “psex.mdl” provides the phase selection function. Figure 4.28 shows
an example of the phase selection block. For this block, the discrete solver can be used
if there is no need to use the DAB to obtain the orthogonal components. In this case the
time step should be selected so that all the harmonics of the signal can be detected. If
the model uses the DAB, as in the example shown below, the ode-45 (Dormand-Prince)
solver is recommended. For this solver a time step does not need to be specified.

Example 12

In the following example an A-B-G fault is simulated. The PS block detects a fault
of type 4, which corresponds to an A-B-G fault. The current-only method is used in
this case.
 155

Figure 4.28 Example for the phase selection block (psex.mdl)

Figure 4.29 Calculation of the orthogonal components of phase voltages in Figure 4.28
 156

Figure 4.30 Calculation of the orthogonal components of phase currents in Figure 4.28

4.1.13 Vector Group Compensator for 2-Winding Transformers

This module computes the differential and restraining currents from the
instantaneous values of six phase currents of a 2-winding transformer. It has three
inputs. They are the instantaneous values of the three-phase currents. The outputs are
the instantaneous values of the differential and restraining currents for each phase.

The module “vg2ex.mdl” provides the compensation function. Figure 4.31 shows
an example of the VG-2 block.

Example 13

In the following example, a fault occurs in phase A of a delta-wye transformer at

t=0.03 seconds. The differential and restraining currents obtained by the VG-2 block
are shown in Figure 4.32 and Figure 4.33.
 157

Figure 4.31 Example for the VG-2 block (vg2ex.mdl)

Figure 4.32 Differential currents

 158

Figure 4.33 Restraining currents

4.1.14 Zone Comparator

This module performs the zone comparison function. The inputs for this block are
the resistance and reactance signals. The output includes five parts. Each part
corresponds to a zone defined in the dialog menu. An output is set to high if the
impedance signal is within its limits.

The module “zcex.mdl” provides the zone comparison function. Figure 4.34 shows
an example of the function block.

Example 14

In the following example the way the ZC operates is illustrated. The zones are
defined as follows:

Zone 1: [0 0; 1 0; 1 1;0 1]

Zone 2: [0 0; 2 0; 2 2;0 2]

Zone 3: [0 0; 3 0; 3 3;0 3]

Zone 4: [0 0; 4 0; 4 4; 0 4]

Reverse Zone: [0 0; -1 0; -1 -1; 0 -1]

 159

Figure 4.34 Example for the Zone Comparator block

4.2 Interfacing Power System and Relay Models

4.2.1 Analytical Generator

This module generates a signal by providing the equation describing the output
value. The first output is the instantaneous value of the signal generated. The second
output is the time signal, which goes from low to high at the start-up time. The module
“AGex.mdl” provides the analytical generation function. Figure 4.35 shows an
example of the AG block.

Example 15

The following analytical function will be generated:

10*cos(2*pi*60*tx)*exp(-tx/0.03)+2*sin(4*pi*60*tx)+3*sin(6*pi*60*tx)

The start-up time is 1/60 seconds.

 160

Figure 4.35 Example for the Analytical Generator (AGex.mdl)

15

10

-5

-10
0 0.02 0.04 0.06 0.08 0.1

Figure 4.36 AGex.mdl simulation results

4.2.2 Fault Signal Generator

This module generates a short circuit signal using assumed analytical model. There
are two outputs for this block. The first one is the instantaneous value of the fault
signal itself as specified in the parameters. The second one is the time signal, which
goes from low to high at the start-up time. Both outputs are zero before the start-up
time.

The module “FSGex.mdl” provides the fault signal generation function.

 161

Figure 4.37 shows an example of the function block. In simulation the ode45
(Dormand-Prince) is recommended. There is no need for time step for this solver. The
discrete solver can also be used. In this case the time step must be such that all the
harmonics are generated properly

Example 16

Generate a fault signal with the following characteristics:

Pre-fault amplitude: 10

Pre-fault phase(degrees): 45

Fault amplitude: 4

Fault phase(degrees): 90

Fault time: 1.25/60 seconds

DC time constant: 0.0004

Oscillatory components:

Table 4.1 Oscillatory components

Frequenc Amplitu Time
y de Constant
800 1.0 0.05
1000 0.8 0.03
3000 0.9 0.06
 162

Figure 4.37 Model for the FSG example (FSGex.mdl)

Fault Signal
10

-2

-4

-6

-8

-10
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time (seconds)

Figure 4.38 FSGex.mdl Simulation results

4.2.3 Phasor Generator

This module generates of a sinusoid waveform according to the parameters

specified. This block has two outputs. The first one is the instantaneous value of the
sinusoidal signal specified by the parameters. The second one is the time signal, which
is set to high at the start-up time. Before that time, this output is zero. The module
 163

“PGex.mdl” provides the phasor generation function. Figure 4.39 shows an example of
the function block.

Example 18

The Phase Generator is used to generate a sinusoid signal with a magnitude of 10

and phase of 45 degrees. The start-up time is 1.25/60 seconds.

Figure 4.39 Example for the Phase Generator (PGex.mdl)

The results of the simulation are shown in Figure 4.40.

Generated Signal
10

2
Amplitude

-2

-4

-6

-8

-10
0 0.05 0.1 0.15 0.2
Time (seconds)

Figure 4.40 Simulation results for PGex.mdl

4.2.4 Spectrum Generator

This module generates a signal composed from the limited number of sinusoid
 164

waveforms. The first output (x) is the instantaneous value of a signal composed of the
sinusoid waveforms specified in the dialog menu. The second output (t) is a signal that
is set high when the Spectrum Generator is activated. Before this time, this output is
zero.

The module “SGex.mdl” provides the spectrum gneration function. Figure 4.41

shows an example of the function block. In simulation the discrete solver with a step
selected so all the harmonics generated can be detected by the other blocks connected.

Example 19

Generate a signal composed by the following harmonics:

Table 4.2 Signal harmonics

Frequency Amplitude Phase
multipliers (degrees)
0 0.2 0
1/3 0.2 45
1 1 0
3 0.1 90
5 0.15 60
7 0.1 10

The fundamental frequency is 60 Hz.and the start-up time is 1/60 seconds. It can
be seen in Figure 4.41, that the icon for the SG block shows the amplitudes of the
components of the signal in the frequency domain. In Figure 2, the signal generated is
shown. Note that the signal is zero before the start-up time (1/60 seconds).
 165

Figure 4.41 Example for the Spectrum Generator (SGex.mdl)

Figure 4.42 Simulation results for SGex.mdl

4.2.5 Three-phase Phasor Generator

This module generates three sinusoid waveforms according to parameters

specified. The first three outputs of this block are the instantaneous values of the
symmetrical or unsymmetrical phase quantities (phase A, B and C) or the symmetrical
components (0, + and - sequences). The fourth output is the time signal, which goes
from low to high at the start-up time.

The module “TPGex.mdl” provides the phasor generation function. Figure 4.43
shows an example of the function block. In simulation, the ode45 (Dormand-Prince) is
 166

selected. There is no time step needed for this solver. The discrete solver can also be
used. In this case the time step has to be selected according to the frequency of the
signal generated.

Example 20

The Three-phase Generator is used to generate unsymmetrical three-phase signal.

The parameters of the phase signals are the following:

Table 4.3 Parameters of phase signals

Phase Magnitud Phase
e (degrees)
A 5 45
B 2 0
C 1 -30

The start-up time is 1/60 seconds

Figure 4.43 Example for the Three-phase Generator (TPGex.mdl)

 167

Three-phase signals
5

Magnitude
0

-1

-2

-3

-4

-5
0 0.02 0.04 0.06 0.08 0.1
Time (seconds)

Figure 4.44 Simulation results for TPGex.mdl

4.3 GUI and Analysis Tools

4.3.1 Phasor Display

This module displays phasors dynamically on the complex plane. Up to six

phasors (12 inputs) are given in polar form (phase in degrees). The output is graph with
the input phasors in the complex plane. The module “pdex.mdl” provides the display
function. Figure 4.45 shows an example of the PD block.

Example 21

The following example shows how this block works. The phasors at the end of the
simulation time are shown in Figure 4.46.
 168

Figure 4.45 Example for a PD block

Figure 4.46 Phasor Display

 169

5. DESIGNING AND IMPLEMENTATION OF DIFFERENT COMMUNICATION

SCHEMES AND TRIP LOGIC

5.1 Introduction

This chapter provides examples and exercises for different communication

schemes and trip logic used in distance relaying. After completion of this exercise the
reader will have an understanding how these schemes work.

5.2 Communication Schemes

5.2.1 Software Modules

This section shows different communication schemes and trip logic used in a
distance relay. The models were developed in Simulink and simulate the following trip
logics of a commercial relay.
• PUTT (Permissive Underreaching Transfer Trip)
• PUTT+OZ (Permissive Underreaching Transfer Trip with additional overreaching
measurement)
• BLOV+TB (Blocking overreaching with current reversal logic)
• BLOV+UZ+TB (Blocking overreaching with independent measuring zone and
current reversal logic)
• BLUN (Block Underreaching)
• POTT+WEI+TB (permissive overreaching transfer trip with weak infeed logic and
current reversal logic)

The module “PUTT.mdl” has the following components:

• Transmission line model
• Two relays (The relay is composed by a measuring system and a trip logic)
• Communication channel
• Displays
 170

Figure 5.1 Block diagram for transmission line protected by a distance relay (PUTT trip
logic)

Figure 5.1 shows the main structure of the PUTT trip logic for distance relay. The
following examples show the behavior of the relays in cases of different fault locations
on the line and outside the line. It also includes cases of a failure communication
channel.

5.2.2 Examples

PUTT logic

For the following examples, the settings of the relays at both ends of the line are the
same. The settings are shown below, where ZM stands for measured impedance:
• Zone 1: ZM1 = 0.75 p.u, t1 = 0.0 sec,
• Zone 2: ZM2 = 1.30 p.u, t2 = 1.0 sec,
• Zone 3: ZM3 = 1.80 p.u, t3 = 2.0 sec,
• Starter: S = [ -1, 4 ] p.u, t4 = 4.0 sec,
 171

• Undervoltage threshold: U< = 0.80 p.u.

Internal fault at 0.2 p.u.

Fault Conditions:
• Fault location: x = 0.20 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.2 Trip and internal signals of relays at both line ends for internal fault at 0.2
p.u.
Result: the behavior of two relays is correct. Relay A operates in zone 1 and sends the
CS signal to station B, so in this way relay A accelerates operation of relay at bus B,
which normally sees fault in zone 2. Due to the communication channel delay time, relay
B operates 20 msec after relay A.
 172

Internal fault at 0.5 p.u.

Fault Conditions:
• Fault location: x = 0.50 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.3 Trip and internal signals of relays at both ends of line for internal fault at 0.5
p.u.
Result: behavior of the two relays is correct. Both relays A and B operate in zone 1.
There is no delay in relay operation.
 173

Internal fault at 0.9 p.u.

Fault Conditions:
• Fault location: x = 0.90 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.4 Trip and internal signals of relays at both ends of line for internal fault at 0.9
p.u.
Result: behavior of two relays is correct. This case is almost the same as the one
shown in section 4.1.1, but now Relay B operates in zone 1 and sends the CS signal to
 174

station A, so in this way relay B accelerates operation of relay at bus A, which normally
sees fault in zone 2.

External fault at 1.1 p.u.

Fault Conditions:
• Fault location: x = 1.10 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.5 Trip and internal signals of relays at both ends of line for an external fault at
1.1 p.u.
 175

Result: behavior of two relays is correct. Relay A operates in zone 2 and it does not
send the CS signal to station B. Relay B operates in back-up zone after the starter delay
time has elapsed.

External fault at 1.5 p.u.

Fault Conditions:
• Fault location: x = 1.50 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.6 Trip and internal signals of relays at both ends of line for internal fault at 1.5
p.u.
 176

Comment: behavior of two relays is correct. Relay A operates in zone 3 and it does not
send to station B the CS signal. Relay B operates in back-up zone after the starter delay
time has elapsed.

External fault at 2.1 p.u.

Fault Conditions:
• Fault location: x = 2.10 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.7 Trip and internal signals of relays at both ends of line for internal fault at 2.1
p.u.
 177

Result: behavior of two relays is correct. Relay A operates in back-up zone (starter). It
does not send to station B the CS signal. Relay B does not operates at all, because the
fault is outside starter range.

External fault at 5.0 p.u.

Fault Conditions:
• Fault location: x = 5.00 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.8 Trip and internal signals of relays at both ends of line for internal fault at 5.0
p.u.
 178

Result: behavior of two relays is correct. Both relays A and B do not operate at all,
because fault is outside their starter ranges.

External fault at -0.5 p.u.

Fault Conditions:
• Fault location: x = -0.50 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: normal operation (20 msec delay).

Figure 5.9 Trip and internal signals of relays at both ends of line for internal fault at
-0.5 p.u.
 179

Result: behavior of two relays is correct. Relay B operates in zone 2. It does not send
the CS signal to station A. Relay A operates in back-up zone after the starter delay time
has elapsed.

Internal fault at 0.2 p.u. (communication channel fails, erroneous signal = 0)

Fault Conditions:
• Fault location: x = 0.20 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal
= 0.

Figure 5.10 Trip and internal signals of relays at both ends of line for internal fault at
0.2 p.u.
 180

Result: only the behavior of relay A is correct. Relay A operates in zone 1, sends to
station B the CS signal. Because of communication channel failure, relay B does not
receive this signal, so relay B operates in zone 2 (there is no acceleration of operating of
relay at station B).

Internal fault at 0.2 p.u. (communication channel fails, erroneous signal = 1)

Fault Conditions:
• Fault location: x = 0.20 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal
= 1.

Figure 5.11 Trip and internal signals of relays at both ends of line for internal fault at
0.2 p.u.
 181

Result: only the behavior of relays A is correct. Relay A operates in zone 1, sends to
station B the CS signal. Because of the communication channel failure relay at station B
sees always the CR signal (even before fault). This is a reason why the relay at bus B
operates immediately after fault and in fact does not wait for the CR signal from bus A.

External fault at -0.5 p.u. (communication channel fails, erroneous signal=0)

Fault Conditions:
• Fault location: x = -0.50 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal
= 0.

Figure 5.12 Trip and internal signals of relays at both ends of line for internal fault at
-0.5 p.u.
 182

Result: behavior of both relays is correct (pilot channel does not affect the relays’ work)
Relay A operates in back-up mode (starter), and relay B operates in zone 3.

External fault at -0.5 p.u. (Communication channel fails, erroneous signal=1)

Fault Conditions:
• Fault location: x = -0.50 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal
= 1.

Figure 5.13 Trip and internal signals of relays at both ends of line for internal fault at
-0.5 p.u.
 183

Result: behavior of both relays is NOT correct. Relays A and B operate immediately,
though relay A should operate after 4 seconds (back-up mode/starter), and relay B after 2
second in 3rd zone. Because of the erroneous signal from communication channel and
the operation of the starters (S * CR is TRUE) both relays operate wrong.

External fault at 2.1 p.u. (communication channel fails, erroneous signal=0)

Fault Conditions:
• Fault location: x = 2.10 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,Communication channel:
operation failure (20 msec delay), erroneous signal
= 0.

Figure 5.14 Trip and internal signals of the relays at both ends of line for internal fault
at 2.1 p.u.
 184

Result: behavior of both relays is correct (pilot channel doesn’t affect the relays’
operation) Relay A operates in back-up zone (starter). Relay B does not operate at all.

External fault at 2.1 p.u. (communication channel fails, erroneous signal=1)

Fault Conditions:
• Fault location: x = 2.1 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal
= 1.

Figure 5.15 Trip and internal signals of relays at both ends of line for internal fault at
2.1 p.u.
 185

Result: The behavior of both relays is NOT correct. Relays A and B operate
immediately, but the fault is very far away from the protected line. Only relay A should
operate after 4 seconds in back-up mode, while relay B should not operate at all.
However, relay A operates because it sees the erroneous CR signal and pick-up of starter.
Relay B operates because of the erroneous CR signal and the operation of the
undervoltage element.

External fault at 4.2 p.u. (communication channel fails, erroneous signal=0)

Fault Conditions:
• Fault location: x = 4.20 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: failure operate (20 msec delay), erroneous signal =
0.

Figure 5.16 Trip and internal signals of relays at both ends of line for internal fault at
4.2 p.u.
 186

Results: behavior of both relays is correct (pilot channel does not affect the relays’
operation). Fault is outside of starters’ range. Therefore the relays do not operate.

External fault at 4.2 p.u. (communication channel fails, erroneous signal=1)

Fault Conditions:
• Fault location: x = 4.20 p.u.,
• Fault time: t = 0.50 sec,
• Post-fault voltage at bus A: Va = 0.90 p.u.,
• Post-fault voltage at bus B: Vb = 0.75 p.u.,
• Communication channel: operation failure (20 msec delay), erroneous signal = 1.

Figure 5.17 Trip and internal signals of relays at both ends of line for internal fault at
4.2 p.u.
 187

Result: behavior of relay B is NOT correct. Relay B operates immediately, but the fault
is very far away from protected line, or there is no fault at all, but only temporary voltage
drop in power system (e.g. because of starting high-power generators). Relay B operates
because of the erroneous CR signal and operation of the undervoltage element.

PUTT+OZ logic

For all the examples in this section, the system parameters have the following

values:

Zone 1 (ZM1) 0.6

Overreach Zone (ZOV) 1.2

Zone 2 (ZM2) 1.8

Zone 3 (ZM3) 2.5

Starter Zone (S) 4.0

Zone 2 Delay (T2) 0.5

Zone 3 Delay (T3) 0.8

Starter Delay (T4) 1.0

The fault time for all the examples is 0.2 seconds.

Fault at x=0.5. Zone 1 operation for both relays

Result: For the system parameters specified above the results obtained from the

simulation for zone 1, 60% of unit line length, is shown in Figure 5.18.
 188

(a) Trip A (b) CS A

(c) Trip B (d) CS B

Figure 5.18 Results for fault at x=0.5, zone 1 operates for both relays

The fault is considered to be within Zone 1 of the relay located at terminal A.

Upon seeing the fault within its primary zone, relay A sends the CS signal to relay B at
the opposite end of the system also causing the relay at terminal B to operate along
with relay at terminal A. Since the fault is also located within the primary zone of
relay B, this relay also sends the CS signal to relay A. So we have both the relay
tripping and both of them issuing the CS signal to one another.

Fault at x=0.8. Zone 1 operation for Relay A and overreach for relay B.

Result: For the system parameters specified above the results for the simulation
 189

for the fault located within the overreach zone of relay A which is specified at 120% of
unit line length are shown below in Figure 5.19.

(a) Trip A (b) CS A

(c) Trip B (d) CS B

Figure 5.19 Results for fault at x=1.5, zone 1 operates for Relay A and overreach for
Relay B

The fault located at the specified point is seen by relay B as a fault in its primary
zone and sends a CS signal to relay at terminal A. Since the fault is also located
within the overreach zone for relay A and with the existence of the communication
signal, CS relay A also trips. However, since the fault is not located in the primary
zone for relay A, this relay doesn’t send a CS signal.
 190

Fault at x=1.5. Zone 2 operation for Relay A.

Result: Simulation for a fault located in zone 2 (180% of the unit line length for

relay located at terminal A) is conducted using the specified parameters. In this case

since the fault is occurring behind the relay located at terminal B, this relay trips in the

starter region with a delay specified for the starter region T4 and relay at A will trip

with a delay specified for zone 2, T2. The results for this simulation are shown in

Figure 5.20.

(a) Trip A (b) CS A

(c) Trip B (d) CS D

Figure 5.20 Results for fault at x=0.8, zone 2 operates for Relay A
 191

It can be seen from the figures that relay A operates in zone 2 and relay B operates
in the starter zone. Relay A operation takes place with a delay of about 0.5 unit time,
while the relay B operation takes place with a delay of about 1.0 unit time. So for a
fault occurring at 0.2 unit time, the relay is operating at 0.7 unit time. Since relay B is
operating in zone 2, the CS signal is disabled. Similarly, for a fault located behind relay
B, this relay does not trip and also it does not enable the CS signal.

Fault at x=2.2. Zone 3 operation for Relay A.

Result: For the parameters of the trip logic specified above, a simulation for a

fault located in zone 3 for relay located at terminal A is conducted. The delay time of

T3 is 0.8 seconds. Similarly as in zone 2 operation, relay B operates in the starter

region with a delay of T4. The results for this simulation are shown in Figure 5.21.

(a) Trip A (b) CS A

 192

(c) Trip B (d) CS B

Figure 5.21 Results for fault at x=2.2, zone 3 operates for Relay A

It can be seen from the figures above that the relay A operates with a delay

specified for zone 3 and relay B operates for starter region with the specified delay.

Same as in the zone 2 operation, the CS signal is disabled for both the relays. Since

the fault is still occurring behind terminal B, this is not detected by relay B. The zone

3 is set at 250% of the unit line length.

Fault at x=-0.3, Fault time = 0.2 s. Starter region operation for Relay A.

Result: In this case the fault occurs behind relay A. This fault is seen by relay B in

it’s zone 2 and the relay trips according to the delay set for the zone 2 operations.

Relay A operates in its starter region with the starter delay T4. The results of the

simulation are shown in Figure 5.22.

 193

(a) Trip A (b) CS A

(b) Trip B (d) CS B

Figure 5.22 Results for fault at x=-0.3, starter region operation for Relay A

From the figures we see that for a fault specified behind relay A, it will be seen in

the forward direction by relay B and will operate according to the fault location. In

this case the fault occurs in zone 2 of relay B. With respect to relay A the fault occurs

in its starter region and the relay operates accordingly. The starter region for both the

relay is set at 400% of unit line length with a delay of 1.0 second.
 194

Fault at x=0.5. One communication channel is disabled.

Result: In this example and the next one the effect of losing a communication

channel between the two relays is simulated. This abnormality will have effect only

when the communication signal is an active part of the trip signal, such as in case for

zone 1 protection and the overreach zone. The above mentioned abnormality will not

affect the performance of the protection scheme for zone 2, zone 3 and the starter zone

operations.

The zone 1 operation under abnormal condition will cause relay A and relay B to

trip and to enable the CS signal since the fault is located within the primary zone for

both relays. The simulation results are shown in Figure 5.23.

(a) Trip A (b) CS A

 195

(c) Trip B (d) CS B

Figure 5.23 Results for fault at x=0.5, one communication channel disabled

The figures above show that both the relays operate within the primary zone and

both the relays provide the CS signal. This is so since the fault occurred in the

primary protection zone for both relays.

Fault at x=0.1, Fault time = 0.2 s. One communication channel is disabled.

Results: In this case the fault occurs within the primary zone for relay A but

within the overreach zone for relay B. Relay A will trip for zone 1 operation with the

CS enabled however, since the fault is in the overreach region for relay B and the CS

signal is not present due to the missing communication channel, relay B thus operate in

the zone 2. Relay B would have operated for overreach zone had there been a

communication channel. The result of the simulation is shown in Figure 5.24.

 196

(a) Trip A (b) CS A

(c) Trip B (d) CS B

Figure 5.24 Results for fault at x=0.2, one communication channel disabled

The figures above show that relay A trips for zone 1 and the CS A is also enabled.

However, since the CR B is not present, relay B doesn’t operate in the overreach

region and rather operates in the zone 2 region.

There is no effect of the missing communication channel on zone 2, zone 3 and

 197

starter region, since these zone operations are independent of the communication

signals.

BLOV+TB logic

The simulation is based on the following parameters for the relays, where ZMB
stands for measured impedance in backward direction:

Zone 1 (ZM1) 0.6

Zone 2 (ZM2) 1.8

Zone 3 (ZM3) 2.5

ZMB -1.3

Overreach Zone (ZOV) 1.3

Starter Zone (S) [-1 3]

Zone 2 Delay (T2) 0.4

Zone 3 Delay (T3) 0.4

Starter Delay (T4) 0.8

Auxiliary time (tHF) 0.2

The following situations will be simulated (all for relay A, and fault occurrence
time is 1s in all cases):

Fault at 0.6 pu of substation A.

Result: The fault location is 0.6 p.u. from substation A (Figure 5.25), in this
situation, both of the two relays should trip at time tHF . The relay model trips correctly.
 198

Figure 5.25 Plot of relay A and B trip signals (fault location = 0.6)

Fault at 1.2 pu of substation A

Result: The fault location is 1.2 p.u. from substation A, in this situation, since the
fault falls in zone ZMB of relay B, relay A is blocked at time tHF, it should trip at time
t2. This fault is in the backward direction of relay B and falls in the zone of the starter,
thus it should trip at time t4. The simulation results are illustrated in Figure 5.26. The
relay model trips correctly.

Figure 5.26 Plot of relay A and B trip signals (fault location =1.2)
 199

Fault at 1.5 pu of substation A.

Result: The fault location is 1.5 p.u. from substation A, in this situation, relay A
should trip at time t2, while this fault is in the backward direction of relay B and falls in
the starter zone, thus it should trip at time t4. The simulation results are illustrated in
Figure 5.27. The relay model trips correctly.

Figure 5.27 Plot of relay A and B trip signals (fault location = 1.5)

Fault at 1.9 pu of substation A.

Result: The fault location is 1.9 p.u. from substation A, in this situation, relay A
should trip at time t3, while this fault is in the backward direction of relay B and falls in
the starter zone, thus it should trip at time t4. The simulation results are illustrated in
Figure 5.28. The relay model trips correctly.
 200

Figure 5.28 Plot of relay A and B trip signal (fault location = 1.9)

Fault at 2.3 pu of substation A.

Result: Set the fault location is 2.3 p.u. from substation A, in this situation, relay A
should trip at time t3, while this fault is in the backward direction of relay B but falls
outside the zone S, thus it will not trip. The simulation results are illustrated in
Figure 5.29. The relay model trips correctly.

Figure 5.29 Plot of relay A and B trip signals (fault location = 2.3)
 201

Fault at 2.8 pu of substation A.

Result: Set the fault location 2.8 p.u. from substation A. In this situation, relay A
should not trip, while this fault is in the backward direction of relay B and falls in the
zone S, thus it should also trip at time t4. The simulation results are illustrated in
Figure 5.30. The relay model trips correctly.

Figure 5.30 Plot of relay A and B trip signal (fault location = 2.8)

The situation when the fault is outside any zone of both of relay A and B is also
simulated and the models also trip correctly.

Since the two relays are identical, we need not simulate the tripping of forward
fault of relay B and backward fault of relay A. But we should consider the situation
when the communication channel fails.

Fault at 0.6 pu of substation A (Both communication channels have failed).

Result: Set the fault location is 0.6 p.u. from substation A and switch the
communication channels to failure mode. In this situation, though the fault falls inside
the line, since the communication channels fails, both relays will receive signal from
 202

the opposite relay that “say” the fault is outside the line and block it from tripping at
time tHF. Thus both of them will trip at t2. The simulation results are illustrated in
Figure 5.31. The relay models trip correctly.

Figure 5.31 Plot of relay A and B trip signals (fault location = 0.6) with failure of both
communication channels.

Fault at -0.1 pu of substation A (Both communication channels have failed).

Result: the fault location is at –0.1 p.u. from substation A and switch the
communication channels to failure mode. In this situation, though the fault falls inside
ZMB zone of relay A and relay B should be blocked from trip at time tHF, since the
communication channel fails, relay B will still trip at time tHF. The simulation results
are illustrated in Figure 5.32. The relay models trip correctly.
 203

Figure 5.32 Plot of relay A and B trip signal (fault location = -0.1) with failure of both
communication channels.

Fault at 1.1 pu of substation A (Both communication channels fail).

Result: Set the fault location is 1.1 p.u. from substation A and switch the
communication channels to bad mode. in this situation, though the fault falls inside
ZMB zone of relay B and relay A should be blocked from trip at time tHF, since the
communication channel fails, relay A will still trip at time tHF. The simulation results
are illustrated in Figure 5.33. The relay model trips correctly.

Figure 5.33 Plot of relay A and B trip signals (fault location = 1.1) with both
communication channels failure
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BLOV+UZ+TB logic

Fault location is set as 0.1 of the length of the line. The fault time is 0 s.

Result: In this case, the relay trip signals are displayed in Figure 5.34. Relay A
trips immediately when the fault happens, and relay B trips after the overreaching
delay (tHF).

Figure 5.34 Trip signals

Fault location is set as 0.5 of the length of the line. The fault time is 0 s.

Result: In this case, the relay trip signals are displayed in Figure 5.35. Both relay
A and relay B trip immediately when the fault occurs.

Figure 5.35 Trip signals

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The fault location is set as 0.9 of the line from the left side.

Result: In this case, the relay trip signals are displayed in Figure 5.36. Relay B
trips immediately when the fault happens, and relay A trips after the overreaching
delay (tHF).

Figure 5.36 Trip signals

The fault location is set as 1.1 of the line from the left side.

Result: The fault location is set as 1.1, i.e. 110% length of the whole line from the left
side, which is inside the zone 2 and the overreaching range, but beyond the whole line
length. Relay #1 trips for zone 2 and the time delay is t2 (0.2s). Relay #2 trips for starter
after a time delay of t4 (1s). See Figure 5.37.

Figure 5.37 Trip signals

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The fault location is set as 2.1 of the line from the left hand side.

Result: The fault location is set as 2.1, i.e. 210% length of the whole line from the
left side, which is inside the zone 3. Relay A trips for zone 3 and the time delay is t3
(0.4s). Relay B does not trip, because the fault is outside its start range. See
Figure 5.38.

Figure 5.38 Trip signals

Communication channel failure (signal fixed as 0)

1. The fault location is set as 0.1, i.e. 10% length of the line from the left side. The
relays trip as shown in Figure 5.34, which indicates that the communication
channel failure has no effect on this case.
2. The fault location is set as 0.5, i.e. 50% length of the whole line from the left side.
The relays trip the same as shown in Figure 5.35, which indicates that the
communication channel failure has no effect on this case.
3. The fault location is set as 0.9, i.e. 90% length of the whole line from the left side.
The relays trip the same as in Figure 5.36, which indicates that the communication
channel failure has no effect on this case.
 207

4. The fault location is set as 1.1, i.e. 110% length of the whole line from the left side.
Relay A trips for this fault in tHF, which indicates that relay A mal-operates for the
missing of the block signal. The trip signals are shown in Figure 5.39.

Figure 5.39 Trip signals

5. The fault location is set as –0.1, i.e. 10% length of the whole line from the left side
in the reverse direction. Relay A trips for this fault in t4 (starter), and relay B trips
in t Because only the communication channel from Relay B to Relay B is
disconnected, Relay B is blocked for the outside fault correctly. See
6. Figure 5.40.

Figure 5.40 Trip signals

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Communication channel has failed (signal fixed as 1)

The A to B communication channel failure menu is checked for this example.

7. The fault location is set as 0.1, i.e. 10% length of the line from the left side. The
relays trip the same as shown Figure 5.34, which indicates that the communication
channel failure has no effect on this case.

The fault location is set as 0.9, i.e. 90% length of the whole line from the left side. The
relays trip the same as shown
8. Figure 5.40, which indicates that relay A is blocked for the ZOV. Relay A trips for
the zone 2 at last, which is a slow clearing for the fault.
9. The fault location is set as 1.1, i.e. 110% length of the whole line from the left side.
The relays trip correctly. Trip signals are shown Figure 5.41.

Figure 5.41 Trip signals

The fault location is set as -0.1, i.e. -10% length of the whole line from the left side.
The relay trips correctly. The trip signals are shown in Figure 5.41.
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BLUN logic

Fault at 0.5 pu. Fault time 0.1 s. Communication channel is good.

Result: After running the model, we have the following graphs:

Figure 5.42 Trip and block signal

From Figure 5.42, we can see relay A and relay B sent trip signal immediately
after the fault occurs (0+tfault=0.1s ). This is because the fault is located in the Zone 1
of both relay A and relay B. And no block signals are sent.
 210

Fault at 0.5 pu. Fault time 0.1 s. Communication channel has failed.

Result: After running the simulation model, we have the results shown in
Figure 5.43.

Trip Signals:

Block Signals:

Figure 5.43 Tripp and block signals

From Figure 5.43, we can see that relay A and relay B trip signals are the same as
the Example above. Because the fault is located outside the zones ZMB of both relay A
and relay B, no block signals are sent.
 211

Fault at 0.9 pu. Fault time 0.1 s. Communication channel is good.

Result: After simulation we have the following results:

Figure 5.44 Trip and block signals (Example 3)

From Figure 5.44, we can see Relay A sent trip signal in 0.1s+tHF time
(0.1+tHF=0.3s), while relay B sent trip signal in zero time (0.1s). This because the fault
located in the Zone 2 of relay A, and in the Zone 1 of relay B, so no block signal is
sent.
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Fault at 1.2 pu. Fault time 0.1 s. Communication channel is good.

Result: After simulation we have the following results:

Figure 5.45 Trip and block signals (Example 4)

From Figure 5.45, we can see that Relay A tripped in t2 seconds after fault
happened (0.1+t2=0.6s), while relay B tripped at 0.1s+t4 (=1.1s). The fault is located
in the zone 2 of relay A, and it is behind relay B, then it sent block signal to relay A
from the fault time (0.1s). Relay A can only trip at 0.1+t2 =0.6s. Relay B tripped at
0.1+t4 time, because the starter is the back-up protection.
 213

Fault at 1.2 pu. Fault time 0.1 s. Communication channel has failed (B to A).

Result: After simulation, we have the following results:

Figure 5.46 The trip and block signals (Example 5)

From Figure 5.46, Relay B tripped at 0.1s+t4 (=1.1s). There is no difference with
the result of Example 3. Relay A tripped at 0.1s+tHF (=0.3s), because it did not receive
the block signal from Relay B. So relay A tripped before the expected time.
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Fault at 2.0 pu. Fault time 0.5 s. Communication channel is good.

Result: After simulation we have the following results:

Figure 5.47 Trip and block signals (Example 6)

From Figure 5.47, we can see Relay A tripped at 0.5s+t3 (=1.3s), relay B tripped at
0.5s+t4 (=1.5s). The protection of Zone 3 in relay A sent trip signal, and starter in relay
B sent a trip signal.
 215

Fault at 3.5 pu. Fault time 0.5 s. Communication channel is good.

Results: After simulation, we have the following results:

Figure 5.48 Trip signals and block signals (Example 7)

From Figure 5.48, because the fault is located outside the zones of main and
back-up protection, we can see that no relay tripped.
 216

Fault at -0.5 pu. Fault time 0.5 s. Communication channel is good.

Result: After running the simulation we have the following result.

Figure 5.49 Trip and block signals (Example 8)

From Figure 5.49, we can see that Relay A tripped at 0.5s+t4 (=1.5s), because the
starter sent a trip signal. Relay B tripped at 0.5s+t2 (=1.0s), because it received a
block signal from Relay A before the time 0.5s+tHF time, and it tripped by the zone 2
protection.
 217

Fault at -0.5 pu. Fault time 0.5 s. Communication channel has failed (A to B).

Results: After simulation, we have the following results:

Figure 5.50 Trip and block signals (Example 9)

From Figure 5.50, Relay A tripped at 0.5s+t4 time. There is no difference with the
result of Example 5 above. Relay B tripped at 0.5s+tHF (=0.7s), because it did not
receive the block signal from Relay A. So relay B is mal-operated before the expected
time.
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POTT+WEI+TB logic

The parameters for the relay in this example are:

Undervoltage relay zones: [2 -1]

Zone 1 (ZM1) 1.4

Zone 2 (ZM2) 1.7

Zone 3 (ZM3) 2.7

ZMB -1.5

Starter Zone (S) [-1 3]

Zone 2 Delay (T2) 0.5

Zone 3 Delay (T3) 1.0

Starter Delay (T4) 1.5

Fault at 0.5 pu. Fault time 2 s. Communication channel is good.

This is an internal fault of line, so ZOV, ZM2, ZM3, U< and S of A and B Relay all
pick up and ZOV should trip instantaneously after the fault. Consider the action time of
relay, relays should trip at 2.2s. S+U< also pick up, but the pick-up of ZOV blocks it.
Observe the performance of the simulation, which provides the same result.
 219

Figure 5.51 The trip time of the relays in Exercise 1

Fault at 1.2 pu. Fault time 2 s. Communication channel is good.

The fault is an external fault, forward to A, backward to B. It should be removed

by other relays instantaneously. If not, relays A, B may trip as remote back-up. In this
study, ZOV of A with overreaching setting picks up and sends the CS to B, but ZOV of B
does not pick up and there is no CR signal received by A, therefore after the time delay
(0.5s) ZM2 of A will trip. To B, S+U< is blocked by ZMB and S picks up, then trips after
1.5 s. Figure 5.52 shows the result as follows.
 220

Figure 5.52 The trip time of the relays in Exercise 2

Fault at 1.5 pu. Fault time 2 s. Communication channel is good.

Out of ZOV of A, the fault lies within zone 2 of relay A and S zone of relay B
(reverse side). Without the CR signal, S+U< of relay A can not trip, while S+U< of
relay B is blocked by ZMB. They will trip separately at 2.7s, 3.7s. (Figure 5.53)

Figure 5.53 The trip time of the relays in Exercise 3

 221

Fault at 2.2 pu. Fault time 2 s. Communication channel is good.

The fault lies in ZM3 of relay A, which will trip after t3 (1.0s). None of zones of
relay B will pick up, so relay B will not trip at all. (Figure 5.54)

Figure 5.54 The trip time of the relays in Exercise 4

Fault at 2.8 pu. Fault time 2 s. Communication channel is good.

The fault lies in S zone of relay A (direct side), which will trip after t4 (1.5s). Relay
B will not trip due to the same reason as discussed in the last example (

Figure 5.55)
 222

Figure 5.55 The trip time of the relays in Exercise 5

Fault at 3.5 pu. Fault time 2 s. Communication channel is good.

This fault site is beyond any relay protection zone of relays A and B. So relays A
and B will not trip at any time. (Figure 5.56)

Figure 5.56 The trip time of the relays in Exercise 6

 223

Fault at -0.5 pu. Fault time 2 s. Communication channel is good.

The fault is on the reverse side of Relay A. Because blocked by ZMB and no CR
signal, its S+U< cannot trip. The fault will be handled by S of relay A, and the time
delay is t4 (1.5s). S+U< of relay A is blocked by ZMB, though it can pick up. ZM2 of
relay B picks up at 2s and trips at 2.7s.

Figure 5.57 The trip time of the relays in Exercise 7

Fault at 0.8 pu. Fault time 2 s. Communication channel has failed

In this case, the communication channel connecting relays A and B fails. When an
internal fault happens, ZOV of relays A and B can pick up and send the CS signals, but
not trip because the CR signals are zero. Under this kind of situation, S+U< is unable
to trip too, as ZOV has picked up and there is no enable CR signals. Thus, the trip will
only take place in the second zone. (Figure 5.58)
 224

Figure 5.58 The trip time of the relays in Exercise 8

Fault at 0.8 pu. Fault time 2 s. Communication channel has failed

An external fault happens, and ZOV of relay A picks up and send CS signal to relay
B. S+U< of relay B also operates, but cannot trip as the communication channel
connecting relays A and B has a failure and the block effect of ZMB. Owing to failure of
communication channel, relay A receives an enable CR signal, it will trip
instantaneously. Relay B will trip after t4 time delay. (Figure 5.59)

Figure 5.59 The trip time of the relays in Exercise 9

 225

Fault at –0.5 pu. Fault time 2 s. Communication channel has failed

A reverse external fault occurs and the communication channel fails. S+U< is
blocked by ZMB, even though it receives a wrong CS (1) signal. It will trip at 3.7s due
to the effect of starter. But the S+U< of relay B operates and receives a wrong CS (1)
signal owing to the communication channel’s failure. So it will trip instantaneously
(only after 0.2s - relay operating time).

Figure 5.60 The trip time of the relays in Exercise 10

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6. DESIGNING AND IMPLEMENTATION OF OVERCURENT, DISTANCE

DIFFERENTIAL, AND PILOTPROTECTION SYSTEM

6.1 Line Protection System: Overcurrent Relaying

6.1.1 Software Modules

The module “Systemtotal.mdl” provides an overcurrent relay simulation and test

system. A block diagram of the implemented system is depicted in Figure 6.1

Figure 6.1 Block diagram of the implemented Power System

The system consists of a radial line, it has at one end a three-phase voltage source
and in at the other end a three-phase load. The system has a breaker unit to connect or
disconnect the source. All the power elements are marked in yellow. In addition, the
system has CTs and VTs at both the sending and the receiving end. These elements are
marked in blue. The signal processing block and the protective relays block are marked
 227

in green and dark green respectively. The block for faults is marked in red color and all
the scopes are marked in white color. A more detailed description of each block is
presented in corresponding section of the accompanying book

6.1.2 Sample Examples

In this section, some results from simulation in normal and fault conditions will be
presented, as well as the settings required for each block.

The following blocks: DAB, UC, OC, and DE, requires a parameter called
sampling frequency (Hz), it should be the same for all the blocks aforementioned, in
this case set it to 40*60. The settings for the Relays are defined in Figure 6.2

Figure 6.2 Settings for each protective relay

Normal operation

This condition means that no faults will be simulated. Therefore, when the system
is working under normal operation a relay trip is not expected. Some waveforms for
 228

this condition are shown in Figure 6.3. Normal operation is chosen by selecting
Normal in the dialog menu of Faults subsystem.

The results are shown in Figure 6.3. In the scope (measurement element) labeled
TRIP there is a change from low to high at the beginning of the simulation. This false
trip is caused by the directional relay; it is because the connection of the Power Source
to the Load at the beginning of the simulation causes a transient (cold-load). After this,
the system works normally and there is no trip caused by faults. This simulation is only
to demonstrate that the system can work under normal conditions and the relays are
working properly.
 229

Figure 6.3 Results for normal operation.

Single-phase to ground fault

A fault involving phase a and ground is selected in the subsystem faults. The
location of the fault is set at 50%, and the rest of the settings is still the same. In
Figure 6.4 there are some waveforms showing the behavior of each relay. Note that trip
signals for each relay are included.
 230

Figure 6.4 Some results for single-phase-to ground fault.

The fault time is set at 0.05 sec. The directional relay makes a trip (Trip abc-DIR)
at 0.06 sec. (0.01 sec. after the fault), while the time overcurrent relay issues a trip
(Trip abc-IT) at 0.1 sec. approximately (0.05 sec. after the fault). This time is very
close to the time expected from a very Inverse function (as shown in Figure 6.3) which
is given as:

13.5 * k
top =
I n −1

Where: top: operation time

k: time parameter

In: normalized input signal. In = magnitude of input current / pickup value

Using k= 0.05, magnitude of fault current = 20 Amp. Pickup value=1.2 Amp. It

 231

gives a top=0.043 sec. approx. which is close to 0.05 sec.

For the residual relay, the trip (Trip abc-RES) appears at 0.22 sec. (0.17 sec. after
the fault). In this case the top for a RI Inverse characteristic is defined as follows.

 2.2 
t op = 3.1 * k 1 + 2.2 
 In 

Using: k=0.05, magnitude of zero sequence current=20/3 Amp. Pickup value=1.2

Amp. It gives a top=0.1628 sec. approx. which is close to 0.17 sec.

Phase-to-phase fault

A fault involving phases b and c is selected in this case while the rest of settings
still the same.
 232

Figure 6.5 Results for phase-phase fault.

The primary protection gives a very fast trip as can be seen in trip abc-DIR
waveform in Figure 6.5. While the time overcurrent relay's trip appears at 0.09 sec.
(0.04 sec. after the fault), in this case the operating time is obtained using
In=28/1.2=23.33

13 .5 * 0.05
t op = = 0 .03 sec .
23 .33 − 1

The residual relay is not giving any trip as expected for a phase-to-phase fault.

Phase-to-phase-to-ground fault

A fault involving two phases and ground (b-c-g) is selected in this case. Results
are shown in the next figure.
 233

Figure 6.6 Results for phase-phase-to ground fault.

 234

Once again, the directional relay has a very fast response as can be seen in the
above figure (Trip abc-DIR). The backup protection is operating in a time similar to
the preceding case. The Residual protection is giving a trip at 0.24 sec. (0.19 sec. after
the fault), the top is obtained using In= 5.1/1.2= 4.25

 
 2 .2 
t op = 3.1 * 0.051 +  = 0.1701
 4.25 2.2 
 

Three-phase fault

A three-phase fault (a-b-c) is simulated and its results are shown in Figure 6.7.
 235

Figure 6.7 Results for three-phase fault.

As in the preceding cases, the directional relay is acting very fast, right after the
fault. The time overcurrent relay is acting at 0.079 sec (0.029 sec. after the fault) with a
theoretic time of:

13 .5 * 0.05 In=30/1.2
t op = = 0.028 sec .
25 − 1

The residual protection does not give a trip as expected.

6.2 Line protection system: differential relaying

6.2.1 Software modules

The module “testsystem2.mdl” provides differential relay model and test system.
Figure 6.8 shows a diagram of the test model for differential line protection system.
 236

Figure 6.8 Protection system model in MATLAB

The system contains the following subsystems: power supply, transmission line
and voltage/current measurement. The detailed description for each block is presented
in corresponding section of the accompanying book.

6.2.2 Examples

Several conditions including internal and external faults are simulated in the
following examples. The failure of the primary protection is also simulated. In this case,
the backup protection should operate.

Internal fault

Consider the situation of internal fault ag and ab.

For internal ag fault, the output waveform is shown in Figure 6.9.

 237

Figure 6.9 Internal AG fault trip signal

Consider the situation when the differential fails to operate. Protection scheme is
available in module “difflinrelay.mdl” as in Figure 6.10.

Figure 6.10 Protection Scheme of Differential Relay

The trip signal waveform is shown as Figure 6.11. It can be seen that although no
time delay was applied to zone 1, there is still some time delay for distance relay
compared with differential protection.
 238

Figure 6.11 Internal ag fault trip signal with primary protection out of service

For internal ab fault, the trip signal with primary protection or without primary
protection is the same as internal ag fault.

External fault

Consider the situation shown in external fault ag. For external ag fault, the trip
signal waveform is shown in Figure 6.12.

Figure 6.12 External ag Fault Trip Signal

 239

In this case, the protection system trips at 0.0052s, definitely this is not the signal
issued by differential relay for this type of relay will operate at less than 0.001s. Since
we have found that for zone 1 fault distance relay operates at 0.0042s and the delay for
zone 2 is 0.001s. It can be concluded that the fault falls in the second zone of distance
relay and now the system works in back-up mode.

If the primary protection is out of service, the trip signal will not change for any
external fault. The trip signal is issued by the distance relay.

For an external ab fault the results are the same.

6.3 Line protection system: zone protection

6.3.1 Software modules

Module “lineprotsys.mdl” provides a transmission line protection system for

two-terminal lines. Figure 6.13 shows a diagram of the simulation models. This
protection system is composed by three main elements: measurements, relay logic and
trip logic. Detailed descriptions for each block are presented in corresponding sections
of the accompanying book.
 240

Figure 6.13 Protection System Overall Structure

6.3.2 Examples

In this section, the configuration and setting for the zone protection are presented.
Then, examples for testing the protection using several scenarios are provided.

Relay Settings

The relay protection system is a mask block. Double click the relay block and the
setting menu will pop up. There are several settings of the relay.

Five zone elements:

The five-zone element has the following appearance (Figure 6.14):

 241

Figure 6.14 Five-zone elements of distance relay

Every zone is a square, so it is only needed to set the width of the zones. The
respective settings are:

Zone I: z1

Zone II: z2

Zone III: z3

Zone IV: z4

Backward zone: zb

Fault detection:

This block will be used in the memory polarization block, because the pre-fault
voltage should be memorized when a fault happens. As the memory polarization is
mainly applied on the faults near the relay, a one-zone element is used. And this zone
should include the zero point. Only the width (f) is needed as a parameter as shown in
Figure 6.15.
 242

Figure 6.15 Fault detection

Memory polarization

The magnitude and the angle of the setting impedance have to be specified as
shown in Figure 6. 16.

Figure 6.16 Required parameters for setting a zone

 243

Power swing:

The width and length of the two rectangles are described with the coordinates
shown in the Figure 6.17.

Figure 6.17 Power swing blocking elements

Direction inverse time overcurrent:

For the directional element, the minimum (angle1) and the maximum angle
(angle2) of the trip zone have to be set. For the inverse time overcurrent, the pickup
value and the time parameter can be set.

Test Examples

Some tests for different faults to see the performance of the protection system are
shown in this section. To generate the test signals a simple system with a generator, a
transmission line and a load was developed. The location and type of fault varies in
each test. The module “internalfault.mdl” is provided for simulations.
 244

Test model

a. Test model for internal faults

With the model shown in the Figure 6.18 the different types of faults to the line
can be simulated. The fault time, type of fault and the location of the fault along the
line have to be specified.

Figure 6.18 Line protection system for internal fault

b. Test model for backward faults

This model is intended to simulate a fault that occurs in the system in the
backward direction of the relay. For this case, the protection system should not trip.
 245

Figure 6.19 Line protection systems for backward fault

Test Example

A three-phase fault is located at the end of the line and fault time is 0.5 second
using the model shown in Figure 6.18. The results of the simulation are written to a
group of files. The protection system was run with these signals and the results are
shown below.

The relay has the following settings as shown in Figure 6.20:

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Figure 6.20 Settings of the relay

Some output signals are shown in Figure 6.21-6.23.

Figure 6.21 Magnitude and angle of the measured impedance

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Figure 6.22 The trip signal issued by zone1 and zone2

Figure 6.23. Directional and CS signals issued by the memory polarization block and
backward zone respectively

From the Figure 6.24, we can see that the zone II trips, but zone I does not trip.
This is because the fault is located outside the zone I but inside the zone II. And the CS
signal is zero, because it is an internal fault.

Test Example

A fault is applied to the line in the model of Figure 6.18. This time the fault occurs
in the middle of the line.
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For this test we have the following results as shown in Figure 6.24.

Figure 6.24. The trip signal of zone I and zone II

Because the fault is located in the first zone, zone I tripped, and after 0.2s (the
delay time of zone II), the zone II tripped.

Test Example

A fault is applied on the line to the model shown in Figure 6.18. The fault is
located very near to the location of the relay. The test results are as shown in Figure
6.25-6.26.

Figure 6.25. Impedance and the directional signal

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Figure 6.26. Memory voltage and fault voltage used in memory polarization.

From the previous graphs, we can see that after fault happened (0.5s), the
measured impedance dropped to zero. At this time, the relay should trip. But the relay
may not response to a "zero" signal. So the memory elements must detect this
phenomenon and sent the corresponding trip signal. This test demonstrates that the
memory polarization works well.

Test Example

A fault is applied to backward zone of the relay using the model shown in
Figure 6.19. The results obtained for this test are shown in Figure 6.27.
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Figure 6.27. CS signal for test four.

Because this is a backward fault, the CS signal will block the relay in the other
terminal.

6.4 Line Protection System: Pilot Protection

6.4.1 Software Modules

The module for the distance relay scheme which can be used to form the pilot
protection scheme is available in “distrelay.mdl”, as shown in Figure 6.28. The
modules for testing in phasor and transient ways are also provided. The phasor testing
allows test the relay design itself. The transient testing allows test and check behavior
of the protection system which consists of the modeled relays.
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Figure 6.28. Distance Relay Scheme

6.4.2 Test Examples

Phasor Testing

In this case, we can check the operating characteristics of the relay. We may also
measure operating time. The scheme for the phasor testing is shown below (Error!
Reference source not found.Figure 6.29).
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Figure 6.29 Phasor testing circuit

This scheme consists only of the relay and the input voltage and current phasors
sources. To determine the shape of the operating characteristic we may do as follows:

2 and 3-phase fault operating characteristic:

1. Set the symmetrical current magnitudes to 5A in all three phases

2. Set the symmetrical voltage magnitudes to 90V in all three phases
3. Adjust the phase between the voltages and currents with a step increment (10
degrees for example)
4. Decrease slowly, with a small step, all voltages until any tested zone or phase
element operates. Run simulation each time voltage is changed. The module of the
operating impedance should be calculated as the voltage divided by the current.
The argument of the operating impedance is the phase shift between the voltage
and current.
5. Increase voltage back to about 90V, shift phase by some other angle, and go back to
step 3.
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Figure 6.30 Phasor testing circuit - replaying waveform from files

A-phase to ground fault operating characteristic:

1. Set the phase A current to 5A

2. Set the symmetrical voltage magnitudes at 90V in all three phases,
3. Adjust the phase between the voltages and currents with a step increment (10
degrees for example),
4. Decrease slowly (with small step) all voltages until any tested zone or phase
element operates. Run simulation each time voltage is changed. The module of the
operating impedance should be calculated as the voltage divided by current times
(1+ko). The argument of the operating impedance is the phase shift between the
voltage and current.
5. Increase voltage back to about 90V, shift phase by some angle, and go back to step
3.

It can be noted after performing the tests that the measured operating
characteristics of the designed relay matches perfectly with theoretical set up
characteristics
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Transient Testing

To make possible performing transient simulation, a model with a two-terminal

500kV transmission line was prepared. All measurements from both ends of the line,
including currents and voltages, are taken out from the line and injected into the relays
at each end of the line. The relays are connected using a communication channel. Also,
the relays are connected to Circuit Breakers, so they can trip them. PUTT logic was
selected (Error! Reference source not found.33).

Figure 6.31 Transient testing - Two terminal 500kV Line Protection system
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Transmission line model:

The line model used in the simulation consists of two

distributed-parameters-model sections. The total length of the line is 200km, which
corresponds to an impedance of 120 Ohms. Between the sections, a simulated fault is
located (in this case it is at 0.1p.u.=20km from substation A). The A-B fault occurs at
t=34 msec. The fault impedance per phase is 1Ohm. Every parameter of the line as
well as the fault can be easy adjusted by the user (Error! Reference source not
found.34).

Figure 6.32 Transmission line model and settings

Communication channel model:

This element provides communication between the relays at both ends of the line. The
user can enter the following parameters:
• Communication channel delay time [ms]
• Operating mode: normal/failure
• Logic value of erroneous signal (0 or 1) in a failure mode
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a)

b)

Figure 6.33 Communication channel: a) Block diagram; b) Block mask

Offline testing model

Another model to test the behavior of the protection system is shown in the
following figures (Error! Reference source not found.36 and Error! Reference
source not found.37). The model given in Error! Reference source not found.36
generates the fault signals that will be used later in the model given in Error!
Reference source not found.37 to test the relay system.
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Figure 6.34 Model of the line to generate fault signals

Figure 6.35 Offline testing of the protection system

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7. DESIGNING AND IMPLEMENTATION OF TRANSFORMER, AND BASBAR

PROTECTION SYSTEM

7.1 Transformer Protection Systems

7.1.1 Software Modules

The module “Diffrelay.mdl” provides a simulation model for transformer

protection system. The overall design diagram of the relay system is shown as
Figure 7.1. It consists of three major elements: measurement, signal processing and
differential relay logic. Detailed descriptions for each block are provided in the
accompanying book.

Figure 7.1 Design Diagram of Transformer Protection System

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The module “transystem1.mdl” provides testing models for transformer relaying.

Figure 7.2 shows a diagram of the simulation models.

Figure 7.2 Transformer relaying test system

7.1.2 Examples

Testing Model

A two-terminal source system, as shown in Figure 7.2, was used to test the
performance of the designed protection system. The current and voltage signals were
saved to a group of .mat files. The voltage and current measurement blocks are shown
in figures Figure 7.3 and Figure 7.4. Note that the CT setting values can be set to
simulate a mismatch in the CTs turns ratio.

The transformer structure is shown in Figure 7.5. It has a wye-delta-11 connection.

Note that the neutral current is being measured. Its corresponding dialog menu is
shown in Figure 7.6. The different internal and external faults are simulated with the
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fault element. The dialog menu for this element is shown in Figure 7.7. To simulate an
external fault the fault element needs to be relocated outside the transformer.

Figure 7.3 Current Measurement

Figure 7.4 Voltage Measurement

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Figure 7.5 Transformer connection (wye-delta-11)

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Figure 7.6 Transformer dialog menu

Figure 7.7 Fault dialog menu

The output files from the test system mentioned above were input to the relay
system. For convenience, the four relays in our design were tested separately. Of
course, it could also be done in the combined model, but it is more time-consuming.
For all the tests the fault time was 0.5 seconds. The models used to test the four relays
are shown in Figure 7.8 - Figure 7.11.
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Figure 7.8 Differential Relay

Figure 7.9 Restricted earth protection relay

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Figure 7.10 Inverse-time overcurrent relay

Figure 7.11 Six-element impedance relay

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The different tests performed on the protection system are shown below. The
graphics of the trip signals are presented. In this case ‘0’ means no trip, while ‘1’
means that the relay sent a trip signal.

Test 1. Normal operation

Differential relay trip signal is shown in Figure 7.12.

Figure 7.12. Differential relay trip signals

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Test 2. Single phase ground fault in the low voltage side terminal.

Differential relay trip signal is shown in Figure 7.13.

Figure 7.13 Differential relay trip signal

Test 3. Single phase to ground fault in the high voltage side terminal.

Differential relay trip signal response is shown in Figure 7.14:

Figure 7.14 Differential relay trip signal

Restricted earth Protection with zero sequence differential trip signal is shown in
Figure 7.15.
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Figure 7.15 Restricted earth Protection with zero sequence differential trip signal

Restricted earth protection with inverse-time overcurrent relay response time is

shown in Figure 7.16.

Figure 7.16 Restricted earth protection with inverse-time overcurrent relay trip signal

Six-element impedance relay trip signal is shown in Figure 7.17.

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Figure 7.17 Six-element impedance relay trip signal

Test 4. AB phase to phase fault on low voltage side terminal.

Differential relay trip signal is shown in Figure 7.18.

Figure 7.18 Differential relay trip signal

Restricted earth protection with inverse-time overcurrent relay trip signal is shown
in Figure 7.19.
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Figure 7.19 Restricted earth protection with inverse-time overcurrent relay trip signal

Test 5. AB phase to phase fault on high voltage side terminal.

Figure 7.20 Differential relay trip signal

Figure 7.21 Restricted Earth Protection with Zero sequence differential trip signal
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Figure 7.22 Inverse-time Overcurrent Relay Restricted Earth Protection trip signal

Test 6. Single phase to ground external fault at the low voltage side.

Figure 7.23 Differential relay trip signal

Test 7. AB phase to phase external fault at the low voltage side.

Figure 7.24 Differential relay trip signal

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Test 8. Single phase to ground external fault at the high voltage side.

Figure 7.25 Differential relay trip signal

Figure 7.26 Restricted Earth Protection with Zero sequence differential trip signal

Figure 7.27 Six-element impedance Relay trip signal

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Test 9. AB phase to phase external fault at the high voltage side.

Figure 7.28 Differential relay trip signal

7.2 Busbar Protection Systems

7.2.1 Software Modules

The module “Busrelay.mdl” provides a simulation model for bus differential

protection system. The whole protection system is shown in Figure 7.2929. It consists
of two major blocks: Data acquisition system and bus protection logic. The detailed
descriptions for each block are presented in the accompanying book.
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Figure 7.29 Bus Differential Protection System

7.2.2 Sample Examples

The module “Bustestsysa.mdl” provides testing models for bus protection system.
Figure 7.300 shows a diagram of the test model.

Test system

In order to test the designed relay, a testing system with four ideal voltage sources
was built. Two of them have small transmission line impedance, and the other two
have relatively higher line impedances, which represent two local power sources and
two remote power sources respectively.

The fault can be put on or outside the busbar, by selecting the appropriate times for
the two fault time settings in the external fault block and the internal fault block.
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Figure 7.30 Bus protection test System.

The simulation results are saved into a MAT file, which will be used later to test
the relay. The current transformer is modeled as a saturable transformer. The saturation
characteristic can be adjusted by selecting the nominal power and the CT load
parameters.

Internal Fault Test

Set the fault time of ‘Internal Fault’ block as 0.02s, the fault time of ‘External
Fault’ block as 0.3s (greater than the simulation time length). Perform the simulation.

After replaying that MAT file on the designed relay, the relay tripped as shown in
Figure 7.3331.
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Figure 7.31 Three-phase Current Transformer

Figure 7.32 Fault currents flow through the CT #1

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Figure 7.33 Trip signal

External Fault Test

Setting the fault time of ‘External Fault’ block as 0.02s, the fault time of ‘Internal
Fault’ block as 0.3s (greater than the simulation time length). Perform the simulation.

Figure 7.34 Fault currents flow through the CT #4

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Figure 7.35 Trip and Pickup signals

After replaying that MAT file on the designed relay, the relay performed as shown
in Figure 7.3535. Although the relay picked up after the fault happened, it did not
miss-operate due to the restraint of the bias-characteristic.

7.3 Summary

This chapter presents different communication schemes and trip logics used in
distance relaying. The different protection systems for busbars (differential) and
transformers (differential) are provided with available software modules. After those
sections, the reader will have a deep understanding of the protection knowledge.
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8. TESTING OF DIGITAL PROTECTIVE RELAYS

8.1 Closed-loop Relay Testing

This chapter describes the following activities:

• Perform closed-loop and open-loop protective relay tests with various power
system disturbance including fault types, locations and resistance.

• Determine appropriate protection scheme for a given power system and

configure relays with correct settings.

• Verify various protection functions including back-up protection scheme.

• Analyze test results and characterize relay operation performance.

Two software modules, “OORT.mdl” and “OIRT.mdl”, are provided for overcurrent
and impedance relay testing. To use the model, firstly run MATLAB (R2015 or later
version). Then direct the Current Directory to where this file is stored or copy the file in
to MATLAB’s default working directory (typically MATLAB\R2015\work) and type
“OORT.mdl” or “OIRT.mdl”. The main menu will display in Figure 8.1 and Figure 8.2.
Double clicking on “On-Line Testing” icon opens the model shown in Figure 8.3 and
Figure 8.4.

Figure 8.1 Main menu of overcurrent relay test model

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Figure 8.2 Main menu of impedance relay test model

Figure 8.3 Closed-loop overcurrent relay test model

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Figure 8.4 Closed-loop impedance relay test model

8.2 Lab Exercises

After completing the lab exercises students will learn how to protect transmission
line using overcurrent relay and impedance relay. Particularly the following concepts are
reinforced: load flow and short-circuit calculations, selecting the protective equipment,
setting and coordinating relays, relay sensitivity check, analysis of the network operation
under variety of conditions including faults and equipment mal-operations.

Overcurrent Relay

The closed-loop overcurrent relay model shown in Figure 8.3 is used for the
following exercises.

Exercise 1: Instantaneous Operation

Place a single phase-to-ground fault (a-g) starting at 0.02 s in the middle of Line 3.
Observe protection relays’ operations and explain their behavior. What is the fault
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clearing time?

Figure 8.5 shows the trip signal sent by relay OR-3. It operates 3 msec after the fault
occurs. Figure 8.6 shows the fault current measured at CT-3. The fault is cleared after
additional 21 msec. Relays OR-1 and OR-2 do not operate because they are configured
as back-up protection for Line 3.

The protection system operates correctly:

• Relay OR-3 operates instantaneously after fault occurs;
• Relays OR-1 and OR-2 do not operate;
• Fault is isolated by CB-3 in 21 msec (CB is configured with 20 msec operating
time);
• Phase selection function detects that the fault type is a-g.

Figure 8.5 Relay OR-3 trip signal

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Figure 8.6 Fault current at CT-3 (secondary A)

Exercise 2: Definite Time Delay Operation I

Place a phase-to-phase fault (b-c) starting at 0.02 s on the 0.3 of Line 2. Observe
protection relays’ operations and explain their behavior. What is the fault clearing time?

Figure 8.7 shows the trip signal sent by relay OR-2. It operates 0.603s after the fault
occurs. Figure 8.8 shows the fault current measured at CT-2. The fault is cleared after
additional 22 msec. Relay OR-1 does not operate because it is configured as back-up
protection for Line 2. Relay OR-3 does not operate because it does not measure any fault
current.

The protection system operates correctly:

• Relay OR-2 operates after definite time delay 0.6 s;
• Relays OR-1 and OR-3 do not operate;
• Fault is isolated by CB-2 in additional 22 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is b-c.
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Figure 8.7 Relay OR-2 trip signal

Figure 8.8 Fault current at CT-2 (secondary A)

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Exercise 3: Definite Time Delay Operation

Place a two phase-to-ground fault (c-a-g) starting at 0.02 s in the middle of line 2.
Observe protection relays’ operations and explain their behavior. What is the fault
clearing time?

Figure 8.9 shows the trip signal sent by relay OR-1. It operates 1.25 s after the fault
occurs. Figure 8.10 shows the fault current measured at CT-1. The fault is cleared after
additional 21 msec. Relays OR-2 and OR-3 do not operate because they do not measure
any fault current.

The protection system operates correctly:

• Relay OR-1 operates after definite time delay 1 s;
• Relays OR-2 and OR-3 do not operate;
• Fault is isolated by CB-1 in additional 21 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is a-a-g.

Figure 8.9 Relay OR-1 trip signal

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Figure 8.10 Fault current at CT-1 (secondary A)

Exercise 4: Back-up Protection

Place a three phase fault (a-b-c) starting at 0.02 s at the end of Line 3. Disconnect
output terminal “Trip” of relay OR-3 from input terminal “Trip” of CB-3. Observe
protection relays’ operations and explain their behavior. What is the fault clearing time?

Relay OR-3 operates but fails to isolate the fault due to the CB-3 being disconnected.
Figure 8.11 shows the trip signal sent by relay OR-2. It operates 0.623 s after the fault
occurs. Figure 8.12 shows the fault current measured at CT-2. The fault is cleared after
additional 25 msec. Relay OR-1 does not operate because the fault is cleared
successfully by relay OR-2.

The protection system operates correctly:

• Relay OR-3 operates instantaneously after fault occurs but CB-3 fails to trip the
faulted element;
• Relay OR-2 operates as back-up protection for Line 3 after time delay 0.6 s;
• Relay OR-1 does not operate;
• Fault is isolated by CB-2 in additional 25 msec (CB is configured with 20 msec
operating time);
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• Phase selection function detects that the fault type is a-b-c.

Figure 8.11 Relay OR-2 trip signal

Figure 8.12 Fault current at CT-2 (secondary A)

Impedance Relay

The closed-loop impedance relay model shown in Figure 8.4 is used for the
following exercises.
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Exercise 1: Zone I Operation

Place a single phase-to-ground fault (a-g) starting at 0.02 s in the middle of the Line
1. Observe protection relays’ operations and explain their behavior. What is the fault
clearing time?

Figure 8.13 shows the trip signal sent by relay ZR-1. It operates 21 msec after the
fault occurs. Figure 8.14 shows the fault current measured at CT-1. The fault is cleared
after additional 20 msec. Relays ZR-2 and ZR-3 do not operate because the fault occurs
in reverse direction.

The protection system operates correctly:

• Zone 1 of relay ZR-1 operates instantaneously after fault occurs;
• Relays ZR-2 and ZR-3 do not operate;
• Fault is isolated by CB-1 in additional 20 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is a-g.

Figure 8.13 Relay ZR-1 trip signal

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Figure 8.14 Fault current at CT-1 (secondary A)

Exercise 2: Zone II Operation

Place a phase-to-phase fault (b-c) starting at 0.02 s at the end of Line 1. Observe
protection relays’ operations and explain their behavior. What is the fault clearing time?

Figure 8.15 shows the trip signal sent by relay ZR-1. It operates 0.37 s after the fault
occurs. Figure 8.16 shows the fault current measured at CT-1. The fault is cleared after
additional 30 msec. Relays ZR-2 and ZR-3 do not operate because the fault occurs in
reverse direction.

The protection system operates correctly:

• Zone 1 of relay ZR-1 fails to operate since the fault occurs out of the range;
• Zone 2 of relay ZR-1 operates after preset time delay;
• Relays ZR-2 and ZR-3 do not operate;
• Fault is isolated by CB-1 in additional 30 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is b-c.
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Figure 8.15 Relay ZR-1 trip signal

Figure 8.16 Fault current at CT-1 (secondary A)

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Exercise 3: Zone III Operation

Place a two-phase-to-ground fault (c-a-g) starting at 0.02 s at the end of Line 1.

Disconnect the input trip signal from relay ZR-1 to CB-1. Observe protection relays’
operations and explain their behavior. What is the fault clearing time?

Figure 8.17 shows the trip signal sent by relay ZR-2. It operates 1.03 s after the fault
occurs. Figure 8.18 shows the fault current measured at CT-2. The fault is cleared after
additional 30 msec. Relay ZR-1 operates but cannot trip the CB-1. And relay ZR-3 does
not operate because the fault occurs in reverse direction.

The protection system operates correctly:

• Zone 2 of relay ZR-1 operates but it does not trip CB-1;
• Zone 3 of relay ZR-2 operates as back-up protection after preset time delay;
• Relay ZR-3 does not operate;
• Fault is isolated by CB-2 in additional 30 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is b-c.

Figure 8.17 Relay ZR-2 trip signal

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Figure 8.18 Fault current at CT-2 (secondary A)

Exercise 4: Zone IV Operation

Place a three phase fault A-B-C starting at 0.02 s at 0.6 of Line 2. Disconnect the
input trip signal sending from relay ZR-2 to CB-2 and relay ZR-3 to CB-3. Observer
protection relays’ operations and explain their behaviors. What is the fault clearing time?

Figure 8.19 shows the trip signal sent by relay ZR-1. It operates 0.68 s after the fault
occurs. Figure 8.20 shows the fault current measured at CT-1. The fault is cleared after
additional 30 msec. Relays ZR-2 and ZR-3 operate but cannot trip the CB-2 and CB-3.

The protection system operates correctly:

• Zone 2 of relay ZR-2 and Zone 3 of relay ZR-3 operate but not trip the CB-1;
• Zone 4 of relay ZR-1 operates as back-up protection after preset time delay;
• Fault is isolated by CB-1 in additional 30 msec (CB is configured with 20 msec
operating time);
• Phase selection function detects that the fault type is a-b-c.
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Figure 8.19 Relay ZR-1 trip signal

Figure 8.20 Fault current at CT-1 (secondary A)

8.3 Open-loop Relaying Testing

Two software modules, “OORT.mdl” and “OIRT.mdl”, are provided for overcurrent
and impedance relay testing. To use the model, firstly run MATLAB (R2015 or later
version). Then direct the Current Directory to where this file is stored or copy the file in
 293

to MATLAB’s default work directory (typically MATLAB\R2015\work) and type

“OORT.mdl” or “OIRT.mdl”. The main menu will display in Figure 8.1 and Figure 8.2.
Double clicking on “Off-Line Testing” icon opens the model shown in Figure 8.21 and
Figure 8.22Figure 8.4.

Figure 8.21 Open-loop overcurrent relay testing model

Figure 8.22 Open-loop impedance relay testing model

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8.4 Closed-loop and Open-loop Analysis

After completing the lab exercises students will learn how to test overcurrent and
impedance relay using digital simulator based relay test system. The following activities
are performed:

• Model various power system disturbances and create test cases for relay tests
through MATLAB simulation;
• Use custom software to insert signals from external file, create test session and
replay test waveforms;
• Set up relays to be tested by using their front panel and/or application software
provided by the manufacturer;
• Observe relay behavior when exposed to various disturbances and explain it..
• Compare test results with on-line relay tests results in Section 7.1 and study relay
operating characteristics.

General Procedures for Performing Tests:

Step 1: Log in to computer with username and password, switch on the power of
simulator and relay;
Step 2: Set up calibration files for each relay being tested.

Step 3: Find the serial number (S/N) of the simulator being used printed on the left
hand side of chassis. An instance given below indicates the S/N is “P806304-4”.

Step 4: Copy the corresponding calibration file named “CalFile1_4_P04.cal” (the

last digit of S/N on chassis is “4” as shown in Figure 3) to “C:\Program
Files\TLI\RA400” and rename it as “CalFile1_4.cal”.
Step 5: Set up relay properly in terms of the protection scheme (refer to instruction
manuals).
Step 6: Open the software “Relay Assistant” and operate tests on selected relays.

Step 7: Observe relay behavior, retrieve event reports.

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Note: Repeat Step 2 to Step 4 when the computer is restarted. For distance relay,
signal input group IW and VY are used for the current inputs and voltage inputs.

Overcurrent Relay

The off-line overcurrent relay model shown in Figure 8.21 is used for the following
exercises.

Exercise 1: Instantaneous Operation

Place a single phase-to-ground fault A-G starting at 0.02 s in the middle of Line 3.
Replay current waveforms stored at Bus R to the relay being tested. Observe relay’
operation and explain its behavior. What is the relay trip time?

Indicators on the front panel show that relay tripped and the fault type was a-g.
Event report retrieved from the relay shows that the relay tripped in 17 msec after fault
occurred.

The relay operated correctly:

• Relay operated instantaneously after a fault occurs;
• Phase selection function detected that the fault type is a-g.
Exercise 2: Time Delay Operation I

Place a phase-to-phase fault (b-c) starting at 0.02 s on the 0.3 of Line 2. Replay
current waveforms stored at Bus Q to the relay being tested. Observer protection relays’
operation and explain their behavior. What is the relay trip time?
 296

Indicators on the front panel show that relay tripped and the fault type was b-c.
Event report retrieved from the relay shows that the relay tripped in 45 msec after fault
occurred.

The relay operated correctly:

• Relay operated in certain time delay after fault occurs;
• Phase selection function detected that the fault type is b-c.

Exercise 3: Definite Time Delay Operation II

Place a two phase-to-ground fault (c-a-g) starting at 0.02 s in the middle of Line 2.
Replay current waveforms stored at Bus P to the relay being tested. Observe protection
relays’ operation and explain their behavior. What is the relay trip time?

Indicators on the front panel show that relay tripped and the fault type was c-a-g.
Event report retrieved from the relay shows that the relay tripped in 67 msec after fault
occurred.

The relay operated correctly:

• Relay operated in certain time delay after fault occurs;
• Phase selection function detected that the fault type is c-a-g.
Exercise 4: Back-up Protection

Place a three-phase fault (a-b-c) starting at 0.02 s at the end of Line 3. Replay
current waveforms stored at Bus P to the relay being tested. Observer protection relays’
operation and explain their behavior. What is the relay trip time?

Indicators on the front panel show that the relay tripped and the fault type was a-b-c.
Event report retrieved from the relay shows that the relay tripped in 1.03 s after fault
occurred.

The relay operated correctly:

• Relay operated in certain time delay after fault occurs;
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• Phase selection function detected that the fault type is a-b-c.

Impedance Relay

The off-line impedance relay model shown in Figure 8.22 is used for the following
exercises.

Exercise 1: Zone I Operation

Place a single phase-to-ground fault (a-g) starting at 0.02 s in the middle of Line 1.
Replay voltage and current waveforms stored at Bus P to the relay being tested.
Observer protection relays’ operation and explain their behavior. What is the relay trip
time?

Indicators on the front panel show that the relay tripped and the fault type was A-G.
Event report retrieved from the relay shows that the relay tripped in 17 msec after fault
occurred.

The relay operated correctly:

• Relay operated instantaneously after fault occurs;
• Phase selection function detected that the fault type is a-g.
Exercise 2: Zone II Operation

Place a phase-to-phase fault b-c starting at 0.02 s at the end of Line 1. Replay
voltage and current waveforms stored at Bus P to the relay being tested. Observe
protection relays’ operation and explain their behavior. What is the relay trip time?

Indicators on the front panel show that the relay tripped and the fault type was b-c.
Event report retrieved from relay shows that the relay tripped in 0.36 s after fault
occurred.

The relay operated correctly:

• Relay operated in Zone II time delay after fault occurs;
• Phase selection function detected that the fault type is b-c.
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Exercise 3: Zone III Operation

Place a two-phase-to-ground fault (c-a-g) starting at 0.02 s at the end of Line 1.

Replay voltage and current waveforms stored at Bus Q to the relay being tested. Observe
protection relays’ operation and explain their behavior. What is the relay trip time?

Indicators on the front panel show that the relay tripped and the fault type was
C-A-G. Event report retrieved from the relay shows that the relay tripped in 1.02 s after
fault occurred.

The relay operated correctly:

• Relay operated in Zone III time delay after fault occurs;
• Phase selection function detected that the fault type is c-a-g.
Exercise 4: Zone IV Operation

Place a three phase fault (a-b-c) starting at 0.02 s at 0.6 of Line 2. Replay voltage
and current waveforms stored at Bus P to the relay being tested. Observer protection
relays’ operation and explain their behavior. What is the relay trip time?

Indicators on the front panel show that relay tripped and the fault type was a-b-c.
Event report retrieved from relay shows that the relay tripped in 0.7 s after fault
occurred.

The relay operated correctly:

• Relay operated in Zone IV time delay after fault occurs;
• Phase selection function detected that the fault type is a-b-c.