07-06-2022

SEMICONDUCTOR MEMORIES ,
VERIFICATION & TESTING
[ UNIT 5 ]

CLASSIFICATION OF MEMORIES

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RAM Organization • There are TWO types of RAM

(1) SRAM – Static Random Access
Memory
(2) DRAM – Dynamic Random Access
memory

• An SRAM cell uses two back-to-

back inverters to store 1-bit of
information.
• The 6T SRAM cell is the standard
implementation of a 1-bit SRAM
cell.
• Data in DRAM is stored as Charge
on a capacitor.
• The 1T-1C DRAM cell is the
standard implementation of 1-bit
DRAM cell.

STATIC RANDOM ACCESS (SRAM) MEMORY

• A 1-bit SRAM cell realized using 6

transistors is shown in figure.
• WL = Word Line
• BL = Bit Line
• Information is stored by the 2 CMOS
inverters in feedback.
• Word Line is used to select a
particular cell for either read/write.
• Bit Line is used to drive logic value
into the memory cell.
• The logic value driven through bit line
is then stored inside the cell.

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STATIC RANDOM ACCESS (SRAM) MEMORY

• A 1-bit SRAM cell realized using 6

transistors is shown in figure.
• WL = Word Line
• BL = Bit Line
• Information is stored by the 2 CMOS
inverters in feedback.
• Read/Write is done by two extra
NMOS transistors (N2 and N4).
• Word Line is used to select a
particular cell for either read/write.
• Bit Line is used to drive logic value
into the memory cell.
• The logic value driven through bit
line is then stored inside the cell.

SRAM WRITE OPERATION WRITE OPERATION

• The WRITE operation consists of the

following sequence.
1. Drive BL and BL’ with necessary
values.
2. Turn on WL
3. Bit Lines overpower cell with new
values
Example:
Assume Q = 0 , Q’ =1 [ Logic 0 is stored in
the SRAM cell]
If BL =1 and BL’ = 0 then it forces Q’ to ‘0’
and Q to ‘1’
[ Logic 1 is stored in SRAM cell now ]

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SRAM READ OPERATION READ OPERATION

• The READ operation consists of the

following sequence.
1. Pre-Charge BL and BL’ to high
2. Turn on WL
3. BL or BL’ will be pulled down to
Low (Logic ‘0’) depending on Q ,
Q’
Example:
If Q = 0 , Q’ =1 [ Logic 0 is stored in
the SRAM cell]
Then BL discharges through N2 – N1 – GND
and BL’ stays high.

SRAM READ OPERATION

• SENSE AMPLIFIER:
• A Sense amplifier is used to read the
data stored inside the SRAM cell.
• It is an op-amp comparator circuit.
• It compares the difference between
BL and BL_bar.
• If BL > BL_bar, output is 1
• If BL < BL_bar, output is 0
• Advantage: It sets the output quickly
without fully charging/discharging.

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DRAM MEMORY
• A 1-bit DRAM cell realized using one
transistor and one capacitor is shown
in fig.
• Smaller cell size, therefore smaller and
cheaper.
• It is called 1T-1C DRAM cell
• The logic value (data) is stored as
charge on the capacitor Cs.
• The capacitor charge leaks with time,
hence it has to be refreshed.
• Volatile: It loses data when powered
OFF.
• Charge storage, Q = C Vdd

DRAM OPERATION

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DRAM OPERATION
• REFRESH OPERATION:
• The process of reading the information of memory and immediately
re-writing the same without modifications is called refresh operation.
• External circuitry periodically refreshes memory cycles, automatically in the
background.
• The refresh cycles are generated by separate counter circuits in the memory.
• The refresh rate is generally in the order of milliseconds.

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Masked ROM (MROM)

• The contents of MROM is programmed during fabrication.
• The actual contents are determined by the layout of a
mask.
• The presence and absence of a transistor determines the
data stored in MROM.
• 1-bit stored – absence of active transistor
• 0-bit stored – presence of active transistor
• MROM is non-volatile.
• They are also denser for a given technology, and are
potentially faster and consumes less power.
• The basic structure of ROM are of two types:
• NOR ROM
• NAND ROM
• Typical Applications:
• Store the micro-coded instructions set of a
microprocessor.
• Store a portion of the operating system for PCs.
• Store the fixed programs for microcontrollers
(firmware).

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1.

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LAYOUT

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2.

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LAYOUT

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Programmable ROM (PROM)

• The contents of PROM is programmed after fabrication.
• The data is programmed (or) burned into PROM using
special PROM Programmers.
• The data is then permanent and cannot be changed. i.e.
PROMs are non-volatile.
• It is one type of read-only memory (ROM).
• The key difference from a MROM is that the data is written
into a MROM during manufacture, while with a PROM the
data is programmed into them after manufacture.
• PROMs are manufactured blank and, depending on the
technology, can be programmed at wafer, final test, or in
system.
• Blank PROM chips are programmed by plugging them into a
device called a PROM programmer.

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Programmable ROM (PROM)

These types of memories are frequently used in:
• Microcontrollers
• Video game consoles
• Mobile phones
• Radio-frequency identification (RFID) tags
• Implantable medical devices
• High-definition multimedia interfaces (HDMI)
and in many other consumer and automotive electronics
products.

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EPROM
UV PROM CHIP

EPROM ERASER

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Verification in Verification Methodologies

In VLSI Design Flow
VLSI Design
• Verification is the process of
checking the design against
the given functionality and
specification.
• There are mainly two types of
verifications performed:
• LOGIC VERIFCATION
• PHYSICAL VERIFCATION

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Logic Verification

• Logic verification is the process of checking the functionality of the circuit.

• It can be classified into two categories:
• Static verification
• Dynamic verification (simulation-based)
STATIC VERIFICATION:
• In the static verification process, no simulation is performed on the circuit.
• It checks against some rules such as electrical rules, design rules, schematic check etc.
• It is fast compared to the dynamic verification process.
DYNAMIC VERIFICATION:
• In the dynamic verification process, the circuit is simulated to check its correctness.
• It is very slow but most accurate and not applicable for the whole big system.

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Logic Verification Principles

• The figure shows a combinational circuit with N-inputs.
• To test this circuit exhaustively, a sequence of 2N test
vectors must be applied and observed.
• This circuit is converted to a sequential circuit with
addition of M registers.
• A minimum of 2N+M test vectors must be applied to exhaustively test the circuit.
• Clearly, exhaustive testing is infeasible for large systems.
• The verification engineer must cleverly devise test vectors that detect any defective node
without requiring so many patterns.

Note: With VLSI, this may be a network with N=25 and M=50 or 275 patterns, which is approximately
3.8 x1022.
Assuming one had the patterns and applied them at an application rate of 1us per pattern, the
test time would be over a billion years (109)

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Test Vectors
• Test vectors are a set of patterns applied to inputs and a set of expected outputs.
• Both logic verification and manufacturing test require a good set of test vectors.
• Directed and random vectors are the most common types. (see figure)
• DIRECTED VECTORS are selected by an engineer who is knowledgeable about the system.
• Their purpose is to cover the corner cases where the system might be most likely to malfunction.
• For example, in a 32-bit datapath, likely corner cases include
the following:
Test
Vectors

Directed Random

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Test Vectors
• Directed vectors are an efficient way to catch the most Test
obvious design errors. Vectors
• A good logic designer will always run a set of directed
Directed Random
tests on a new piece of RTL to ensure a minimum level
of quality.
RANDOM TEST VECTORS:
• Applying a large number of random or semirandom vectors is a surprisingly good way to detect
more subtle errors.
• The effectiveness of the set of vectors is measured by the fault coverage.
• Automatic test pattern generation tools are good at producing high fault coverage for
manufacturing test.

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TESTING AND MANUFACTURING TEST PRINCIPLES

• The purpose of manufacturing test
is to screen out most of the
defective parts before they are
shipped to the customers.
• Typical commercial products target
a defect rate of 350–1000 defects
per million (DPM) chips shipped.
• The customer then assembles
systems from the chips, tests the
systems, and discards or repairs
defective systems.
• A high defect rate leads to unhappy customers.

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FAULT MODELS
• To deal with the existence of good and bad parts,
it is necessary to propose a fault model;
• Fault model represent how faults occur and their
impact on circuits.
• The most popular model is called the Stuck-At
model.
• The Short Circuit/Open Circuit model can be a
closer fit to reality, but is harder to incorporate
into logic simulation tools.
STUCK-AT MODEL:
• In the Stuck-At model, a faulty gate input is
modelled as a stuck at zero (Stuck-At-0, SA0) or
stuck at one (Stuck-At-1, SA1).

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FAULT MODELS
• To deal with the existence of good and bad parts, it is
necessary to propose a fault model;
• Fault model represent how faults occur and their
impact on circuits.
• The most popular model is called the Stuck-At model.
• The Short Circuit/Open Circuit model can be a closer
fit to reality, but is harder to incorporate into logic
simulation tools.
STUCK-AT MODEL:
• In the Stuck-At model, a faulty gate input is modelled
as a stuck at zero (Stuck-At-0, SA0) or stuck at one
(Stuck-At-1, SA1).
• Figure illustrates how an S-A-0 or S-A-1 fault might
occur.
• These faults most frequently occur due to:
(i) gate oxide shorts (the nMOS gate to GND or the
pMOS gate to VDD) or (ii) metal-to-metal shorts.

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FAULT MODELS
SHORT-CIRCUIT AND OPEN-CIRCUIT FAULTS:
• Other models include stuck-open or shorted models.
• Two bridging or shorted faults are shown in Figure.
• The short S1 results in an SA0 fault at input A, while short S2
modifies the function of the gate.
• Faults should be modelled at the transistor level because it is only at
this level that the complete circuit structure is known.
• This implies that test generation should ideally
take account of possible shorts and open circuits
at the switch level.

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FAULT MODELS
A Combinational circuit being converted to a Sequential
Circuit due to a fault.
• A particular problem that arises with CMOS is
that it is possible for a fault to convert a
combinational circuit into a sequential circuit.
• This is illustrated in Figure for the case of a
2-input NOR gate in which one of the transistors
is rendered ineffective.
• If nMOS transistor A is stuck open, then the
function displayed by the gate will be:

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CONTROLLABILITY AND OBSERVABILITY

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CONTROLLABILITY AND OBSERVABILITY

OBSERVABILITY :
• The observability of a particular circuit node is the degree to which we can observe that
node at the outputs of an integrated circuit (i.e., the pins).
• This metric is relevant when we want to measure the output of a gate within a larger circuit
to check that it operates correctly.
• Given the limited number of nodes that can be directly observed, it is the aim of good chip
designers to have easily observed gate outputs.
• Adoption of some basic design for test techniques can aid tremendously in this respect.
• Ideally, we should be able to observe directly or wait for few cycles every gate output
within an integrated circuit.
• While at one time this aim was hindered by the expense of extra test circuitry and a lack of
design methodology, current processes and design practices allow us to do it.

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CONTROLLABILITY AND OBSERVABILITY

CONTROLLABILITY :
• The controllability of an internal circuit node within a chip is a measure of the ease of setting
the node to a 1 or 0 state.
• This metric is of importance when assessing the degree of difficulty of testing a particular
signal within a circuit.
• An easily controllable node would be directly settable via an input pad.
• A node with little controllability, such as the most significant bit of a counter, might require
many hundreds or thousands of cycles to get it to the right state.
• Often, we will find it impossible to generate a test sequence to set a number of poorly
controllable nodes into the right state.
• It should be the aim of good chip designers to make all nodes easily controllable.
• In common with observability, the adoption of some simple design for test techniques can aid
in this respect tremendously.
• Making all flip-flops resettable via a global reset signal is one step toward good controllability.

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REPEATABILITY AND SURVIVABILITY

REPEATABILITY :
• The repeatability of system is the ability to produce the same outputs given the same inputs.
• Combinational logic and synchronous sequential logic is always repeatable when it is functioning
correctly.
• However, certain asynchronous sequential circuits are nondeterministic. For example, an arbiter
may select either input when both arrive at nearly the same time.
• Testing is much easier when the system is repeatable.
• Some systems with asynchronous interfaces have a lock-step mode to facilitate repeatable
testing.
SURVIVABILITY :
• The survivability of a system is the ability to continue function after a fault.
• For example, In Memories error-correcting codes provide survivability in the event of soft errors.
• Redundant rows and columns in memories and spare cores provide survivability in the event of
manufacturing defects.

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FAULT COVERAGE
• A measure of goodness of a set of test vectors is the amount of fault coverage it achieves.
• That is, for the vectors applied, what percentage of the chip’s internal nodes were
checked?
• Conceptually, the way in which the fault coverage is calculated is as follows:
“ Each circuit node is taken in sequence and held to 0 (S-A-0), and the circuit is simulated
with the test vectors comparing the chip outputs with a known good machine––a circuit with
no nodes artificially set to 0 (or 1).
When a discrepancy is detected between the faulty machine and the good machine,
the fault is marked as detected and the simulation is stopped. This is repeated for setting the
node to 1 (S-A-1). In turn, every node is stuck (artificially) at 1 and 0 sequentially”
• The fault coverage of a set of test vectors is the percentage of the total nodes that can be
detected as faulty when the vectors are applied.
• To achieve world-class quality levels, circuits are required to have in excess of 98.5% fault
coverage.

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DESIGN FOR MANUFACTURABILITY

• A Circuits can be optimized for manufacturability to increase their yield.
• This can be done in a number of different ways.
(1) PHYSICAL LEVEL:
• At the physical level (i.e., mask level), the yield and hence manufacturability can be improved
by reducing the effect of process defects.
• The design rules for particular processes will frequently have guidelines for improving yield.
Some examples of guidelines are:
• Increase the spacing between wires where possible, this reduces the chance of a defect causing
a short circuit.
• Increase the overlap of layers around contacts and vias––this reduces the chance that a
misalignment will cause an aberration in the contact structure.
• Increase the number of vias at wire intersections beyond one if possible, this reduces the chance
of a defect causing an open circuit.
• Electronic Design Automation tools are dealing with these kinds of optimizations automatically.

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DESIGN FOR MANUFACTURABILITY (DFM)

(2) REDUNDANCY :
• Redundant structures can be used to
compensate for defective components on a
chip.
• For example, memory arrays are commonly
built with extra rows.
• During manufacturing test, if one of the words
is found to be defective, the memory can be
• reconfigured to access the spare row instead.
• Laser-cut wires or electrically programmable
fuses can be used for configuration.
• Similarly, if the memory has many banks and
Fig: Spare rows being activated due to faulty rows
one or more are found to be defective, they
in a memory chip.
can be disabled, possibly even under software
control.

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DESIGN FOR MANUFACTURABILITY (DFM)

(3) POWER :
• Elevated power can cause failure due to excess
current in wires, which in turn can cause metal
migration failures.
• In addition, high-power devices raise the chip
temperature, degrading device performance and,
over time, causing device parameter shifts.
• The method of dealing with this component of
manufacturability is to minimize power through
design techniques.
• In addition, a suitable package and heat sink should
be chosen to remove excess heat.

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DESIGN FOR MANUFACTURABILITY (DFM)

(4) YIELD ANALYSIS :
• When a chip has poor yield or will be manufactured in high volume, chips that fail
manufacturing test can be taken to a laboratory for yield analysis to locate the root cause
of the failure.
• If particular structures are determined to have caused many of the failures, the layout of
the structures can be redesigned.
• For example, during volume production ramp-up for the Pentium microprocessor, the
silicide over long thin polysilicon lines was found to crack and raise the wire resistance.
• This in turn led to slower-than-expected operation for the cracked chips.
• The layout was modified to widen polysilicon wires or strap them with metal wherever
possible, boosting the yield at higher frequencies.

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