H. V.

Ravish Aradhya

ANLYSIS AND DESIGN OF DIGITAL CIRCUITS

THEORY AND PRACTICE(10EC33)

UNIT-1: Review of Basics and MSI Components

A. Review of Basics:

1. Write out the truth table and draw the circuit corresponding to the
Boolean function

Soln: Truth table Logic Diagram

Figure 1.1: Function table and circuit for example-1

2. Write out the Boolean expression for in fundamental sum
ofproducts (SOP) form.

Soln:The product terms (which contain all of the input variables) are
calledfundamentalproduct terms or 'canonical‟ SOP terms.

Using the truth table written out for this function in Problem-1, we can write

3. Express the Boolean expression in fundamental sum of

products (SOP) form.

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Soln:Thealternate Canonical SOP form of the given expression

is

4. Draw the logic circuit to implement the fundamental sum of products

expression below and then minimize it to obtain the simplified Boolean
expression .

Soln:

(a) Circuit for un-simplified expression

(b) Circuit for simplified expression

Figure 1.2: Circuit realization for example-4

5. Minimize the logic expression below and draw the logic circuit for the
simplified expression .

Soln:

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6. Minimize the logic expression below and draw the logic circuit for the
simplified expression .

Soln:

7. Simplify using Boolean laws:

Soln: F= (A‟ + C‟) + ABC + AC; Using De-Morgan‟s law (Similarly, readers
are required list out all applicable laws in each step)

= (A‟ + AC) + (C‟ + ABC) = (A‟ + C) + (C‟ + AB) = (C + C‟) + (A‟ +

AB) = (1) + (A‟ + B) = 1

Soln: F= XY(Z + Z‟) + X‟Y = XY (1) + X‟Y =Y (X + X‟) = Y(1) = Y

Soln: F= X(Y + Y‟Z) + YZ = X(Y +Z) + YZ = XY + XZ + YZ

Soln: F= AB‟ + AB(D + D‟) + (A‟ + B‟ + C‟) + A‟BC‟;Using De-Morgan‟s

law(Similarly, the reader is required list outall applicable laws in each
step)

= AB‟ + AB(1) + (A‟ + B‟ + C‟) + A‟BC‟

= A (B‟ + B) + (A‟ (1+ BC‟)) + B‟ + C‟ = A (1) + (A‟ (1)) + B‟ + C‟

= (A + A‟) + B‟ + C‟ =1

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Soln: F= B(D + CD‟) + A(B‟ + C‟ + D‟) = B(D + C) + A(B‟ + C‟ + D‟)‟ = BD

+ BC + AB‟ + AC‟ + AD‟

Karnaugh Maps:

Minterm:Each fundamental product term occupies a single cell in the

Karnaugh map and is called a „minterm‟ (as it specifics the minimum area
of l's, i.e. a single cell in a SOP representation) in the Karnaugh map. A
minterm is also called as an implicant.

Maxterm:Each fundamental sum term occupies a single cell in the

Karnaugh map and is called a „minterm‟ in the Karnaugh map (it is the dual
of the minterm, i.e. a single cell in POS representation). A minterm is also
called as an implicant.

Prime implicants (PI): A „prime implicant‟ is a product term obtained by

combining the maximum possible number of minterms from adjacent
squares in the map. Once the minterms are looped and grouped in the
minimization process, it forms duals (pairs), quads and octets. The duals
(pairs), the quads and the octets are therefore called prime implicants.

Essential prime implicants(EPI): An „essential prime implicant‟ is a prime

implicant that includes at least one minterm which is not covered by any
other prime implicant. In order to minimize a function all of the
minterms in the K-map must be covered (i.e. grouped and looped),
since they must be contained in the minimized Boolean expression.
However, if all of the possible groups, that is the prime implicants, are used
in the final minimized sum of product expression there may be more of
them than are strictly necessary to cover the whole map. Those
prime implicants which describe product terms which must be used for
all minterms to be covered are called essential prime implicants.

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Figure 1.3: K-map example

The map for X contains four prime implicants: the quad, BD; and
duals ABC‟, A‟BC and A‟CD‟. However, only three of these are essential
prime implicants since A‟BC is also covered by BD and A‟CD‟. The minimized
expression is therefore

The map for Y contains six prime implicants: the quads C‟D and AB;
and duals A‟B‟D, A‟B‟C, ACD‟ and B‟CD‟. Only two of these are
essential prime implicants, namely" AB and C‟D. The remaining three
minterms A‟B‟CD, A‟B‟CD‟ and AB‟CD‟ must also be covered by
choosing appropriate non-essential prime implicants from the four
remaining. This can be achieved a number of ways, any of which provide a
complete and therefore adequate minimized expression. These are

Redundant groups:The map for Y below contains three prime implicants

AB, A‟C and BC. Of these AB and A‟C are essential prime implicants with
BC non-essential or redundant, since it is also covered by these two.

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Figure 1.4: K-map example

Therefore, the minimized form is

8. Simplify using K-map:

Soln:

Figure 1.5: K-map for example-8

9. Simplify using K-map f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)

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Soln:

Figure 1.6: K-map for example-9

10.Don’t-care Conditions:

P = A'B'C'D' + B'CD + BC'D + BCD' + AD

Figure 1.7: K-map with don’t cares

11.Getting POS Expressions: Simplified POS expression can be obtained
by grouping the maxterms (i.e. 0s) of given function. Given
F=m(0,1,2,3,5,7,8,9,10,11), we first draw the K-map, then group the
maxterms together

Figure 1.8: K-map for POS expression

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Figure 1.9: K-map for POS expression

The rules for using Karnaugh maps are as follows:

i. Draw the map, remembering the 'pattern' when filling from a

truth table.
ii. Loop all octets, quads and duals (groups of eight, four and two
adjacent minterms). These are the prime implicants. It does not
matter if some minterms are covered more than once, although
duals should not be totally enclosed in quads, and quads in
octets as this simply means full minimization has not been
performed.
iii. Remember the map can be 'rolled' across its edges, or across
the two maps in the case of a five-variable map.
iv. Remember that you can set 'don't care' or 'can't happen' terms
to either 0 or 1 to aid minimization.
v. Determine which prime implicants are essential and so must be
used in the minimized sum of products expression.
vi. Pick enough prime implicants which together with the essential
prime implicants already selected will cover the whole map.
Other non-essential prime implicants need not be included in the
minimized expression.

Also bear in mind:

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i. Although the minimized expression is obtained it may not be the best

expression for your particular problem (e.g. you may already have
generated otherproduct terms, for some other circuit, which could
be used).
ii. Look out for the characteristic XOR pattern that cannot be
minimized but which is implemented easily using XOR gates.
iii. Do not forget that it is sometimes easier to minimize by
inspection from thetruth table (i.e. a Karnaugh map may not offer
the best route to minimization).

5-Variable K-maps

A 5-variable K-Map, which consists of 25 or 32 cells numbered from 0 to 31,

is drawn as a group of two 4-variable K-Maps. The logic behind drawing two
maps instead of a single map is that in any binary progression there are
exactly half number of input combinations with MSB as '0' and the rest half
with MSB as '1'. This also means that there are exactly half minterms /
maxterms in any binary progression with MSB as '0' and the other half with
MSB as '1', as shown in Fig 1.10.

Number Total Minterms/Maxte Minterms/Max

of Possible rms terms
Function
Variabl combinat With MSB as '0' With MSB as
es ions ( a=0) '1'( a=1)
f(a,b) 2 4 0 to 1 2 to 3
f(a,b,c) 3 8 0 to 3 4 to 7
f(a,b,c,d) 4 16 0 to 7 8 to 15
f(a,b,c,d,e) 5 32 0 to 15 16 to 31
f(a,b,c,d,e,f) 6 64 0 to 31 32 to 63
Figure 1.10: Segregation of minterms/maxterms based on MSB

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The K-Map of 5-variable function f(a, b, c, d, e) shown in Fig. 3.2 is divided

into two 4-variable K-Maps (i) the 1st map of 4-variables b, c, d and e
consisting of 16 cells corresponding to minterms/maxterms 0 to 15 with the
MSB 'a' as 0 and (ii) the 2nd map of 4-variables b, c, d and e consisting of 16
cells corresponding to minterms/maxterms 16 to 31 with the MSB 'a' as 1.
Similarly, a 4-variable K-Map can also be expressed as a group of two 3-
variable K-Maps, but we don't do so as it is not very difficult to group
minterms/maxterms in just 16 cells. Each cell in a 5-variable K-Map will
have a maximum of five adjacent cells, as shown in Fig 1.11. For example
the adjacent cells of a cell numbered 4, have been highlighted in Fig. 1.12.
An important observation that we should make here is that any two
cells whose decimal values differ by 16 are also adjacent cells. Their
locations on the two maps will be exactly same. For example, cells (4, 20),
(10, 26), (15, 31) etc. are therefore called adjacent cells and their binary
representations differ only in the MSB position as shown below and therefore
the MSB and its complement gets eliminated, when such cells are formed as
a pair.

  

4= 00100 10  01010
 15  01111


20  10100 
26  11010 
31  11111

Cell Adjacent Cells Cell Adjacent Cells Cell Adjacent Cells Cell Adjacent Cells
0 1, 2, 4, 8, 16 8 0, 9, 10, 12, 24 16 0, 17, 18, 20, 24 24 8, 16, 25, 26, 28,
1 0, 3, 5, 9, 17 9 1, 8, 11, 13, 25 17 1, 16, 19, 21, 25 25 9, 17, 24, 27, 29
2 0, 3, 6, 10, 18 10 2, 8, 11, 14, 26 18 2, 16, 19, 22, 26 26 10, 18, 24, 27, 30
3 1, 2, 7, 11, 19 11 3, 9, 10, 15, 27 19 3, 17, 18, 23, 27 27 11, 19, 25, 26, 31
4 0, 5, 6, 12, 20 12 4, 8, 13, 14, 28 20 4, 16, 21, 22, 28 28 12, 20, 24, 29, 30
5 1, 4, 7, 13, 21 13 5, 9, 12, 15, 29 21 5, 17, 20, 23, 29 29 13, 21, 25, 28, 31
6 2, 4, 7, 14, 22 14 6, 10, 12, 15, 30 22 6, 18, 20, 23, 30 30 14, 22, 26, 28, 31
7 3, 5, 6, 15, 23 15 7, 11, 13, 14, 31 23 7, 19, 21, 22, 31 31 15, 23, 27, 29, 30
Figure 1.11: Adjacent Cells in a five variable K-Map

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Column a=0 ← MSB → a=1

Variables
de de de de de de de de de
00 01 11 10 00 01 11 10

bc 0 1 3 2 16 17 19 18
00

bc 4 5 7 6 20 21 23 22
01

bc 12 13 15 14 28 29 31 30
11

bc 8 9 11 10 24 25 27 26
Row 10
Variables
bc
Figure 1.12: Five Variable K-Map

Let us see some examples of grouping the cells in a 5-variable map and the
process of obtaining their reduced expressions. Fig. 1.13 shows a 5-variable
map where there is no matching terms i.e. minterms in the same locations,
on both the maps. Observe in such a case that the variable 'a' appears,
either in complemented form (if the group is present on the left side map) or
un-complemented form (if the group is present on the right side map), in
the reduced expression for every group. Except for this difference, the rules
for obtaining the reduced expression are same as those of a 4-variable K-
Map. In contrast to Fig. 1.13, note that exact matching of terms are shown
in Fig. 1.14. Observe that the variable 'a' is missing in all the reduced
expressions for the reason that the groups have been spread over two maps.

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a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 11 11 11 abcde
a b cde
00
4 5 7 6 20 21 23 22
bc 1 11
ade 11 acd
01
12 13 15 14 28 29 31 30
bc 1 11 11
11
8 9 11 10 24 25 27 26
bc 11 11 11 abce
10

Figure 1.13: Five Variable K-Map without any matching

Minterms on both theMaps

For example, the reduced expression for the pair and quad in Figure 1.13 is
as below:

Pair
Minterms  1 17
Binary  00001 10001
Expression  a b c de + ab c de = b c de

Quad
2 = 
00010 
18 = 10010
6 = 
00110 
22 = 10110
Expression = 
abcde 
abcde
Reduced Expression  ab de + ab de = bde

It is easy to see that the octet in the 3rd row of Fig. 1.14 corresponds to the
reduced expression 'bc', as it eliminates 3 variables. The following examples
will reinforce the above concepts in a clear way.

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a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 Pair 1 11
00 bcde
4 5 7 61 Qua 20 21 23 221
bc
1 d 1
01
bde
12 13 15 14 Octe 281 29
1 31
1 130
bc 1 1 1 1
1 1 1 1 t 1 1 1 1
11
bc
8 9 11 10 24 25 27 26
bc
10
Figure 1.14: Five variable K-Map with matching
Minterms on both the Maps

12.Simplify the following Boolean function and obtain the most optimal sum
of products expression.

f(a,b,c,d,e) = Σm (0, 1, 4, 5, 6, 7, 9, 12, 13, 14, 15, 16, 17, 20, 21, 22, 23, 25, 29)

Soln:The given minterms are mapped on to a 5-variable K-Map as in Fig.

a=0 a=1
de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 1 1
00
4 5 7 6 20 21 23 22
bc 1 1 1 1 1 1 1 1
01
12 13 15 14 28 29 31 30
bc 1 1 1 1 1
11
8 9 11 10 24 25 27 26
bc 1 1
10
Figure 1.15: Five Variable K-Map for Example 3.1
1.15.

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First of all we should see if a group of minterms are available in the same
locations on both the maps. Suppose we group cells (4, 5, 6, 7) as a quad,
we see that it can be combined into an octet with another group of cells (20,
21, 22, 23) which are exactly in the same locations on the other map, as
shown in Fig. 1.16.

a=0 a=1
de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 1 1
00
4 5 7 6 20 21 23 22
bc Octet
11 11 11 1 1 11 11 11 11
01 bc
12 13 15 14 28 29 31 30
bc 1 1 1 1 1
11
8 9 11 10 24 25 27 26
bc 1 1
10
Figure 1.16: Grouping of Minterms for Example 3.1 - Step 1

The cells covered after step 1 are identified with a 'X' symbol as shown
below.

Minterms  0 1 4 5 6 7 9 12 13 14 15 16 17 20 21 22 23 25 29
Covered after step 1  X X X X X X X X

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a=0 a=1
de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 Octet 1 1
00 1 1 1 1
bd
4 5 7 6 20 21 23 22
bc 11 1
01 11 1 111 11 1 1 111 11 11
12 13 15 14 28 29 31 30
bc 1 1 1 1 1
11
8 9 11 10 24 25 27 26
bc 1 1
10
Figure 1.17: Grouping of Minterms for Example 3.1 - Step 2

Now we see that another octet could be formed by combining (0, 1, 4, 5)

with (16, 17, 20, 21), as shown in Fig. 1.17. The minterms covered up to
step 2 are as shown below and the process is repeated until we find a 'X'
below each minterm.

Minterms  0 1 4 5 6 7 9 12 13 14 15 16 17 20 21 22 23 25 29
Covered after step 2  X X X X X X X X X X X X

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a=0 a=1
de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 1 1
00 1 11 1 11
4 5 7 6 20 21 23 22
bc 111
01 111 111 11 1 1 1111 11 11
12 13 15 14 28 29 31 30
bc 1 11 1 1 Octet 11
11
de
8 9 11 10 24 25 27 26
bc 1
1 11
10
Figure 1.18: Grouping of Minterms for Example 3.1 - Step 3

Minterms  0 1 4 5 6 7 9 12 13 14 15 16 17 20 21 22 23 25 29
Covered after step 3  X X X X X X X X X X X X X X X X
a=0 a=1
de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc 1 1 1 1
00 1 11 1 11
4 5 7 6 20 21 23 22
bc 111
01
111 11 11 11 1 1111 11 11
12 13 15 14 Octet
28 29 31 30
bc 1 11 1 1 ac 1
11
8 9 11 10 24 25 27 26
bc 11 1
10

Figure 1.19: Grouping of Minterms for Example 3.1 - Step 4

Minterms  0 1 4 5 6 7 9 12 13 14 15 16 17 20 21 22 23 25 29
Covered after step 4  X X X X X X X X X X X X X X X X X X X

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Since all the minterms are covered at least once, by step 4, we stop the
process. Hence, the MSOP expression, consisting of four octets, is finally

obtained as

f(a,b,c,d,e) = b c + b d + d e + a c

13.Draw the 2-level NAND circuit for the following Boolean expression

F = (ab+cd)e + bc(a+b) . Also obtain the minimal SOP expression and

draw the circuit using NAND gates.

Soln:The given function F is a 5-variable function. In order to draw the 2-
level NAND circuit, we expand F as
F = (ab+cd)e + bc(a+b)
= abe + cde + abc + bc
To obtain the minimal SOP expression, we expand the function F further so
as to express it in Σm form, as shown below.
Product Terms of F
a b - - e - - c d e a b c - - - b c - -

1 0 0 0 1 = 17 0 0 1 0 1 = 5 1 1 1 0 0 = 28 0 1 1 0 0 = 12
1 0 0 1 1 = 19 0 1 1 0 1 = 13 1 1 1 0 1 = 29 0 1 1 0 1 = 13
1 1 1 0 1 = 21 1 0 1 0 1 = 21 1 1 1 1 0 = 30 0 1 1 1 0 = 14
1 0 1 1 1 = 23 1 1 1 0 1 = 29 1 1 1 1 1 = 31 0 1 1 1 1 = 15
1 1 1 0 0 = 28
1 1 1 0 1 = 29
1 1 1 1 0 = 30
1 1 1 1 1 = 31
Figure 1.20: Product terms of ‘F’

On removing the repeated minterms, which are shown as cut in the above
table, the function F can be expressed as

F(a,b,c,d,e) = Σm (5, 12, 13, 14, 15, 17, 19, 21, 23, 28, 29, 30, 31)

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The five variable K-Map for F is as shown in Fig. 1.21.

a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc Quad
1 1
1 1 abe
00
4 5 7 6 Quad 20 21 23 22
bc 1 1 1
01 1 cde 1 1
12 13 15 14 28 29 31 30
bc
11 11 111 11 1 1 Octet 11 11 11 11
bc
8 9 11 10 24 25 27 26
bc
10

Figure 1.21: Five Variable K-Map for Example 3.2

The 2-level NAND circuit that implements the original function F, along with
the simplified circuit drawn based on the minimal SOP expression obtained
through K-Map, is shown in Fig. 1.22. The simplification process has
removed one 3-input NAND gate.

a
b a
e b
c e
d c
e F d
a F
e
b
c b
b c
c
(b) Simplified Circuit
(a) Original Circuit

Figure 1.22: Two-Level NAND Circuits

14. Simplify the following Boolean function and obtain the most optimal sum
of products expression.

f(a,b,c,d,e) = Σm (8, 12, 13, 18, 19, 21, 22, 24, 25, 28, 30, 31) + d.c (1, 2, 4, 6, 7, 11, 26)

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Soln: This is an example of an incompletely specified 5-variable Boolean

function. The don't care terms are treated in the same way as it was done in
3 and 4-variable K-Maps i.e. use them to our advantage if possible while
grouping else simply ignore them. The K-Map for is drawn in Fig. 1.23.

a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc
X X 1 1
00
4 5 7 6 20 21 23 22
bc
X X X 1 1
01
12 13 15 14 28 29 31 30
bc
1 1 1 1 1
11
8 9 11 10 24 25 27 26
bc
1 X 1 1 X
10
Figure 1.23: Five Variable K-Map for Example 3.3

The grouping of minterms is as shown in Figure 1.24. Observe that all the
don't care terms, except the one in cell 26, remain unused. There are 2
quads, 3 pairs and an isolated minterm. The reduced expression for each
group is also shown in Fig. 3.24. The MSOP expression is given by

f(a,b,c,d,e) = b d e + a d e + a b c d + a b c d + a b c d + a b c d e

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a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 00 01 11 10
0 1 3 2 16 17 19 18
bc X X Pair
00 11 11 abcd
4 5 7 6 20 21 23 22
bc Single Term Quad
X X X 1
01 abcde 11 1
ade
12 13 15 14 28 29 31 30
bc Pair
11
Pair
11 11 11 a bcd 1 1 1
abcd
8 9 11 10 Quad 24 25 27 26
bc 1 X 1 11 X
X
bde
10 Pair
abc d
Figure 1.24: Minterm grouping

15. Design an SOP logic circuit, which will output a 1(logic High) whenever
the input is the binary equivalent of decimal 0, 1, 5, 7, 8, 10, 13, 15, 16, 17,
23, 24 and 31. JNTU-Nov/2009
Soln:The circuit to be designed will have 5-inputs for the reason that the
binary representation of 31, the largest decimal to be detected, needs 5 bits.
Assuming the five input variables as a, b, c, d,e and the output as F, the
equation for the output can be written as

F(a,b,c,d,e) = m (0, 1, 5, 7, 8, 10, 13, 15, 16, 17, 23, 24, 31)

We can obtain the MSOP expression through the 5-variable K-Map

minimization, shown in Fig. 1.25, as

F(a,b,c,d,e) = bcd + cde + ace + cde + abce

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a=0 ← MSB → a=1

de de de de de de de de
00 01 11 10 Quad 00 01 11 10
0 1 3 2 bcd 16 17 19 18
bc 111 11 111 11
00 Quad
4 5 7 6 cde 20 21 23 22
bc 1 1 11 Quad 11
01
12 13 15 14 ace 28 29 31 30
bc 1 1
11 1 1 1 Quad 11
cde 24 25 27 26
8 9 11 10
bc Pair 1
11 1 1
10 abce

Figure 1.25: K-Map for Example 3.4

The logic circuit for F can be constructed either as AND-OR circuit or as

NAND-NAND circuit with 5 gates (four 3-input gates and one 4-input gate) at
level 1 and a single 5-input gate at level 2.

Code Converters

16. Design a 4-bit BCD to Exess-3 code converter.

Soln: Truth Table:

BCD EXESS 3
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1

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0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

K-map for Z: K-map for Y:

K-map for X: K-map for W:
The expressions are given Eq. 1.1.

Z = D, Y = C ⊕ D, X = B ⊕ (C+D), W = A + B(C + D) . . . . . Eq. 1.1

Circuit diagram:

Figure 1.26: Logic diagram of BCD to EXCESS-3 code converter

17. Design a 4-bit Exess-3 to BCD code converter.

Soln:K-maps are drawn similar to Ex.10 and the expressions are inEq. 1.2.
D = Z, C = Y ⊕ Z, B = X ⊕ YZ, A = W(X + YZ). . . . . .Eq. 1.2
Circuit diagram:

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Figure 1.27: Logic diagram of EXCESS-3 to BCD code converter

18. Design a 4-bit Binary to Gray code converter.

Soln: Truth Table:

BINARY CODE GRAY CODE
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-maps are drawn similar to Ex.10 and the expressions areinEq. 1.3.
G3 = B3, G2 = B3 + B2, G1 = B2 + B1, G0 = B1 + B0 . . . . . . Eq. 1.3

19. Design a 4-bit Gray to Binary code converter.

Soln:K-maps are drawn similar to Ex.10 and the expressions areinEq. 1.4.
B3 = G3, B2 = G2 + B3, B1 = G1 + B2, B0 = G0 + B1 . . . . . . Eq. 1.4

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B. MSI Circuits:

Adders: Abinary adder is a circuit which adds the two input binary numbers
A and B.The circuit produces the two outputsnamely Sum (S O) and Carry
(CO).

(a)Logic diagram (b) Function Table

Figure 1.28: Block diagram of Adders
For addition, if only the two input bits are used and the carry output
from the previous stage is not considered then, the adder circuit is called
“Half adder.”
On the other hand, if the carry output from the previous stage is also
consideredfor addition, along with the two input bits then, the adder circuit
is called “Full adder.”
Subtractors: A binary subtractor is a circuit which subtracts the two input
binary numbers A and B.The circuit produces the two outputsnamely
Difference (DO) and Borrow(BO). For subtraction, if only the two input digits
are used and the borrow output from the previous stage is not considered
then, the subtractor circuit is called “Half subtractor.”

(a)Logic diagram (b) Function Table

Figure 1.29: Block diagram of Subtractors

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On the other hand, if the borrow output from the previous stage
is also consideredfor subtraction, along with the two input digits then, the
subtractor circuit is called “Fullsubtractor.”

I. ADDER CIRCUITS:
(a) HALF-ADDER:
Function Table Design:

Figure 1.30: Function table and K-map for Half adder

(i) Realizationusing basic gates:

Figure 1.31: Logic diagram of Half-Adder using basic gates

Note: To design the circuit shown in Figure 1.3(a), simplify the function
table in Figure 1.3(b) using K-map and implement the simplified expression
using the required logic gates.
(ii) Realization using NAND gates:

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Figure 1.32: Logic diagram of Half-Adder using NAND gates

(b) FULL-ADDER:
Function Table Design:

Figure 1.33: Function table and K-map for Full adder

(i) Realizationusing basic gates:

Figure 1.34:Logic diagram of Full-Adder using basic gates

(ii) Realization using NAND gates:

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Figure 1.35(a): Logic diagram of FA using NAND (7400) gates

Figure 1.35(b): Logic diagram of FA using NAND (7410) gates

II. SUBTRACTOR CIRCUITS:
(a) HALF-SUBTRACTOR:
Function Table Design:

Figure 1.36: Function table and K-map for Half-Subtractor

(i) Realization using basic gates:

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Figure 1.37: Logic diagram of Half-Subtractor using basic gates

(ii) Realization using NAND gates:

Figure 1.38: Logic diagram of Half-Subtractor using NAND gates

(b) FULL-SUBTRACTOR:
Function Table Design:

Figure 1.39: Function table and K-map for Full-Subtractor

(i) Realization using basic gates:

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Figure 1.40: Logic diagram of Full-Subtractor using basic gates

(ii) Realization using NAND gates:

Figure 1.41: Logic diagram of Full-Subtractor using NAND gates

III. Multiple bit Adders:
(i) PARALLEL ADDERCIRCUITS:
(a) 4-bit Parallel Adder:

Figure 1.42: Logic diagram of 4-bit parallel adder

(b) N-bit Parallel Adder:

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Figure 1.43: Logic diagram of N-bit parallel adder

(c) 4-bit Parallel Adder/Subtractor:
20.(i) Design of Adder/Subtractor:

Soln:
Figure 1.44: Parallel adder/subtractor

Simplification results in the following expressions;

Xi = Ai, Yi = Bi⊕ S, and Cin = S. Realizing these expressions in a parallel
adder results in a parallel adder/subtractor shown in Figure 1.12.

Figure 1.45: Logic diagram of parallel adder/subtractor

(ii) 4-bit Parallel Adder/Subtractor using IC-7483:

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Figure 1.46: Parallel adder/subtractorusing IC-7483

(d) N-bit Parallel Adder/Subtractor:

Figure 1.47: Logic diagram of N-bit parallel adder/subtractor

(ii) SERIAL ADDERS:
- - - - - - Assignment - - - - - -
IV. DECIMAL ADDER:

Figure 1.48: Blockdiagram of BCD adder

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(a) 4-bit Decimal Adder:

CO = C4 + F4F3 + F4F2. . . . . . . . . . . Eq. 1.1

Figure 1.49: Logic diagram of BCD adder

(b) N-digit Decimal Adder:
V. FAST ADDERS:- - - - - - Assignment - - - - - -
(a) Ripple Carry Adder: a parallel adder
(b) Carry Look-ahead Adder
(c) Carry Save Adder, etc.
VI. MULTIPLIER CIRCUITS:

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Figure 1.50:Block diagram of Binary Multiplier

(i) 2 x 2 Multiplier circuit:

Figure 1.51: Logic diagram of 2 x 2 Binary Multiplier

(ii) 4 x 3 Multiplier circuit:

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Figure 1.52: Logic diagram of 4 x 3 Binary Multiplier

(iii) 4 x 4 Multiplier circuit:

Figure 1.53 (a): A 4 x 4 Binary Multiplier

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Figure 1.53 (b): A 4 x 4 Binary Multiplier

VII. MAGNITUDE COMPARATORS:

A comparator is a special combinational circuit designed to compare
relative magnitudes. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determines their relative magnitude.
The outcome of the comparison is specified by 3 binary variables that
indicate whether A >B or A < B or A = B.

(i) 1-bit comparator:

(a) Function Table (b) Karnaugh Map

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Figure 1.54: Logic diagram of 1-bit Magnitude Comparator

Figure 1.55:Circuit diagram of 1-bit Magnitude Comparator

Output Expressions:

Y1 = A  B  A B Y2 = A  B  A B Y3 = A  B  A B  A B

(ii) 2-bit comparator:

(a) Function Table (b) Karnaugh Map

Figure 1.56: Logic diagram of 2-bit Magnitude Comparator

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OR

Figure 1.57:Circuit diagramof 2-bit Magnitude Comparator

(iii) 4-bit comparator:

(a) 4-bit Equality Comparator using Ex-Or gates

(b) 4-bit Magnitude Comparator

Figure 1.58:Circuit diagram of 4-bit Magnitude Comparator

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VIII. ENCODERS and DECODERS:

(i) ENCODERS

An encoder is a combinational circuit that performs the conversion of a

original message into a coded form. An encoder has a maximum of 2n inputs
and n outputs. Figure 1.59 shows the block diagram and the truth table of
the 4-to-2 encoder. From the truth table, it can be concluded that an
encoder actually performsdecimal-to-binary conversion.

Figure 1.59:Block diagram of 4-2 Encoder

In the encoder defined by table, it is assumed that only one of the four
inputs can be HIGH at any time. If more than one input is 1 at the same
time, an undefined output is generated. For example, if d3, and d2 are 1 at
the same time, both x0 and x1 are 1. This represents binary 3 rather than 1
or 2. Therefore, in an encoder in which more than one input can be active
simultaneously, a priority scheme must be implemented in the inputs to
ensure that only one input will be encoded at the output.

Figure 1.60: Logic diagram of 4-2 Encoder

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(a) Priority Encoder:

A 4-to-2 priority encoder may be designed assuming that inputs

with higher subscripts have higher priorities. This means that d 3 has
the highest priority and d0 has the lowest priority. Therefore, if d0 and d3,
become one simultaneously, the output will be 11. The truth table of the 4-
to-2 priority encoder is shown in Figure 1.61 shows the function table, logic
diagram and the K-maps of the 4-to-2 priority encoder.

(a) Function table (b) Logic diagram

(c) K-maps
Figure 1.61:A 4-2 Priority Encoder
Output Expressions:

x1 = d2 + d3 x0 = d3 + d3 d2‟ v = d0 + d1 + d2 + d3

(ii) DECODERS

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A decoder is a logic circuit that performs the reverse operation of an

encoder.An n-bit binary number provides 2n minterms or maxterms. For
example, a 2-bit binary number will generate 4 (22) minterms or
maxterms. A decoder is a combinational circuit , when enabled, selects one
of 2n minterms or maxterms at the output based on the input
combinations. However, a decoder sometimes may have less than 2n
outputs. For example, the BCD to seven-segment decoder has 4 inputs and
7 outputs rather than 16 (24) outputs. The block diagram of a 2-to-4
decoder is shown in Figure 1.62. In the truth table, the symbol x is the don‟t
care condition, which can be 0 or 1. Also, E = 0 disables the decoder. On the
other hand, the decoder is enabled when E = 1. For example, when E = 1,
x1= 0, x0 =0, and the output d0 is HIGH while the other outputs d1, d2, and
d3, are zero. Note that
Therefore, the 2-to-4 line decoder outputs one of the four minterms
of the two input variables x1 and x0 when E = 1. In general, for n inputs,
the n-to 2ndecoder when enabled selects one of 2n minterms or maxterms at
the output based on the input combinations. The decoder actually provides
binary to decimal conversion operation. Using the truth table of Table 4.8,
a logic diagram of the 2-to-4 decoder can be obtained as shown in Figure
4.16. Large decoders can be designed using small decoders as the
building blocks. For example, a 440- 16 line decoder can be designed using
five 2-to-4 decoders as shown in Figure 1.62.Commercially available
decoders are normally built using NAND gates rather than AND gates
because it is less expensive to produce the selected decoder output in its
complement form. Also, most commercial decoders contain one or more
enable inputs to control the circuit operation. An example of the
commercial decoder is the 74HC138 or the 74LS138. This is a 3-to-8
decoder with three enable lines G, , G,, , and G. When G, = H, G,, = L
and G,, = L, the decoder is enabled. The decoder has three inputs, C, B,

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and A, and eight outputs Yo, Y,, Y,, ..., Y,. With CBA = 001 and the
decoder enabled, the selected output line Y, (line 1) goes to LOW while the
other output lines stay HIGH.

Figure 1.62: Logic diagram of a 2-4 decoder

Figure 1.63: Logic diagram of a 3-8 decoder

Standard MSI decoders:

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(a) Logic diagram (b) Pin diagram

(c) Function table

Figure 1.62: Logic diagram of 3-8 decoder IC-74LS138

Figure 1.63: A 4-16 decoder implementation using 2-4 decoder

21. Realization of Full adder-using Decoder (IC 74139):

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Figure 1.64 (a): Full adder using the 2x4 Decoder IC-74139

Figure 1.64 (b): Full adder using the 3x8 Decoder IC-74138
22. Realization of Full Subtractor-using Decoder (IC 74139):

Figure 1.65: Full subtractor using the 2x4 Decoder IC-74139

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23. Realization of 3-bit Binary to Gray code converter using IC-

74139:

Figure 1.66: 3-bit Binary to Gray code converter using IC- 74139
G0 =  m( 1,2,5,6)G1 =  m(2,3,4,5) G2 =  m(4,5,6,7)G2 = B2
24. Realization of BCD to Excess-3 code converter using IC- 74139:

Figure 1.67: 3-bit BCD to Excess-3 code converter using IC- 74139
E0 =  m (0,2,4,6,8) E1 =  m (0,3,4,7,8)
E2 =  m (1,2,3,4,9) E3 =  m (5,6,7,8,9)

IX. MULTIPLEXERS and DE- MULTIPLEXERS:

(i) Multiplexers:

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Figure 1.68: A 2x1Multiplexer

Figure 1.69: A 4x1Multiplexer

Figure 1.70: A 4x1Multiplexer using 2x1Multiplexers

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An 8-to-1 multiplexer can be constructed from smaller multiplexers like

this:

Figure 1.71: A 8x1Multiplexer using 2x1and 4x1 Multiplexers

Another implementation of an 8-to-1 multiplexer using smaller multiplexers

Figure 1.72: A 8x1Multiplexer using 2x1and 4x1 Multiplexers

A 16-to-1 multiplexer can be constructed from five 4-to-1 multiplexers:

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Figure 1.73: A 16x1Multiplexer using 4x1 Multiplexers

25. Function implementation using 4x1 Multiplexers

Soln:

Figure 1.74: Function implementation using 4x1 Multiplexers

26. Function implementation using 4x1 Multiplexers

Soln:

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Figure 1.75: Function implementation

Realization of Full adder-using Multiplexer (IC-74153):

Figure 1.76: Full adder using the 4x1 Multiplexer IC-74153

Truth Tables:

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27. Realization of Full Subtractor-using Multiplexer (IC 74153):

Soln:

Figure 1.77: Full subtractor using the 4x1 Multiplexer IC-74153

28. Use a 74153 to implement: f(x1,x2,x3) = m(0,2,3,5)

Figure 1.78: Function implementation using the 4x1 Multiplexer IC-

74153

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F(A,B,C) = S m(0,1,3,6) = A‟B‟C‟ + A‟B‟C + A‟BC + ABC‟

= A‟B‟(C‟ + C) + A‟BC + ABC‟

Figure 1.79: Function implementation

(ii) De-multiplexer:

Given an input line and a set of selection lines, the de-multiplexer will direct
data from input to a selected output line.

An example of a 1-to-4 de-multiplexer

Figure 1.80: De-multiplexer

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