UNIT-5

FUNDAMENTALS OF
ELECTRONIC SCIENCE
 Difference between BJT and FET

BJT - Bipolar Junction Transistor FET – Field Effect Transistor

• Three terminal semiconductor • Three terminal semiconductor device
device. • Source (S), Gate (G), Drain (D)
• Emitter (E), Base (B), Collector (C) • Voltage controlled device
• Current controlled device • Unipolar device – The current is
• Bipolar device –. The current is carried by only one type of charge
carried by both electrons and holes particles, either electrons or holes.
• Low i/p impendence • High I/P impedance
• Noise generated is high • Noise generated is low
• Size big • Size small
• Transconductance is high • Lower than BJT
Applications: Applications:
• As switch - saturation & cutoff region • As switch – Ohmic & Cutoff region
• As amplifier - Active region • As Amplifier – Saturation region
Classification of FET
Symbols of BJT and FET

BJT 

FET 
 Construction of N-channel JFET

• Major part of the structure is n- type

meterial.
• Top of the n-type channel Is
connected through an ohmic contact
to a terminal Reffered to as drain(D).
• As lower end Connected through an
ohmic contact to a terminal Reffered
as source (S).
• P-type meterials connected to gether
and taken as terminal gate(G).
• JFET has two pn junctions under no
bias condition.
Operation of n – Channel JFET
Con…
• In JFET, the p-n junction b/w gate and source is always kept in reverse
biased condition, thus the p-n junction extremely small, practically zero;
the gate current in JFET is often neglected and assumed to be zero.
• Voltage VDD is applied b/w D and S.
• Due to the applied voltage, the majority carriers (e-) started flowing
from S  D. The flow of e- makes the drain current, ID. The width of this
channel can be controlled by varying the gate voltage.
• Fig. a, n-channel with the gate directly connected to the source
terminal. Drain voltage (VGS= 0) is applied, a current flows Is to ID. Received
o/p maximum (10 mA) ID current, due to high width of n-channel region
(size of n-channel is high).
• Fig. b, Drain voltage (VGS = -1) is applied, Received o/p reduced ID
current (7 mA), due to increasing width of depletion region.
• Fig. c, Drain voltage (VGS = -3) is applied, Received o/p minimum ID
current (2 mA), due to increased width of depletion region.
• The Gate to Source voltage controls the current flowing channel and
hence FET is called as voltage controlled current source.
Drain Characteristics of n-channel JFET

Experimental setup 
• Further, increase in VDS does not increase the drain current ID. ID
approaches the constant saturation value. The voltage VDS at which the
current ID reaches to its constant saturation level is called “Pinch-off
Voltage”, VP.
• If we further exceed VDS, the voltage will be reached at which the gate-
channel junction breaks down, due to avalanche effect. At this point the
drain current increases very rapidly, and the device may be destroyed.
• In the Ohmic region, the drain current ID varies with VDS and the JFET is
said to behave as voltage variable resistance.
• In the saturation region, the drain current ID remains fiarly constant
and does not vary with VDS.
 Transfer Characteristics of n-channel JFET
• The relationship between the drain current ID and
gate to source voltage VGS is non-linear. This
relationship is defined by Shockely’s equation,
2
 V 
I D  I DSS 1  GS 
 VP 

• The squared term of the equation will result in a

non-linear relationship between ID and VGS
producing a curve that grows exponentially with
decreasing magnitudes of VGS. From equation we
can also write,
 ID 
VGS  VP 1  
 I DSS 

• Point A at the bottom end the curve on the VGS axis represents VGS(off), and
point B at the top end of the curve on the ID axis represents IDSS (max. current
at VGS = 0). Thus, this curve shows the operating limits of a JFET.
These are, ID = 0 when VGS = VGS(off)
ID = IDSS when VGS = 0
Construction of p – Channel JFET
Operation of p – Channel JFET

• The p-channel JFET is constructed in exactly the same manner as the n-

channel JFET but with reverse of the p- and n-type materials.
• All current directions and voltage polarities are reversed.
• For, VGS = 0, channel width is maximum. By increasing +ve gate to
source (VGS), the channel width is reduced.
Drain Characteristics of p-channel JFET
Transfer Characteristics of p-channel JFET
Characteristics parameters of JFET
• Transconductance (gm)
• I/P resistance and capacitance
• Drain to source resistance (rd)
• Amplification factor (µ)
• Power Dissipation (PD)
Applications of JFET

• JFET has high I/P impedance and low O/P impedance they are
used as a buffer in measuring instruments.
• Low noise, they are used in RF amplifier in FM tuners and in
communications equipments.
• FET are used in mixer circuits in FM and TV receivers, and
communication equipments.
• Low frequency drift they are used in oscillations.
• FET are used in low frequency amplifiers, and digital amplifiers.
 Single Electron Transistor (SET)
Single electron phenomena:

Condition for coulomb blockade where,

C – Capacitance of QD
T – Temperature of the system
Wc – Charging energy
Single Electron Tunneling
Tunneling is the way the electrons cross both the physical barriers and
the energy barriers separating a quantum dot from the material that
surrounds it.
• Tunneling is the quantum mechanical phenomena where particle
through the barrier.
• Tunneling is possible due to wave like properties.
Single Electron Transistor
Definition
• SET is three-terminal switching devices which can transfer electrons from
source to drain one by one.
• The purpose of SET is to control the tunneling of electron into or from the
Quantum Dot (QD).

Structure of SET is similar to FET (Field Effect Transistor)

• SET has tunneling junction instead of PN junction
• SET has QD in the place of channel region of FET
Construction & working
Therefore, no. of electrons in the quantum dot is controlled using the gate
voltage.
Advantages
• The fast information transfer
• No wire is needed between arrays.
• This can be used for the next generation quantum computer.
Limitations
• In order to operate SET circuit at room temperature
• It is very hard to fabricate
Applications
• The main fields of application of SET is used in sensor technology
and digital electronic circuits.
• It can used by AND or NOR gates and Data storage.
 Spintronics
Spintronics – Spin Based Electronics
Definition:
• Study of the intrinsic spin of the
electron and its associated magnetic
moment, in addition to its fundamental
electronic charge, in solid state devices.
• Spintronics uses electron spins in addition to or in place
of the electron charge.
• The rotational moment creates a small magnetic field.
• Key concept is controlling the spin of electrons.
• Spintronics is intrinsic spin of the electron + its associated
magnetic moment + its fundamental electronic charge.
Principle
• Spintronics is based on the spin of electrons rather than its
charge.
• Every electron exists in one of the two states- spin up and spin
down with spins either positive half or negative half.
• In other words, electrons can rotate either clockwise or
anticlockwise around its own axis with constant frequency.
• The two possible spin states represent ‘0’ and ‘1’ in logical
operations.
Applications
• Giant magnetoresistance (GMR) in various fields.
• Spin valve.
• Solid state non volatile memories.
• Quantum Information processing and quantum computation.
• Spin based transistors.
 Electonic Devices Vs Spintronic Devices

Sl. No.
Electronic Devices Spintronic Devices
1 Power failure problem No power failure problem

2 Boot up waitin problem No Boot up waitin problem

3 More power consumption Less power consumption

4 Normal speed Faster speed

5 Cheaper Costlier

6 Classical property Quantum Property

7 Less Compact More Compact

Based on properties of charge Based on intrinsic property of spin
8.
ofelectron ofelectron
 Advantages of Transistorized Logic Gates

The main advantages of logic gates built using

transistors can be summarized as given below:
• Transistors are cheaper than ICs.
• Transistorized logic gates can be operated with
voltages as low as 1.5V, while the IC
counterparts need a minimum of 3 V.
• A transistorized logic gate can be customized to
control heavier loads, which an IC based logic
gate cannot do
Transistor Logic NOT Gate
A simple single input logic NOT gate can be constructed using a RTL Resistor-transistor
switch as shown below with the input connected directly to the transistors base. The
transistor must be fully-ON, or fully-OFF for the inverted output to be present at Q.
For the OR logic, the transistors are in parallel and the output is driven high if either of
the transistors is conducting.
For the AND logic, the transistors are in series and both transistors must be in the
conducting state to drive the output high
Logic NOR Gate
 Logic NAND Gate
The Logic NAND Gate is a combination of a
digital logic AND gate and a NOT gate
connected together in series
we can observe that the XOR gate produces a HIGH output when the
inputs A and B are different, and a LOW output when the inputs are the
same.
we can observe that the XOR gate produces a HIGH output when the inputs A
and B are different, and a LOW output when the inputs are the same.
XOR GATE USING TRANSISTOR
 Karnaugh map (K-map ) SoP and PoS forms

General Introductions:
“Boolean algebra is a system of mathematical logic. It differs
from both ordinary algebra and the binary number system”

DeMorgan’s theorems:
DeMorgan suggested two theorems that form an important part
of Boolean algebra. In equation form becomes.

1. AB  A  B :
The complement of product
is equal to the sum of the
complement.
2. A  B  A  B :
The complement of a sum is equal to the product of the
complement.
Karnaugh map (K-map)
“A K-map is a pictorial form of truth table, in which the map
diagram is made up of squares, with each squares (cells)
representing one minterm or Maxterm of the function”

 minterm  SOP
Example:  Maxterm  POS
• The K-map method, gives us a systematic approach for
simplifying a Boolean expressions.

• The map method, 1st proposed by Veitch and modified by

Karnaugh, hence, it is known as the Veitch diagram or Karnaugh
map.

Variables:
The basis of this method is a graphical chart known as K-map. It
contains boxes called cells. Each of the cell represents one of the 2n
possible products that can be formed n variables.

• 21 = 2 cells
• 22 = 4 cells
• 23 = 8 cells
• 24 = 16 cells
Variables with K-maps
1, 2, 3 and 4-Variable K-maps with product terms
1, 2, 3 and 4-Variable K-maps with sum terms