03-02-2024

Micro Processor
ONE SHOT Unit 6

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Interrupts and Identifying Interrupts

• Interrupts and exceptions alter the normal program flow, in
order to handle external events, to report errors or
exceptional conditions.
• The difference between interrupts and exceptions is that
interrupts are used to handle asynchronous external events
while exceptions handle instruction faults.
• Interrupt is a mechanism by which an I/O device(hardware
interrupt) or an instruction (software interrupt) can suspend
the normal processor program execution and get itself
serviced.
• Interrupts are of two types:
1. Hardware Interrupts
2. Software Interrupts

Hardware Interrupts
• In this type of interrupt, physical pins are provided in the chip.
This interrupts are generated by changing the logiclevels on
the 80386's interrupt pins. 80386 has two interrupt pins:
1. NMI (Non Maskable Interrupt)
2. INTR

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Software Interrupts
• A program can generate a software interrupt via an INT“N”
instruction, the processor treats software interrupts as
exceptions. For example INT0 instruction can be used to
send execution to a divide by zero interrupt service routine.
• With the help of these software interrupts we can call the
routines from different programs in the system. For example:
BIOS.

Exceptions:
• Internally generated errors produce an interrupt for
microprocessor referred as “Exception" by the engineers.
• Every interrupt is assigned a type code" that identifies it to the
CPU.
• There could be two sources for exceptions:
1. Processor detected: These are further classified as faults, traps, and
aborts.
2. Programmed: The instructions INT0, INT 3, INT n, and BOUND can
trigger exceptions. These instructions are often called "software
interrupts", but the processor handles them as exceptions.
• The NMI and the exceptions recognized by the processor are
assigned predetermined identifiers in the range 0 through 31.
• The identifiers of the maskable interrupts are determined by
external interrupt controllers and communicated to the processor
during the processor's interrupt-acknowledge sequence.

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Enabling and Disabling Interrupts

• The processor services interrupts and exceptions only between the end of one
instruction and the beginning of the next.
• NMI Masks Further NMls
• While an NMI handler is executing, the processor ignores further interrupt signals at
the NMI pin until the next IRET instruction is executed.
• IF Masks INTR:
• The IF (interrupt-enable flag) controls the acceptance of external interrupts via the
INTR pin. When IF=0 INTR interrupts are inhibited;
• The instructions CLI and STI alter the setting of IF. These instructions may be
executed only if CPL < IOPL.
• RF Masks Debug Faults:
• This permits debug faults to be raised for a given instruction at most once, no matter
how many times the instruction is restarted.
• MOV or POP to SS Masks Some Interrupts and Exceptions:
• If an interrupt or exception is processed, after SS has been changed but before ESP
has received the corresponding change, the two parts of the stack pointer SS:ESP are
inconsistent
• To prevent this situation, the 80386, after both a MOV to SS and a POP to SS
instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the
instruction boundary. page fault and general protection fault may still occur.

Exception Conditions
• Exceptions are classified as:
• Faults are exceptions that are detected and serviced before the
execution of the faulting instruction. A fault would occur in a
virtual memory system, when the processor referenced a page or
a segment which was not present. The operating system would
fetch the page or segment from disk, and then the 80386 would
restart the instruction.
• Traps are exceptions that are reported immediately after the
execution of the instruction which caused the problem. User
defined interrupts are examples of traps. Instruction is not
restarted
• Aborts are exceptions which do not permit the precise location
of the instruction causing the exception to be determined. Aborts
are used to report severe errors, such as a hardware error, or
illegal values in system tables. Program is terminated

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Processing (Handling) an interrupt

1. Whenever an INT instruction is sensed, the 80386 microprocessor
will first push the flags on the Stack.
2. The processor will clear the trace flag and the interrupt enable flag.
3. Then the contents of CS and IP are pushed onto the Stack.
4. An 8-bit vector is supplied to the 80386 which identifies the
appropriate entry in the interrupt table. The table contains the
starting address of the interrupt service routine..
5. The user supplied interrupt service routine is executed.
6. Finally, when an IRET instruction is executed the old processor state
is restored and program execution resumes at the appropriate
instruction.
The 8-bit interrupt vector is supplied to the 80386 in several different
ways: exceptions supply the interrupt vector internally; software INT
instructions contain or imply the vector; maskable hardware interrupts
supply the 8-bit vector via the interrupt acknowledge bus sequence.
Non-Maskable hardware interrupts are assigned to interrupt vector 2

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IDT Gate Descriptors

Priority among Simultaneous Interrupts and

Exceptions
• If more than one interrupt or exception are pending at an instruction
boundary, the µP services one of them at a time.
• µP has its own priority of interrupts so it services higher priority
interrupts first.
• When NMI and maskable INTR are both recognized at the same
instruction boundary, the 80386 invokes the NMI service routine first.
• If, after the NMI service routine has been invoked, maskable interrupts
are still enabled, then the 80386 will invoke the appropriate interrupt
service routine.

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Interrupt Tasks and Interrupt Procedures

• Just as a CALL instruction can call either a procedure or a
task, so an interrupt or exception can "call" an interrupt
handler that is either a procedure or a task.
• Interrupt Procedures:
• An interrupt gate or trap gate points indirectly to a procedure which
will execute in the context of the currently executing task.
• The selector of the gate points to an executable-segment descriptor
in either the GDT or the current LDT.
• The offset field of the gate points to the beginning of the interrupt
or exception handling procedure.
• Interrupt Tasks:
• A task gate in the IDT points indirectly to a task, i.e. The selector of
the gate points to a TSS descriptor in the GDT.
• Handling an interrupt with a separate task offers two advantages:
1. The entire context is saved automatically.
2. The interrupt handler can be isolated from other tasks by giving it a separate
address space, either via its LDT or via its page directory.

Difference between Microprocessor and Microcontroller

Microprocessor Microcontroller
Microprocessor is suited to processing Microcontroller is suited to control of I/O
information in computer systems devices.

Data and programs are stored in same memory Data and program memory are separate.

Most of them do not have power saving features. Most of them Offer power-saving mode.
High Processing capability Low processing capability
uP is designed to perform general-purpose uC is designed for specific applications
computing tasks.

requires additional components like memory, I/O has all the necessary peripherals and
devices and other peripherals memory integrated into a single chip.

µPs are relatively expensive µCs are relatively cheaper in cost.

High power consumption Low power consumption
Big size system Compact size systems

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Architecture of typical Microcontroller

Architecture of typical Microcontroller

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Characteristics of microcontrollers
• It is impossible to connect anything to the pins of the
microcontroller without knowing the input current requirement
for an input pin and the output current drive capability for an
output pin.
• Input Characteristics : The input characteristics of these
microcontrollers are compatible with all the standard logic
components available today. The input current levels are very
small because the inputs are the gate connections MOSFETs and
represent only leakage currents. But µCs can easily sink a
significant amount of current from the input pins.
• Output Characteristics: The voltage levels for logic 0 and 1 are
compatible with that of most standard logic families.
• 0= -0.5(min) to 0.2Vdd-0.1(max)
• 1= 2.4 (min) to 0.9Vdd
• The output current levels for most µCs are significantly low (~2mA) but
some µCs (like PIC18FXX) can provide upto 25mA from some of their
output pins.

Application of Microcontrollers
• Consumer Electronics Products: Toys, Cameras, Robots,
Washing Machine, Microwave Ovens etc.
• Instrumentation and Process Control: Oscilloscopes, Multi-
meter, Leakage Current Tester, Data Acquisition and Control
etc.
• Medical Instruments: Digital Thermometer, BP monitor
• Communication: WIFI-Routers, mobile phones, wireless etc
• Office Equipment: Printers, Telephones, Fax machines
• Multimedia Application: IPODs, MP3 players, small video
players.
• Automobile: ….

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Pyq
• Interrupt identification
• Source and enabling, disabling interrupts
• Interrupt handling procedure
• Procedure as an interrupt handler
• Faults, traps aborts
• IDT
• Interrupt gate and trap gate descriptor
• Int0- int 4
• General detect fault
• When does a Page fault occur.
• Difference b/w mc and mp
• Architecture of mc
• Applications of mc

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