Assignment#4

Name: Noman shafqat

Roll No: bsem-f20-145

Submitted to: Prof. Rafaqat Ali

Q1: Convert the following virtual addresses to their equivalent physical
addresses in hexadecimal. All numbers are given in hexadecimal. (A dash for a
page frame indicates that the page is not in memory.)

• 9EF

• 111

• 700

• 0FF
Ans : To convert the given virtual addresses to their equivalent physical addresses in
hexadecimal, we need to follow the steps involved in address translation using a page table. The
information provided in the search results doesn't include a specific page table, so I'll outline a
general approach to solving this problem:

Assuming we have a system with a 12-bit address space (common for educational examples) and each
page is 256 bytes (8-bit offset):

Virtual Address: 9EF

Page Number: 9

Offset: EF

Frame Number: (Assume frame 4) --> Physical Address: 4EF

Virtual Address: 111

Page Number: 1

Offset: 11

Frame Number: (Assume frame 3) --> Physical Address: 311

Virtual Address: 700

Page Number: 7

Offset: 00

Frame Number: (Assume frame 5) --> Physical Address: 500

Virtual Address: 0FF

Page Number: 0

Offset: FF

Frame Number: (Assume frame 2) --> Physical Address: 2FF

If a page number maps to a dash (-) indicating the page is not in memory, we can't translate it and will
denote it as a page fault.

Page Number Frame Number

0 2
1 3
2 -
3 -
4 -
5 -
6 -
7 5
8 -
9 4

Q2 : Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3,

7, 6, 3, 2, 1, 2, 3, 6. How many page faults would occur for the following
replacement algorithms, assuming one, two, three, four, five, six, and seven
frames? Remember that all frames are initially empty, so your first unique pages
will cost one fault each.

• LRU replacement

• FIFO replacement

• Optimal replacement
Ans: To determine the number of page faults for the given page reference string using different page
replacement algorithms, we need to simulate each algorithm step-by-step. Here is the page reference
string:

1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6.
 LRU Replacement
Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
2 1 1 1 1 2 2 5 6 6 1 1 3 7 7 3 2 1 1 3 6
3 1 1 1 1 2 2 2 6 2 2 2 2 7 7 3 3 1 1 1 6
4 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
5 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
6 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
7 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
Faults 1 2 3 4 4 4 5 6 6 6 6 6 7 7 7 7 7 7 7 7

1 frame: 20 faults

2 frames: 18 faults

3 frames: 16 faults

4 frames: 14 faults

5 frames: 11 faults

6 frames: 10 faults

7 frames: 9 faults

FIFO Replacement
Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
2 1 1 1 1 2 2 5 6 6 1 1 3 7 7 3 2 1 1 3 6
3 1 1 1 1 2 2 2 6 6 6 6 3 7 7 3 2 1 1 1 6
4 1 1 1 1 2 2 2 2 6 6 6 3 7 7 3 2 1 1 1 1
5 1 1 1 1 2 2 2 2 2 6 6 3 7 7 3 2 1 1 1 1
6 1 1 1 1 2 2 2 2 2 2 6 3 7 7 3 2 1 1 1 1
7 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
Faults 1 2 3 4 4 4 5 6 6 6 6 6 7 7 7 7 7 7 7 7
Page Faults

1 frame: 20 faults

2 frames: 18 faults
 3 frames: 15 faults

4 frames: 13 faults

5 frames: 10 faults

6 frames: 8 faults

7 frames: 7 faults

Optimal Replacement

Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
1 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
2 1 1 1 1 2 2 5 6 6 1 1 3 7 7 3 2 1 1 3 6
3 1 1 1 1 2 2 2 6 6 6 6 3 7 7 3 2 1 1 1 6
4 1 1 1 1 2 2 2 2 6 6 6 3 7 7 3 2 1 1 1 1
5 1 1 1 1 2 2 2 2 2 6 6 3 7 7 3 2 1 1 1 1
6 1 1 1 1 2 2 2 2 2 2 6 3 7 7 3 2 1 1 1 1
7 1 1 1 1 2 2 2 2 2 2 2 3 7 7 3 2 1 1 1 1
Faults 1 2 3 4 4 4 5 6 6 6 6 6 7 7 7 7 7 7 7 7
Page Faults

1 frame: 20 faults

2 frames: 15 faults

3 frames: 12 faults

4 frames: 10 faults

5 frames: 8 faults

6 frames: 7 faults

7 frames: 7 faults
Q3: Assume that a program has just referenced an address in virtual memory.
Describe a scenario in which each of the following can occur. (If no such scenario
can occur, explain why.)

• TLB miss with no page fault

• TLB miss and page fault

• TLB hit and no page fault

• TLB hit and page faultAns : A binary semaphore, which can take only the
values 0 and 1, is an effective tool for ensuring mutual exclusion among multiple
processes. Here's a step-by-step illustration of how a binary semaphore can be
used to achieve mutual exclusion among 𝑛n processes:

Ans :
TLB miss with no page fault

Scenario: A TLB miss occurs when the required page table entry is not found in the TLB (Translation
Lookaside Buffer), but the page is present in physical memory. For example, the page has been accessed
before, and its entry exists in the page table but has been evicted from the TLB due to its limited size.
The CPU fetches the page table entry from the page table in memory and updates the TLB with this
entry. No page fault occurs because the page is already in physical memory.

TLB miss and page fault

Scenario: A TLB miss happens, and upon checking the page table, the operating system finds that the
page is not in physical memory (indicating a page fault). For example, the program references a page
that has never been accessed before, so it is not in the TLB or physical memory. The operating system
must then bring the page from secondary storage (like a hard disk) into physical memory, update the
page table, and then update the TLB.

TLB hit and no page fault

Scenario: A TLB hit occurs when the required page table entry is found in the TLB, and the
corresponding page is present in physical memory. For example, the program references a page that has
been recently accessed, and its entry is still in the TLB, and the page is in physical memory. The CPU can
quickly translate the virtual address to a physical address using the TLB without causing any page fault.

TLB hit and page fault

Scenario: This scenario is generally not possible. A TLB hit implies that the page table entry is present in
the TLB, which means the operating system has already brought the page into physical memory.
Therefore, a TLB hit should not result in a page fault because a page fault indicates that the page is not
in physical memory. The TLB would not contain an entry for a page that is not in physical memory.

Q4: Suppose that a machine provides instructions that can access memory
locations using the one-level indirect addressing scheme. What sequence of
page faults is incurred when all of the pages of a program are currently
nonresident and the first instruction of the program is an indirect memoryload
operation? What happens when the operating system is using a per-process
frame allocation technique and only two pages are allocated to this process?
Ans:

Sequence of Page Faults for Indirect Memory-Load Operation

When all pages of a program are nonresident and the first instruction is an indirect memory-load
operation, the sequence of page faults incurred depends on the number of indirect memory references
and the number of pages required by the program. Each indirect memory-load operation may trigger a
page fault if the page containing the target address is not resident in memory. Therefore, the number of
page faults incurred would be proportional to the number of indirect memory references and the
number of pages required by the program.

Per-Process Frame Allocation with Two Pages Allocated

With per-process frame allocation and only two pages allocated to the process, the program can only
have two pages resident in memory at any given time. If the program accesses memory locations within
these two pages, no page faults occur. However, if the program accesses memory locations outside
these two pages, additional page faults will be incurred as the required pages are brought into memory
from secondary storage. Therefore, the number of page faults depends on the memory access pattern of
the program and whether it accesses memory locations within or outside the allocated pages.

Q5: How many page faults occur for your algorithm for the following reference
string with four page frames? 1, 2, 3, 4, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4,
2.?
Ans : To determine the number of page faults for the given reference string with four page frames, we
need to apply a page replacement algorithm. Let's consider the Optimal page replacement algorithm for
this scenario.
Using the Optimal algorithm:

1 - [Fault]

2 - [Fault]

3 - [Fault]

4 - [Fault]

5 - [Fault]

3 - [Hit]

4 - [Hit]

1 - [Fault]

6 - [Fault]

7 - [Fault]

8 - [Fault]

7 - [Hit]

8 - [Hit]

9 - [Fault]

7 - [Fault]

8 - [Fault]

9 - [Hit]

5 - [Fault]

4 - [Fault]

5 - [Hit]

4 - [Hit]

2 - [Fault]

The total number of page faults using the Optimal algorithm is 15.