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1 1

2
Compal Confidential 2

ADL-P MB Schematic Document CPU Part Number

I5 ES sample
I5ES@
UC1
S IC FJ8071504587817 QXZR J0 1G BGA S
SA0000EMV00
I5 pre-QS sample
I5preQS@

LA-M241P
UC1
S IC FJ8071504785803 QYY1 K0 2.5G BGA 1744 S
SA0000F4F00
I7 pre-QS sample
I7preQS@
UC1
S IC FJ8071504786105 QYY4 K0 2.3G BGA 1744 S
SA0000F2X30

I9 pre-QS sample
I9preQS@
UC1
3 3

Rev:1A
S IC FJ8071504786408 Q00G K0 2.5G BGA 1744 S
SA0000F3W 00

I7 sup-QS sample
Q07G@
PCB Part Number VGA Part Number UC1
S IC FJ8071504786106 Q07G L0 2.3G BGA S
PCBV0@ SA0000F7I00

2021.12.14
ZZZ E3MP@
PCB 3MC LA-M241P REV0 MB S UV1
DAC0002M000 S IC GN20-E3-A1 FCBGA 2714 GPU ABO !
I9 sup-QS sample
SA0000E1930 Q07K@
UC1
PCBV1@ E6QS@ S IC FJ8071504786411 Q07K L0 2.5G S
ZZZ UV1 SA0000F8F00
PCB 3MC LA-M241P REV1 MB S IC GN20-E6-A1 FCBGA 2714 GPU S
DAC0002M010 SA0000EQ310
I7 MP sample
E8QS@ SRLD1@
PCBV1A@ UV1 UC1
ZZZ S IC GN20-E8-A1 FCBGA 2714 GPU S S IC FJ8071504786106 SRLD1 L0 2.3G ABO !
PCB 3MC LA-M241P REV1A MB SA0000EQ400 SA0000F7I40
DAC0002M01A

E6MP@
I9 MP sample
UV1 SRLD4@
4
S IC GN20-E6-A1 FCBGA 2714 GPU ABO ! UC1 4
SA0000EQ340 S IC FJ8071504786411 SRLD4 L0 2.5G ABO !
SA0000F8F30
E8MP@
UV1
S IC GN20-E8-A1 FCBGA 2714 GPU ABO !
HDMI Royalty SA0000EQ420
Compal Secret Data
Security Classification
2020/09/25 2021/12/31 Title
Compal Electronics, Inc.
45@
Issued Date Deciphered Date
ZZZ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
HDMI LOGO AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
RO0000003HM DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 1 of 112
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Tiger Lake H Block Diagram Alden lake P USB TypeA- JUSB1 page 71 USB TypeA - JUSB2
- USB3 GEN2
page 72 Finger print JFP1page 66

File Name : LA-L211P 943pin BGA

- USB3 GEN2
- U3 Redriver(GL9901NT)
- U3 Retimer(PS8811)
- U2 Redriver((TUSB212)
- USB2
- USB port9
HDA Codec page 56 - USB3 Port 1 - USB3 Port 2
Release Date: 2020/09/24 - ALC287-CG
HD Audio - USB2 Port 1 - USB2 Port 2

USB3 redriver page 71 USB3 retimer page 72 USB Chargerpage 72 USB2 redriverpage 66
1
Genesys GL9901NT Parade PS8811 SILEGO SLGC55544 TI TUSB212 1

Speaker page 56 DMIC page 38 Audio Jack page 56

USB2 redriverpage 72 Port9
- On Camera - UAJ
USB3 Port1 Port2 TI TUSB212
LPDDR5 315 ball page 21~24
ConceptD
Port1 Port3
VDDQ:0.5V Memory BUS USB2
Port5
VDD1:1.8V Memory
VDD2:1.065V Dual Channel CNVi eye tracker
1R: 5200Mhz page 60
2R: 4800Mhz

CMOS Camera - Jedp1 page 38 Wire less Lan page 53

3D lengs page 60
- on board 1216 package Port6
- USB2 - Killer 1670S
180pin GDDR6- X8 E3/E5/E7&E6/E8 - U2 Redriver((TUSB212) - PCIE Gen1
- USB2 Port7 PCIe 1.0 - PCIE Port4
GDDR_A page 32 GDDR_C page 34
SSD - JSSD1 2.5GT/s - USB2 Port10
- CNVi per key keyboard page 63
Port8
PCIEX4_A USB2 redriver page 38
CPU PCIE
GDDR_B page 33 GDDR_D page 35 TI TUSB212
- PCIE Gen4
- PCIEX4 A Port0-3 page 68 Port7 Port10
2 2
Port2 Port4

Memory BUS SPI ROM SSD - JSSD2 TypeC - JTYPEC2 page 43 TypeC - JTYPEC2 page 46

Dual Channel - Thunderbolt 4

16 Mb - Thunderbolt 4 - Two burnside bridge(JHL8040R)
PCIEX4_B - One burnside bridge(JHL8040R)
page 28 - U2 Redriver((TUSB212)
- PD in - PD in
SPI - PCIE Gen4 - TCP Port 0 - TCP Port 2
VGA - PCIEX4 B Port0-3 page 69 - USB2 port 4 - USB2 port 3

NV GN20 - E6/E8 TBT4 retimer page 42 SPI ROM TBT4 retimer page 44 SPI ROM USB2 redriverpage 46
PCIEX8 Intel JHL8040R 64 Mb Intel JHL8040R 64 Mb TI TUSB212
PEX
PD controller page 43 ROM TBT4 retimer page 45 SPI ROM
DDI
IFPC eDP - Jedp1 page 38 TI PS65992DAE 256 kb Intel JHL8040R 64 Mb
- DDS(PS8461) PD controller page 46 ROM
- Intel DDIA port
IFPC IFPD - NV IFPD port DDS TI PS65992DAE 256 kb
MiniLED
OLED
3 HDMI - JHDMI1 eDP Mux and retimer page 3
LAN - JRJ1 3

Port0 Port2
TCP port
- HDMI 2.1 PARADE PS8461-A3 - Killer Lan
- NV IFPC port - PCIE Gen3
- HDMI retimer(PS8419) SD Card - JCR1 page 70 - PCIE redriver(GL9903)
page 38 DDIA - PCIE Port12 page 51
PCH PCIE
- SD 7.0
HDMI retimer EC controller page 58
- PCIE Gen3
LAN controller page 51
- PCIE Port10
PARADE PS8419 eSPI BUS ConceptD - Realtek RTS5261
- ENE 9052 LAN(GbE) KillerE3100G
I2C Light sensor page 60 SD controller page 70
Port0
Realtek RTS5261
Extend GPIO page 59 Gyro page 60
Port2
- ENE KC3810
Touch screen page 38
Port3

EMR page 60
Port4 Port10 Port12 Port4
Int.Key Board page 63

4 4
- 3 zone keyboard: SPI
KB matrix:9052, Touch Pad page 66
Port1
BL:TLC59116 SPI0
Sub Board -ConceptD keyboard SPI ROM
KB matrix:9052,
BL:normal 5V 128 Mb page 9
Turbo_key
TPM page 66 Security Classification
2020/09/25
Compal Secret Data
2021/12/31 Title
Compal Electronics, Inc.
LS_L211P LED driver page 62
Issued Date Deciphered Date
TGL-H Block Diagram
NPCT750AABYX THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
ENE TLC 599116 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
HH67A MB LA-M241P 0.1

Date: Friday, December 24, 2021 Sheet 2 of 112

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Board ID Table for AD channel

Vcc 3.3V +/- 1% SOC SMBUS Address Table
100K +/- 1% Address (8bit)
Ra Net Name Power Rail Device Address (7 bit)
Write Read
Board ID /PCB Revision Rb V AD_BID min V AD_BID TYP V AD_BID Max EC AD3
Volante 0 --> 0.1 0 0V 0.300 V 0x00 - 0x13 SD028000080 NA
12K +/- 1% 0.354 V 0x14 - 0x1E SOC_SMBCLK +3VS
1 --> 1.0 0.347 V 0.36 V SD034120280 SOC_SMBDATA
15K +/- 1% 0.430 V 0x1F - 0x25 SD034150280 only PU no connect
2 -->1A 0.423 V 0.438 V to device NA
3 --> 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 SD034200280
4 --> 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A SD034270280 Re-Timer 1- UT4
1
5 --> 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 SD034330280 (Port0 右右) 1

6 --> 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54 SD034430280

7 --> 56K +/- 1% 1.169 V 1.185 V 0x55 - 0x64 SD034560280 SOC_SML0CLK Re-Timer 2- UT2
1.200 V SOC_SML0DATA +3VALW_PRIM (Port2 左右)
8 --> 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 SD034750280
9 --> 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 SD034100380 Re-Timer 3- UT7
Greenday 10 --> 130K +/- 1% 1.849 V 1.865 V 0x88 - 0x96 SD034130380 (Port2 左右)
1.881V
11 --> 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 SD034160380
2.185 V 0xA5 - 0xAF SD034200380 PD1(TPS65992DA)
12 --> 200K +/- 1% 2.200 V 2.215 V (Port0 右右) - UT36
240K +/- 1% 2.316V SOC_SML1CLK
13 --> 2.329V 2.343V 0xB0 - 0xB7 SD000001B80 SOC_SML1DATA +3VALW_PRIM
14 --> 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF SD00000G280 PD1(TPS65992DA)
15 --> 330K +/- 1% 2.521 V 2.533V 2.544 V 0xC0 - 0xC9 SD034330380 (Port2 左右) - UT38
16 --> 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 SD00000WM80
17 --> 560K +/- 1% 2.791 V 2.800 V 0xD5 - 0xDD SD034560380
18 --> 750K +/- 1% 2.905 V 2.912 V
2.808 V
2.919 V 0xDE - 0xF0 SD00000AL80 PCH I2C Address Table
Address (8bit)
19 --> NC 3.000 V 3.000 V 0xF1 - 0xFF NC I2C Port Power Rail Device Address (7 bit)
Write Read
BOM Structure Table Voltage Rails
Function Stuff Un-Stuff I2C_0_SCL
Power Plane Description S0 S0ix S4/S5 Pseudo-G3 I2C_0_SDA +3VS ALS
+19V_ADPIN Adapter power supply N/A N/A N/A N/A
+17.4V_BATT+ Battery power supply N/A N/A N/A N/A
+19VB AC or battery power rail for power circuit N/A N/A N/A N/A
+3VALW_PRIM
2 +VCC_CORE Core voltage for CPU ON OFF OFF OFF I2C_1_SCL 2

I2C_1_SDA Level shift to Touch Pad

+VCCIN_AUX CPU and PCH merged auxiliary power rail ON ON OFF OFF +3V_PTP
+1.8V_PROC +1.8V_PROC is the PCIE5 1.8V rail ON ON OFF OFF
+VCC_GT Graphic Power Rail ON OFF OFF OFF
+1.065V_MEM Processor Memory power rail ON ON OFF OFF I2C_2_SCL
I2C_2_SDA +3VS Gyro
+1.8V_PRIM_MCP TCSS/AGSH TypeC sub system / CPU analog power supply ON OFF OFF OFF
+1.8VALW_PRIM System +1.8V power rail ON ON ON* OFF
+1.8VS System +1.8VS power rail ON ON OFF OFF I2C_3_SCL
I2C_3_SDA +3VS Touch screen
+3VALW System +3VALW always on power rail ON ON ON* OFF
+3VLP +19VB to +3VLP power rail for Pseudo-G3 ON ON ON ON
+3VALW_DSW +3VALW power for PCH DSW rails ON ON ON* OFF
+3VALW_PRIM +3VALW power for PCH suspend rails ON ON ON* OFF
I2C_4_SCL
+3VS System +3VS power rail ON ON OFF OFF I2C_4_SDA +3VS EMR
+5VALW System +5VALW power rail ON ON ON* OFF
+5VS System +5VS power rail ON ON OFF OFF
+RTCVCC RTC power ON ON ON ON
+1.05V_PROC +1.05V_PROC is a gated power rail derived from
+1.05VO_OUT_FET. ON ON ON OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF
EC SMBUS Address Table
Address (8bit)
EC_SMBUS Port Power Rail Device Address (7 bit)
3
Write Read 3

SMBUS Port0 BAT 0x16

EC_SMB_CK0 +3VLP_EC
EC_SMB_DA0 CHGR 0x12
0x9E
dGPU
Power State SMBUS Port1 TMS for KB - TOP 0x98
SIGNAL SLP_S0# +3VLP_EC UF6 - (NCT7718W)
STATE CPU_C10_GATE# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock EC_SMB_CK1 TMS for Dcover - BOT 0x9A
EC_SMB_DA1 UF3 - (G781)
S0 (Full ON) HIGH HIGH HIGH HIGH HIGH ON ON ON ON TMS - safety - BOT 0x90
UF5 - (G753)
S0IX LOW LOW HIGH HIGH HIGH ON ON ON ON
S4 (Suspend to Disk) HIGH HIGH SMBUS Port2 TLC59116 0xC0
LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) HIGH PerKey KB TBD
HIGH LOW LOW LOW ON OFF OFF OFF
EC_SMB_CK2 +5VALW
EC_SMB_DA2 DDS 0x10 ~ 0x2F
TMS for VRAM - TOP
UF2 - (NCT7718W) 0x98

USB3 retimer 0x50 ~ 0x53

PS8811
4 4

PD - UT36
SMBUS Port3 (TPS65992DA) TBD
EC_I2C_3_SCL
Load BOM Option Table EC_I2C_3_SDA +3V_TBT0_PDLDO PD - UT38
TBD
(TPS65992DA)
BOM Number Load BOM Option

Security Classification
2020/09/25
Compal Secret Data
2021/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 3 of 112
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PLZ11、PLZ12 VR_ON PUZ2、PUZ3、PUZ4、PUZ5 PLM1 PJM3

(5A_Z80_0805_2P) +19VB_CPU NCP302045MNTWG +VCC_CORE 4.7UH_MLN-YT12N4R7M-M1L__1.9A +1.8V_MEMP JUMP +1.8V_MEM

+1.8V_PG PUA01 PLM2 PJM4

NCP81270MNTXG +VCCIN_AUX 0.47UH_MMD05AHNR47M_10.5A +1.065V_MEMP JUMP +1.065V_MEM

VR_ON PUG1、PUG2 PJM5

NCP302045MNTWG +VCC_GT +0.5V_VDDQP JUMP +0.5V_VDDQ
1 1

ADAPTER PLZM3 SYSON PUM1

(5A_Z80_0805_2P) +19VB_DDR TPS51488RJER

PL1802 EC_1.8V_EN PUM1 PL1801 PJ1801 RC256 RC196

(5A_Z80_0805_2P) +19VB_1.8VALWP TPS51488RJER 1UH_6.6A +1.8VALWP JUMP +1.8VALW_PRIM 0805 0 ohm +1.8V_PRIM_MCP 0402 0 ohm +1.8V_VCCA_CLKLDO

BATTERY +19VB
1V8_AON_EN UV12
5V_3V_EN AOZ1334DI-01 +1.8VSDGPU_AON
PL501 PU501 PL502 PJ501
(800LMA50T) +19VB_5V SY8288CRAC 1.5UH_9A +5VALWP JUMP +5VALW
UV108
RT9059GQW +1.2VS_DDS
CHARGER UT40
(PUB1) +20V_VIN_TYPEC_0_L TBD SUSP# UVH2
RT9059GQW +1.1V_HDMI

LDO UT39 POW_EXT_SWR UL5

+5VALW_USBA SY6288C20AAC RT9059GQW +VDD095_EXT
+3VLP

R28
2
0402 R-short +1.8VALW_ESPI 2

PL551 5V_3V_EN PU551 PL552 PJ551 EC_KBL_EN

(800LMA50T) +19VB_5V_2 SY8288CRAC 1.5UH_9A +5VALWP_2 JUMP +5VALW_L RA83
0402 0 ohm +1.8V_AUDIO
UV118
RT9059GQW +1.2V_U3RT
TypeC 1 PD-IN
UT41 SUSP#
+20V_VIN_TYPEC_1_L TBD U15 R58
JW7110DFNC +1.8VS_R 0402 R-short +1.8VS

UE12
TypeC 2 PD-IN +5VS_BL SY6288C20AAC

U12
+5V_KB SY6288C20AAC US2 R81
SLGC55544CVTR +USB3VCCA_CHG 1206 R-short +5VALW_USBB
SUSP#

U15 JPQ1 UVH3

JW7110DFNC JUMP +5VS AP2330W-7 +HDMI_5V_OUT

JPA1
JUMP +5V_AUDIO

3V_EN RF4
3
PL311 PU301 PL301 PJ302 0603 R-short +VCC_FAN1 3

(800LMA50T) +19VB_3V SY8388BRHC 1.5UH_9A +3VALWP JUMP +3VALW

RF7
LAN_PWR_EN RC68 0603 R-short +VCC_FAN2
0402 R-short +3V_SPI
UL2
+3VALW_LAN SY6288C20AAC JPC2
EC_WLAN_ON JUMP +3VALW_PRIM RF30
0603 R-short +VCC_FAN3
UM7
+3VS_WLAN SY6288C20AAC RC197
0402 0 ohm +3VALW_DSW
FP_PWR_EN RV178
+3VS 0402 0 ohm +3V_OVRM
UK5
+FP_VCC SY6288C20AAC SUSP# U14 JPQ2 LCD_ENVDD
TP_PWR_EN JW7110DFNC JUMP UV117
SY6288C20AAC +LCDVDD
UK2 TBT_2_RETIMER_LS_EN SUSP#
+3V_PTP SY6288C20AAC UV119
UT34 SY6288C20AAC +TS_PWR
SY6288C20AAC +3VS_TBT_2_RETIMER
RS1 TBT_0_RETIMER_LS_EN
+3V_U3RT 0805 R-short RA82
0402 0 ohm +3V_AUDIO
UT1
SY6288C20AAC +3VS_TBT_0_RETIMER
RT895 RR1
+3VS_TYPEA 0603 R-short 0805 R-short +3VS_CR
4 4
SUSP# UM4 JPQ3
+1.8V_PROC_EN +3VS_SSD1_NGFF
EM5209VF JUMP 3VSDGPU_EN
PJ1852 PU1851 PJ1851 U14 RG306
+1.8V_PROC JUMP AP7343D-18FS4 VIN_1.8VP_PROC JUMP JW7110DFNC 0603 R-short +3VSDGPU
JPQ4
JUMP +3VS_SSD1_NGFF
Security Classification
2020/09/25
Compal Secret Data
2021/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 4 of 112
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1 1

2 2

3 3

4 4

Security Classification
2020/09/25
Compal Secret Data
2021/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 5 of 112
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UC1A
REV 0.6
CPU_EDP_TXP3 W3 BE8 TBT_0_TRX_DTX_P1
<39> CPU_EDP_TXP3 CPU_EDP_TXN3 DDIA_TXP_3 TCP0_TXRX_P1 TBT_0_TRX_DTX_N1 TBT_0_TRX_DTX_P1 <44>
AA3 BE6
<39> CPU_EDP_TXN3 CPU_EDP_TXP2 DDIA_TXN_3 TCP0_TXRX_N1 TBT_0_TRX_DTX_P0 TBT_0_TRX_DTX_N1 <44>
AA1 BG8
<39> CPU_EDP_TXP2 CPU_EDP_TXN2 DDIA_TXP_2 TCP0_TXRX_P0 TBT_0_TRX_DTX_N0 TBT_0_TRX_DTX_P0 <44>
AB1 BG6
<39> CPU_EDP_TXN2 CPU_EDP_TXP1 DDIA_TXN_2 TCP0_TXRX_N0 TBT_0_TTX_DRX_P1 TBT_0_TRX_DTX_N0 <44>
AB3 AY3 TBT_0_TTX_DRX_P1 <44>
<39> CPU_EDP_TXP1 CPU_EDP_TXN1 DDIA_TXP_1 TCP0_TX_P1 TBT_0_TTX_DRX_N1
AD3 BB3 TBT_0_TTX_DRX_N1 <44>
<39> CPU_EDP_TXN1 CPU_EDP_TXP0 DDIA_TXN_1 TCP0_TX_N1 TBT_0_TTX_DRX_P0
1 AF1 BD3 TBT_0_TTX_DRX_P0 <44> 1
<39> CPU_EDP_TXP0 CPU_EDP_TXN0 DDIA_TXP_0 TCP0_TX_P0 TBT_0_TTX_DRX_N0
AD1 BE3 TBT_0_TTX_DRX_N0 <44>
<39> CPU_EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 TBT_0_DP_AUXP
BB1 RC1 1 @ 2 0_0201_5%
CPU_EDP_AUXP TCP0_AUX_P TBT_0_DP_AUXN TBT_0_DP_AUXP_R <44>
<39> CPU_EDP_AUXP AF3 BD1 RC2 1 @ 2 0_0201_5%
CPU_EDP_AUXN DDIA_AUXP TCP0_AUX_N TBT_0_DP_AUXN_R <44>
<39> CPU_EDP_AUXN AG3
DDIA_AUXN AV8
1.A add RC799 PD by intel command SOC_GPP_E22 ER23 TCP1_TXRX_P1 AV6
1 SOC_GPP_E23 ET23 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AY8
RC799 1 2 10K_0201_5% SOC_GPP_E22 T226 @ GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AY6
CPU_EDP_HPD EV25 TCP1_TXRX_N0 AP3
<39> CPU_EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISC_A TCP1_TX_P1 AR3
RC3 1 @ 2 100K_0201_5% SOC_HDMI_HPD AP6 TCP1_TX_N1 AU3
RC4 1 2 100K_0201_5% CPU_EDP_HPD AP8 DDIB_TXP_3 TCP1_TX_P0 AW3
AM6 DDIB_TXN_3 TCP1_TX_N0 AR1
AM8 DDIB_TXP_2 TCP1_AUX_P AU1
AK6 DDIB_TXN_2 TCP1_AUX_N
RC5 1 GLITCH@2 100K_0201_5% SOC_ENVDD AK8 DDIB_TXP_1 BN8 TBT_2_TRX_DTX_P1
DDIB_TXN_1 TCP2_TXRX_P1 TBT_2_TRX_DTX_P1 <42>
RC6 1 GLITCH@2 100K_0201_5% SOC_ENBKL AH6 BN6 TBT_2_TRX_DTX_N1
DDIB_TXP_0 TCP2_TXRX_N1 TBT_2_TRX_DTX_P0 TBT_2_TRX_DTX_N1 <42>
AH8 BL8
DDIB_TXN_0 TCP2_TXRX_P0 TBT_2_TRX_DTX_N0 TBT_2_TRX_DTX_P0 <42>
BL6
TCP2_TXRX_N0 TBT_2_TTX_DRX_P1 TBT_2_TRX_DTX_N0 <42>
AE6 BK3 TBT_2_TTX_DRX_P1 <42>
AE8 DDIB_AUXP TCP2_TX_P1 BM3 TBT_2_TTX_DRX_N1
DDIB_AUXN TCP2_TX_N1 TBT_2_TTX_DRX_N1 <42>
follow RVP BG3 TBT_2_TTX_DRX_P0
TCP2_TX_P0 TBT_2_TTX_DRX_P0 <42>
EK46 BH3 TBT_2_TTX_DRX_N0
GPP_H15/DDPB_CTRLCLK/PCIE_LINK_DOWN TCP2_TX_N0 TBT_2_TTX_DRX_N0 <42>
EL46 BH1 TBT_2_DP_AUXP RC466 1 @ 2 0_0201_5%
GPP_H17/DDPB_CTRLDATA TCP2_AUX_P TBT_2_DP_AUXN TBT_2_DP_AUXP_R <42>
BK1 RC467 1 @ 2 0_0201_5%
SOC_HDMI_HPD TCP2_AUX_N TBT_2_DP_AUXN_R <42>
EB47
<26,40> SOC_HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB BW8
DV54 TCP3_TXRX_P1 BW6 確確port
2 TPM_PIRQ# DV52 GPP_A21/DDPC_CTRLCLK TCP3_TXRX_N1 BU8 2
<66> TPM_PIRQ# GPP_A22/DDPC_CTRLDATA TCP3_TXRX_P0 BU6
TBT_0_LSX_TX ER26 TCP3_TXRX_N0 BU3
<44> TBT_0_LSX_TX TBT_0_LSX_RX GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD/BSSB_LS0_RX TCP3_TX_P1
ET26 BV3
<44> TBT_0_LSX_RX GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD/BSSB_LS0_TX TCP3_TX_N1 BN3
EL26 TCP3_TX_P0 BR3
GPP_E21 EN26 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD/BSSB_LS1_RX TCP3_TX_N0 BR1
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX TCP3_AUX_P BU1
TBT_2_LSX_TX FC37 TCP3_AUX_N
<42> TBT_2_LSX_TX TBT_2_LSX_RX GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/BSSB_LS2_RX/GSPI2_CS0#
EV37 AL3
<42> TBT_2_LSX_RX GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/BSSB_LS2_TX/GSPI2_CLK VSS TCRCOMP_DN
AM1 RC7 1 2 2.2K_0201_1%
EY37 TCP_RCOMP
+3VALW _PRIM GPP_D12 FA37 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/BSSB_LS3_RX/GSPI2_MISO AF32 DSI_DE_TE_2 RC8 1 2 100K_0201_5%
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/BSSB_LS3_TX/GSPI2_MOSI DISP_UTILS_2
RC9 1 2 10K_0201_5% USB_OC2# PCH_PW M_MUX DY54 AJ1 DDIA_RCOMP RC10 1 2 150_0201_1%
RC11 1 2 10K_0201_5% USB_OC1# <39> PCH_PWM_MUX EB49 GPP_A17/DISP_MISCC DDIA_RCOMP AL1 DDIB_RCOMP RC12 1 2 150_0201_1%
EB51 GPP_A19/DDSP_HPD1/DISP_MISC1 DDIB_RCOMP
GPP_A20/DDSP_HPD2/DISP_MISC2 DJ1 DISP_UTILS RC279 1 @ 2 100K_0201_5%
USB_OC1# DY47 DISP_UTILS_1
<71> USB_OC1# USB_OC2# GPP_A14/USB_OC1#/DDSP_HPD3/DISP_MISC3
DY49 Intel reserve
<72> USB_OC2# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4
SOC_ENVDD ET21
<39> SOC_ENVDD SOC_ENBKL VDDEN
EN21
<39,58> SOC_ENBKL SOC_BKL_PW M eDP_BKLTEN
EL21
<39> SOC_BKL_PW M eDP_BKLTCTL

ADL-P_BGA1744
@
3 +3VALW _PRIM Signal: TBT_0_LSX_RX 3
Usage: TBT LSX #0 PINS VCCIO CONFIGURATION
This strap has a 20 kohm ± 30% internal pull-down.
0=> DDP1 I2C / TBT_LSX0 / BSSB_LS0 pins at 1.8V
1=> DDP1 I2C / TBT_LSX0 / BSSB_LS0 pins at 3.3V
4.7K_0201_5%

4.7K_0201_5%

4.7K_0201_5%

4.7K_0201_5%

Notes:
1

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well.
RC318

RC319

RC320

RC321

@ @ @ @
Signal: TBT_1_LSX_RX/GPP_E21
Usage: TBT LSX #1 PINS VCCIO CONFIGURATION
2

This strap has a 20 kohm ± 30% internal pull-down.

0 = DDP2 I2C / TBT_LSX1 / BSSB LS1 pins at 1.8V
1 = DDP2 I2C / TBT_LSX1 / BSSB LS1 pins at 3.3V
TBT_0_LSX_RX Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
GPP_E21 2. This signal is in the primary well.

TBT_2_LSX_RX Signal: TBT_2_LSX_RX

Usage: TBT LSX #2 PINS VCCIO CONFIGURATION
GPP_D12 This strap has a 20 kohm ± 30% internal pull-down.
0 = DDP3 I2C / TBT_LSX2 / BBSB_LS2 pins at 1.8V
1 = DDP3 I2C / TBT_LSX2 / BBSB_LS2 pins at 3.3V
1

1
20K_0201_5%
RC787

20K_0201_5%
RC788

20K_0201_5%
RC789

20K_0201_5%
RC790

Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well.

Signal: TBT_3_LSX_RX/GPP_D12
2

Usage: TBT LSX #3 PINS VCCIO CONFIGURATION

4 This strap has a 20 kohm ± 30% internal pull-down. 4
0 = DDP4 I2C / TBT_LSX3 / BBSB_LS3 pins at 1.8V
1 = DDP4 I2C / TBT_LSX3 / BBSB_LS3 pins at 3.3
Notes:
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. This signal is in the primary well.
確確確確 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(1/14)DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 6 of 121
A B C D E
 A B C D E

+1.05V_PROC

1 2 CATERR#
RC13 1K_0201_5% CHECK power net name, 05/17
2 1 H_THERMTRIP#
RC15 1K_0201_5% +1.05V_PROC

CC1 2 1 0.1U_0201_10V6K

1
XEMC@ RC16 UC1V
1 1K_0201_5% REV0.6 1
CATERR# AF15 R6 SOC_XDP_TRST#
0.1U_0201_10V6K 1 2 CC2 H_PECI H_PECI DG3 CATERR# PROC_JTAG_TRST# U8 SOC_XDP_TMS
<58> H_PECI

2
1 2 H_PROCHOT#_R AK32 PECI PROC_JTAG_TMS AA6 SOC_XDP_TDO
<58,85> H_PROCHOT# PROCHOT# PROC_JTAG_TDO
XEMC@ RC18 499_0201_1% H_THERMTRIP# AH32 W8 SOC_XDP_TDI
THERMTRIP# PROC_JTAG_TDI N6 SOC_XDP_TCK0
RC19 2 1 PROC_POPIRCOMP EMC@ 2 1 PROC_POPIRCOMP DV60 PROC_JTAG_TCK
49.9_0201_1% CC3 100P_0201_50V8J PCH_OPIRCOMP DG1 PROC_POPIRCOMP N8 SOC_XDP_TCK0
RC20 2 1 PCH_OPIRCOMP 1 SOC_TP_1 DV11 DMI_RCOMP PCH_JTAGX U6 SOC_XDP_TMS
ESD function TP_3 PCH_JTAG_TMS
49.9_0201_1% T228 @ 1 SOC_TP_2 DV10 AA8 SOC_XDP_TDO
T229 @ TP_2 PCH_JTAG_TDO W6 SOC_XDP_TDI
XDP_ITP_PMODE ET14 PCH_JTAG_TDI FB6 PCH_JTAG_TCK1
DBG_PMODE PCH_JTAG_TCK R8 SOC_XDP_TRST#
1 T230@
EB56 PCH_PROC_TRST#
EC_TP_INT# EB57 GPP_B4/PROC_GP3/ISH_GP5B L6 XDP_PREQ#
+3VS <58,66> EC_TP_INT# GPP_B3/PROC_GP2/ISH_GP4B PROC_PREQ#
SOC_GPP_E7 FB23 L8 XDP_PRDY# 1 T233@
EY23 GPP_E7/PROC_GP1 PROC_PRDY#
check SW setting for leakage, 1225 GPP_E3/PROC_GP0
1 @ 2 SOC_GPP_E7 AF25 SOC_EAR
RC21 10K_0201_5% SOC_GPP_H2 ET46 EAR#
SOC_GPP_H1 EL48 GPP_H2 EN28 SOC_TS_RST#
SOC_GPP_H0 GPP_H1 GPP_F7 SOC_TS_RST# <38>
EK48 ET28 TS_I2C_INT#
GPP_H0 GPP_F9/BOOTMPC TS_I2C_INT# <38>
EF28
DY61 GPP_F10
+3VALW _PRIM PCH_SPKR DW56 GPP_B15/TIME_SYNC0/ISH_GP7
<56> PCH_SPKR GPP_B14/SPKR/TIME_SYNC1/SATA_LED#/ISH_GP6

ADL-P_BGA1744
1

@
2 RC26 RC27 RC28 +1.05V_PROC 2
4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5% +3VALW _PRIM
@ @ @ SOC_XDP_TMS 51_0201_5% 2 CMC@ 1RC22
2

1
SOC_XDP_TDI 51_0201_5% 2 CMC@ 1RC24
SOC_GPP_H2 RC31
100K_0201_5% SOC_XDP_TDO 51_0201_5% 2 CMC@ 1RC25
SOC_GPP_H1
check SW setting, 1225 @ 05/13 RC93 change 100 follow ADL DDR4 RVP rev07

2
SOC_GPP_H0 1 2 H_PROCHOT#
<17,43,46> VCCIN_AUX_CORE_ALERT#_R
DC1 1.0 RC25 change from 100 ohm to 51 ohm
RB751S40T1G_SOD523-2
2

RC460 RC461 RC462 SOC_XDP_TCK0 51_0201_5% 2 CMC@ 1RC29

20K_0201_5% 20K_0201_5% 20K_0201_5%
PCH_JTAG_TCK1 51_0201_5% 2 @ 1RC30
1

+1.05VO_OUT_FET
@ @ @
RC23 1 CMC@ 2 1K_0201_5% XDP_ITP_PMODE
EDS 12.12 internal PH/PD
XDP_ITP_PMODE
DFX TEST MODE
INTERNAL PU 20K
This strap should sample high. There should NOT be
SOC_GPP_H0 GH4FT For RTD3 SSD any on-board device driving it to opposite direction +1.05V_PROC
GH52T Remove 20200817 during strap sampling.
SOC_GPP_H2
BOOT STRAP3 - BIT3 XDP_PREQ# RC255 1 @ 2 3.3K_0201_5%
3 This is bit 1 of a total of 4-bit encoded pin straps for 3
boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
Strap Pin 05/17 Follow ADL_P SchChk_rev1.2
INTERNAL PD 20K +3VS
SOC_GPP_H1
BOOT STRAP1 - BIT2
This is bit 1 of a total of 4-bit encoded pin straps for +1.05V_PROC
boot configuration.
4.7K_0201_5%

Refer to Boot Strap 0 (on GPP_C5) for the encoding.

1

INTERNAL PD 20K

1
RC458

SOC_GPP_H0 @ RC14
BOOT STRAP1 - BIT1 1K_0201_5%
This is bit 1 of a total of 4-bit encoded pin straps for
2

boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.

2
INTERNAL PD 20K
SOC_EAR
PCH_SPKR

1
SPKR Stall reset sequence after PCU PLL
TOP SWAP OVERRIDE RC17
INTERNAL PD 20K lock until de-asserted:
SOC_WWAN_RST# (No used) 1K_0201_5%
20K_0201_5%

HIGH: Top swap enable 1 = (Default) Normal

1

This strap should sample LOW. There should NOT be @

any on-board device driving it to opposite direction LOW: Disable (Default) Operation; No stall.
RC459

2
during strap sampling. 0 = Stall.
INTERNAL PD 20K @
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(2/14)MISC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 7 of 121
A B C D E
 5 4 3 2 1

Follow Intel LPDDR5

D D

UC1B
<21> DDR_M0_D0_[0..7] REV0.6 UC1C
DDR_M0_D0_7 DH58 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CD49 REV0.6
DDR_M0_D0_6 DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7/DDR0_DQ_0_7 DDR0_CLK_P_1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P/DDR1_CLK_P_1 DDR_M3_CLK <22> <23> DDR_M4_D0_[0..7] DDR_M4_D0_7
DG57 CD48 BB58 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 V48
DDR_M0_D0_5 DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6/DDR0_DQ_0_6 DDR0_CLK_N_1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N/DDR1_CLK_N_1 CH61 DDR_M3_CLK# <22> DDR_M4_D0_6 DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7/DDR4_DQ_0_7 DDR1_CLK_P_1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P/DDR3_CLK_P_1 DDR_M7_CLK <24>
DH56 BA57 V49
DDR_M0_D0_4 DG60 DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5/DDR0_DQ_0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P/DDR1_CLK_P_0 CF61 DDR_M2_CLK <22> DDR_M4_D0_5 BB56 DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6/DDR4_DQ_0_6 DDR1_CLK_N_1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N/DDR3_CLK_N_1 AB61 DDR_M7_CLK# <24>
DDR_M0_D0_3 DL60 DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4/DDR0_DQ_0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N/DDR1_CLK_N_0 CN49 DDR_M2_CLK# <22> DDR_M4_D0_4 BA60 DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5/DDR4_DQ_0_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P/DDR3_CLK_P_0 Y61 DDR_M6_CLK <24>
DDR_M0_D0_2 DK56 DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3/DDR0_DQ_0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P/DDR0_CLK_P_1 CN48 DDR_M1_CLK <21> DDR_M4_D0_3 BE60 DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4/DDR4_DQ_0_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N/DDR3_CLK_N_0 AG49 DDR_M6_CLK# <24>
DDR_M0_D0_1 DL57 DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2/DDR0_DQ_0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N/DDR0_CLK_N_1 CU61 DDR_M1_CLK# <21> DDR_M4_D0_2 BD56 DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3/DDR4_DQ_0_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P/DDR2_CLK_P_1 AG48 DDR_M5_CLK <23>
DDR_M0_D0_0 DK58 DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1/DDR0_DQ_0_1 DDR0_CLK_P_0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P_0 CR61 DDR_M0_CLK <21> DDR_M4_D0_1 BE57 DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2/DDR4_DQ_0_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N/DDR2_CLK_N_1 AL61 DDR_M5_CLK# <23>
<21> DDR_M0_D1_[0..7] DDR_M0_D1_7 DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0/DDR0_DQ_0_0 DDR0_CLK_N_0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N_0 DDR_M0_CLK# <21> DDR_M4_D0_0 DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1/DDR4_DQ_0_1 DDR1_CLK_P_0/DDR4_CLK_P/DDR4_CLK_P/DDR4_CLK_P/DDR2_CLK_P_0 DDR_M4_CLK <23>
DA58 <23> DDR_M4_D1_[0..7] BD58 AJ61
DDR_M0_D1_6 DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7/DDR0_DQ_1_7 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 DDR_M4_D1_7 DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0/DDR4_DQ_0_0 DDR1_CLK_N_0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N/DDR2_CLK_N_0 DDR_M4_CLK# <23>
CY57 CF51 AR58
DDR_M0_D1_5 DB56 DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6/DDR0_DQ_1_6 NC/DDR3_CKE_0/DDR3_WCK_P/DDR3_WCK_P/NC CH51 DDR_M3_WCK_P <22> DDR_M4_D1_6 AP57 DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7/DDR4_DQ_1_7 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AB51
DDR_M0_D1_4 CY60 DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5/DDR0_DQ_1_5 NC/DDR3_CKE_1/DDR3_WCK_N/DDR3_WCK_N/NC CE57 DDR_M3_WCK_N <22> DDR_M4_D1_5 AR56 DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6/DDR4_DQ_1_6 NC/DDR7_CKE_0/DDR7_WCK_P/DDR7_WCK_P/NC Y51 DDR_M7_WCK_P <24>
DDR_M0_D1_3 DE60 DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4/DDR0_DQ_1_4 NC/DDR2_CKE_0/DDR2_WCK_P/DDR2_WCK_P/NC CF58 DDR_M2_WCK_P <22> DDR_M4_D1_4 AP60 DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5/DDR4_DQ_1_5 NC/DDR7_CKE_1/DDR7_WCK_N/DDR7_WCK_N/NC W57 DDR_M7_WCK_N <24>
DDR_M0_D1_2 DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3/DDR0_DQ_1_3 NC/DDR2_CKE_1/DDR2_WCK_N/DDR2_WCK_N/NC CR51 DDR_M2_WCK_N <22> DDR_M4_D1_3 DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4/DDR4_DQ_1_4 NC/DDR6_CKE_0/DDR6_WCK_P/DDR6_WCK_P/NC Y58 DDR_M6_WCK_P <24>
DD56 AV60
DDR_M0_D1_1 DE57 DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2/DDR0_DQ_1_2 NC/DDR1_CKE_0/DDR1_WCK_P/DDR1_WCK_P/NC CU51 DDR_M1_WCK_P <21> DDR_M4_D1_2 AU56 DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3/DDR4_DQ_1_3 NC/DDR6_CKE_1/DDR6_WCK_N/DDR6_WCK_N/NC AL51 DDR_M6_WCK_N <24>
DDR_M0_D1_0 DD58 DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1/DDR0_DQ_1_1 NC/DDR1_CKE_1/DDR1_WCK_N/DDR1_WCK_N/NC CR58 DDR_M1_WCK_N <21> DDR_M4_D1_1 AV57 DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2/DDR4_DQ_1_2 NC/DDR5_CKE_0/DDR5_WCK_P/DDR5_WCK_P/NC AJ51 DDR_M5_WCK_P <23>
<21> DDR_M1_D0_[0..7] DDR_M1_D0_7 DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0/DDR0_DQ_1_0 NC/DDR0_CKE_0/DDR0_WCK_P/DDR0_WCK_P/NC CP57 DDR_M0_WCK_P <21> DDR_M4_D1_0 DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1/DDR4_DQ_1_1 NC/DDR5_CKE_1/DDR5_WCK_N/DDR5_WCK_N/NC AJ58 DDR_M5_WCK_N <23>
DG50 <23> DDR_M5_D0_[0..7] AU58
DDR_M1_D0_6 DG47 DDR1_DQ_0_7/DDR0_DQ_2_7/DDR0_DQ_2_7/DDR1_DQ_0_7 NC/DDR0_CKE_1/DDR0_WCK_N/DDR0_WCK_N/NC DDR_M0_WCK_N <21> DDR_M5_D0_7 BA50 DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0/DDR4_DQ_1_0 NC/DDR4_CKE_0/DDR4_WCK_P/DDR4_WCK_P/NC AH57 DDR_M4_WCK_P <23>
DDR_M1_D0_5 DDR1_DQ_0_6/DDR0_DQ_2_6/DDR0_DQ_2_6/DDR1_DQ_0_6 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL) DDR_M5_D0_6 DDR1_DQ_4_7/DDR1_DQ_2_7/DDR2_DQ_2_7/DDR5_DQ_0_7 NC/DDR4_CKE_1/DDR4_WCK_N/DDR4_WCK_N/NC DDR_M4_WCK_N <23>
DH48 BN51 AY47
DDR_M1_D0_4 DDR1_DQ_0_5/DDR0_DQ_2_5/DDR0_DQ_2_5/DDR1_DQ_0_5 DDR1_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3/DDR3_DQSP_1 DDR_M3_DQS1 <22> DDR_M5_D0_5 DDR1_DQ_4_6/DDR1_DQ_2_6/DDR2_DQ_2_6/DDR5_DQ_0_6 DDR4(IL) / DDR4(NIL) / DDR5(NIL) / LP4x-LP5(NIL)
DG53 BL51 BB48 N51
DDR_M1_D0_3 DDR1_DQ_0_4/DDR0_DQ_2_4/DDR0_DQ_2_4/DDR1_DQ_0_4 DDR1_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3/DDR3_DQSN_1 DDR_M3_DQS#1 <22> DDR_M5_D0_4 DDR1_DQ_4_5/DDR1_DQ_2_5/DDR2_DQ_2_5/DDR5_DQ_0_5 DDR1_DQSP_7/DDR1_DQSP_7/DDR3_DQSP_3/DDR7_DQSP_1 L51 DDR_M7_DQS1 <24>
DL53 BW51 BA53
DDR_M1_D0_2 DDR1_DQ_0_3/DDR0_DQ_2_3/DDR0_DQ_2_3/DDR1_DQ_0_3 DDR1_DQSP_2/DDR0_DQSP_6/DDR1_DQSP_2/DDR3_DQSP_0 DDR_M3_DQS0 <22> DDR_M5_D0_3 DDR1_DQ_4_4/DDR1_DQ_2_4/DDR2_DQ_2_4/DDR5_DQ_0_4 DDR1_DQSN_7/DDR1_DQSN_7/DDR3_DQSN_3/DDR7_DQSN_1 N61 DDR_M7_DQS#1 <24>
DK48 BU51 DDR_M3_DQS#0 <22> BE53 DDR_M7_DQS0 <24>
DDR_M1_D0_1 DM47 DDR1_DQ_0_2/DDR0_DQ_2_2/DDR0_DQ_2_2/DDR1_DQ_0_2 DDR1_DQSN_2/DDR0_DQSN_6/DDR1_DQSN_2/DDR3_DQSN_0 BL61 DDR_M5_D0_2 BD48 DDR1_DQ_4_3/DDR1_DQ_2_3/DDR2_DQ_2_3/DDR5_DQ_0_3 DDR1_DQSP_6/DDR1_DQSP_6/DDR3_DQSP_2/DDR7_DQSP_0 L61
DDR_M1_D0_0 DDR1_DQ_0_1/DDR0_DQ_2_1/DDR0_DQ_2_1/DDR1_DQ_0_1 DDR0_DQSP_3/DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1 DDR_M2_DQS1 <22> DDR_M5_D0_1 DDR1_DQ_4_2/DDR1_DQ_2_2/DDR2_DQ_2_2/DDR5_DQ_0_2 DDR1_DQSN_6/DDR1_DQSN_6/DDR3_DQSN_2/DDR7_DQSN_0 A43 DDR_M7_DQS#0 <24>
DL50 BN61 BE47
<21> DDR_M1_D1_[0..7] DDR_M1_D1_7 DDR1_DQ_0_0/DDR0_DQ_2_0/DDR0_DQ_2_0/DDR1_DQ_0_0 DDR0_DQSN_3/DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1 DDR_M2_DQS#1 <22> DDR_M5_D0_0 DDR1_DQ_4_1/DDR1_DQ_2_1/DDR2_DQ_2_1/DDR5_DQ_0_1 DDR0_DQSP_7/DDR1_DQSP_5/DDR3_DQSP_1/DDR6_DQSP_1 A44 DDR_M6_DQS1 <24>
CY50 BU61 BE50
DDR_M1_D1_6 DDR1_DQ_1_7/DDR0_DQ_3_7/DDR0_DQ_3_7/DDR1_DQ_1_7 DDR0_DQSP_2/DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0 DDR_M2_DQS0 <22> <23> DDR_M5_D1_[0..7] DDR_M5_D1_7 DDR1_DQ_4_0/DDR1_DQ_2_0/DDR2_DQ_2_0/DDR5_DQ_0_0 DDR0_DQSN_7/DDR1_DQSN_5/DDR3_DQSN_1/DDR6_DQSN_1 A49 DDR_M6_DQS#1 <24>
CY47 BW61 AP50
DDR_M1_D1_5 DDR1_DQ_1_6/DDR0_DQ_3_6/DDR0_DQ_3_6/DDR1_DQ_1_6 DDR0_DQSN_2/DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0 DDR_M2_DQS#0 <22> DDR_M5_D1_6 DDR1_DQ_5_7/DDR1_DQ_3_7/DDR2_DQ_3_7/DDR5_DQ_1_7 DDR0_DQSP_6/DDR1_DQSP_4/DDR3_DQSP_0/DDR6_DQSP_0 A51 DDR_M6_DQS0 <24>
DB48 DC51 AP47
DDR_M1_D1_4 DDR1_DQ_1_5/DDR0_DQ_3_5/DDR0_DQ_3_5/DDR1_DQ_1_5 DDR1_DQSP_1/DDR0_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1 DDR_M1_DQS1 <21> DDR_M5_D1_5 DDR1_DQ_5_6/DDR1_DQ_3_6/DDR2_DQ_3_6/DDR5_DQ_1_6 DDR0_DQSN_6/DDR1_DQSN_4/DDR3_DQSN_0/DDR6_DQSN_0 AU51 DDR_M6_DQS#0 <24>
DA53 DB51 AR48
DDR_M1_D1_3 DDR1_DQ_1_4/DDR0_DQ_3_4/DDR0_DQ_3_4/DDR1_DQ_1_4 DDR1_DQSN_1/DDR0_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1 DDR_M1_DQS#1 <21> DDR_M5_D1_4 DDR1_DQ_5_5/DDR1_DQ_3_5/DDR2_DQ_3_5/DDR5_DQ_1_5 DDR1_DQSP_5/DDR1_DQSP_3/DDR2_DQSP_3/DDR5_DQSP_1 AR51 DDR_M5_DQS1 <23>
DE53 DK51 AP53
DDR_M1_D1_2 DDR1_DQ_1_3/DDR0_DQ_3_3/DDR0_DQ_3_3/DDR1_DQ_1_3 DDR1_DQSP_0/DDR0_DQSP_2/DDR0_DQSP_2/DDR1_DQSP_0 DDR_M1_DQS0 <21> DDR_M5_D1_3 DDR1_DQ_5_4/DDR1_DQ_3_4/DDR2_DQ_3_4/DDR5_DQ_1_4 DDR1_DQSN_5/DDR1_DQSN_3/DDR2_DQSN_3/DDR5_DQSN_1 BD51 DDR_M5_DQS#1 <23>
DC48 DH51 DDR_M1_DQS#0 <21> AV53 DDR_M5_DQS0 <23>
DDR_M1_D1_1 DE47 DDR1_DQ_1_2/DDR0_DQ_3_2/DDR0_DQ_3_2/DDR1_DQ_1_2 DDR1_DQSN_0/DDR0_DQSN_2/DDR0_DQSN_2/DDR1_DQSN_0 DB61 DDR_M5_D1_2 AU48 DDR1_DQ_5_3/DDR1_DQ_3_3/DDR2_DQ_3_3/DDR5_DQ_1_3 DDR1_DQSP_4/DDR1_DQSP_2/DDR2_DQSP_2/DDR5_DQSP_0 BB51
DDR_M1_D1_0 DDR1_DQ_1_1/DDR0_DQ_3_1/DDR0_DQ_3_1/DDR1_DQ_1_1 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 DDR_M0_DQS1 <21> DDR_M5_D1_1 DDR1_DQ_5_2/DDR1_DQ_3_2/DDR2_DQ_3_2/DDR5_DQ_1_2 DDR1_DQSN_4/DDR1_DQSN_2/DDR2_DQSN_2/DDR5_DQSN_0 AR61 DDR_M5_DQS#0 <23>
<22> DDR_M2_D0_[0..7] DE50 DC61 DDR_M0_DQS#1 <21> AW47 DDR_M4_DQS1 <23>
DDR_M2_D0_7 BU58 DDR1_DQ_1_0/DDR0_DQ_3_0/DDR0_DQ_3_0/DDR1_DQ_1_0 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DH61 DDR_M5_D1_0 AV50 DDR1_DQ_5_1/DDR1_DQ_3_1/DDR2_DQ_3_1/DDR5_DQ_1_1 DDR0_DQSP_5/DDR1_DQSP_1/DDR2_DQSP_1/DDR4_DQSP_1 AU61
DDR_M2_D0_6 DDR0_DQ_2_7/DDR0_DQ_4_7/DDR1_DQ_0_7/DDR2_DQ_0_7 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDR_M0_DQS0 <21> <24> DDR_M6_D0_[0..7] DDR_M6_D0_7 DDR1_DQ_5_0/DDR1_DQ_3_0/DDR2_DQ_3_0/DDR5_DQ_1_0 DDR0_DQSN_5/DDR1_DQSN_1/DDR2_DQSN_1/DDR4_DQSN_1 BB61 DDR_M4_DQS#1 <23>
BT57 DK61 C49
DDR_M2_D0_5 DDR0_DQ_2_6/DDR0_DQ_4_6/DDR1_DQ_0_6/DDR2_DQ_0_6 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR_M0_DQS#0 <21> DDR_M6_D0_6 DDR0_DQ_6_7/DDR1_DQ_4_7/DDR3_DQ_0_7/DDR6_DQ_0_7 DDR0_DQSP_4/DDR1_DQSP_0/DDR2_DQSP_0/DDR4_DQSP_0 BD61 DDR_M4_DQS0 <23>
BU56 E48 DDR_M4_DQS#0 <23>
DDR_M2_D0_4 BT60 DDR0_DQ_2_5/DDR0_DQ_4_5/DDR1_DQ_0_5/DDR2_DQ_0_5 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CM60 DDR_M6_D0_5 F49 DDR0_DQ_6_6/DDR1_DQ_4_6/DDR3_DQ_0_6/DDR6_DQ_0_6 DDR0_DQSN_4/DDR1_DQSN_0/DDR2_DQSN_0/DDR4_DQSN_0
DDR_M2_D0_3 DDR0_DQ_2_4/DDR0_DQ_4_4/DDR1_DQ_0_4/DDR2_DQ_0_4 DDR0_MA_5/DDR0_CA_5/DDR0_CA_6/DDR0_CA_0/NC DDR_M0_CA0 <21> DDR_M6_D0_4 DDR0_DQ_6_5/DDR1_DQ_4_5/DDR3_DQ_0_5/DDR6_DQ_0_5 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5
BY60 CL55 B48 AE60
DDR_M2_D0_2 BW56 DDR0_DQ_2_3/DDR0_DQ_4_3/DDR1_DQ_0_3/DDR2_DQ_0_3 DDR0_MA_7/DDR0_CA_4/DDR0_CA_5/DDR0_CA_1/NC CM57 DDR_M0_CA1 <21> DDR_M6_D0_3 B52 DDR0_DQ_6_4/DDR1_DQ_4_4/DDR3_DQ_0_4/DDR6_DQ_0_4 DDR1_MA_5/DDR4_CA_5/DDR4_CA_6/DDR4_CA_0/NC AE55 DDR_M4_CA0 <23>
DDR_M2_D0_1 DDR0_DQ_2_2/DDR0_DQ_4_2/DDR1_DQ_0_2/DDR2_DQ_0_2 DDR0_MA_6/DDR0_CA_3/DDR0_CA_4/DDR0_CS_1/NC DDR_M0_CS#1 <21> DDR_M6_D0_2 DDR0_DQ_6_3/DDR1_DQ_4_3/DDR3_DQ_0_3/DDR6_DQ_0_3 DDR1_MA_7/DDR4_CA_4/DDR4_CA_5/DDR4_CA_1/NC DDR_M4_CA1 <23>
BY57 CP60 Descending F51 AF57
DDR_M2_D0_0 BW58 DDR0_DQ_2_1/DDR0_DQ_4_1/DDR1_DQ_0_1/DDR2_DQ_0_1 DDR0_MA_8/DDR0_CA_2/DDR0_CA_3/DDR0_CS_0/DDR0_CA_9 CU58 DDR_M0_CS#0 <21> DDR_M6_D0_1 E52 DDR0_DQ_6_2/DDR1_DQ_4_2/DDR3_DQ_0_2/DDR6_DQ_0_2 DDR1_MA_6/DDR4_CA_3/DDR4_CA_4/DDR4_CS_1/NC AH60 DDR_M4_CS#1 <23> Descending
<22> DDR_M2_D1_[0..7] DDR_M2_D1_7 DDR0_DQ_2_0/DDR0_DQ_4_0/DDR1_DQ_0_0/DDR2_DQ_0_0 NC/DDR0_CA_1/DDR0_CA_1/DDR0_CA_5/DDR0_CA_0 DDR_M0_CA5 <21> DDR_M6_D0_0 DDR0_DQ_6_1/DDR1_DQ_4_1/DDR3_DQ_0_1/DDR6_DQ_0_1 DDR1_MA_8/DDR4_CA_2/DDR4_CA_3/DDR4_CS_0/DDR2_CA_9 DDR_M4_CS#0 <23>
BL58 CU56 C51 AL56
DDR_M2_D1_6 DDR0_DQ_3_7/DDR0_DQ_5_7/DDR1_DQ_1_7/DDR2_DQ_1_7 NC/DDR0_CA_0/DDR0_CA_0/DDR0_CA_6/DDR0_CA_1 DDR_M0_CA6 <21> <24> DDR_M6_D1_[0..7] DDR_M6_D1_7 DDR0_DQ_6_0/DDR1_DQ_4_0/DDR3_DQ_0_0/DDR6_DQ_0_0 NC/DDR4_CA_1/DDR4_CA_1/DDR4_CA_5/DDR2_CA_1 DDR_M4_CA5 <23>
BK57 CM47 E41 AL58
DDR_M2_D1_5 DDR0_DQ_3_6/DDR0_DQ_5_6/DDR1_DQ_1_6/DDR2_DQ_1_6 DDR0_BA_1/DDR1_CA_5/DDR1_CA_6/DDR1_CA_0/DDR0_CA_10 DDR_M1_CA6 <21> DDR_M6_D1_6 DDR0_DQ_7_7/DDR1_DQ_5_7/DDR3_DQ_1_7/DDR6_DQ_1_7 NC/DDR4_CA_0/DDR4_CA_0/DDR4_CA_6/DDR2_CA_0 DDR_M4_CA6 <23>
BL56 CM53 C42 AE47
DDR_M2_D1_4 DDR0_DQ_3_5/DDR0_DQ_5_5/DDR1_DQ_1_5/DDR2_DQ_1_5 DDR0_MA_16/DDR1_CA_4/DDR1_CA_5/DDR1_CA_1/DDR0_CA_8 DDR_M1_CA5 <21> DDR_M6_D1_5 DDR0_DQ_7_6/DDR1_DQ_5_6/DDR3_DQ_1_6/DDR6_DQ_1_6 DDR1_BA_1/DDR5_CA_5/DDR5_CA_6/DDR5_CA_0/DDR2_CA_10 DDR_M5_CA6 <23>
BK60 CT46 F43 AE53
DDR_M2_D1_3 BP60 DDR0_DQ_3_4/DDR0_DQ_5_4/DDR1_DQ_1_4/DDR2_DQ_1_4 DDR0_MA_15/DDR1_CA_3/DDR1_CA_4/DDR1_CS_1/DDR0_CA_7 CP53 DDR_M1_CA4 <21> Ascending DDR_M6_D1_4 B41 DDR0_DQ_7_5/DDR1_DQ_5_5/DDR3_DQ_1_5/DDR6_DQ_1_5 DDR1_MA_16/DDR5_CA_4/DDR5_CA_5/DDR5_CA_1/DDR2_CA_8 AK46 DDR_M5_CA5 <23>
DDR_M2_D1_2 BN56 DDR0_DQ_3_3/DDR0_DQ_5_3/DDR1_DQ_1_3/DDR2_DQ_1_3 DDR0_MA_14/DDR1_CA_2/DDR1_CA_3/DDR1_CS_0/DDR0_CA_11 CW47 DDR_M1_CA3 <21> DDR_M6_D1_3 B46 DDR0_DQ_7_4/DDR1_DQ_5_4/DDR3_DQ_1_4/DDR6_DQ_1_4 DDR1_MA_15/DDR5_CA_3/DDR5_CA_4/DDR5_CS_1/DDR2_CA_7 AH53 DDR_M5_CA4 <23> Ascending
C DDR_M2_D1_1 BP57 DDR0_DQ_3_2/DDR0_DQ_5_2/DDR1_DQ_1_2/DDR2_DQ_1_2 DDR0_CS_1/DDR1_CA_1/DDR1_CA_1/DDR1_CA_5/DDR0_CA_2 CV53 DDR_M1_CA1 <21> DDR_M6_D1_2 F44 DDR0_DQ_7_3/DDR1_DQ_5_3/DDR3_DQ_1_3/DDR6_DQ_1_3 DDR1_MA_14/DDR5_CA_2/DDR5_CA_3/DDR5_CS_0/DDR2_CA_11 AM47 DDR_M5_CA3 <23> C
DDR_M2_D1_0 DDR0_DQ_3_1/DDR0_DQ_5_1/DDR1_DQ_1_1/DDR2_DQ_1_1 DDR0_ODT_1/DDR1_CA_0/DDR1_CA_0/DDR1_CA_6/DDR0_CA_3 DDR_M1_CA0 <21> DDR_M6_D1_1 DDR0_DQ_7_2/DDR1_DQ_5_2/DDR3_DQ_1_2/DDR6_DQ_1_2 DDR1_CS_1/DDR5_CA_1/DDR5_CA_1/DDR5_CA_5/DDR2_CA_2 DDR_M5_CA1 <23>
<22> DDR_M3_D0_[0..7] BN58 CC60 E46 AM53
DDR_M3_D0_7 DDR0_DQ_3_0/DDR0_DQ_5_0/DDR1_DQ_1_0/DDR2_DQ_1_0 DDR0_CKE_0/DDR2_CA_5/DDR2_CA_6/DDR2_CA_0/NC DDR_M2_CA6 <22> DDR_M6_D1_0 DDR0_DQ_7_1/DDR1_DQ_5_1/DDR3_DQ_1_1/DDR6_DQ_1_1 DDR1_ODT_1/DDR5_CA_0/DDR5_CA_0/DDR5_CA_6/DDR2_CA_3 DDR_M5_CA0 <23>
BT50 CB55 C45 T55
DDR_M3_D0_6 DDR1_DQ_2_7/DDR0_DQ_6_7/DDR1_DQ_2_7/DDR3_DQ_0_7 DDR0_CKE_1/DDR2_CA_4/DDR2_CA_5/DDR2_CA_1/NC DDR_M2_CA5 <22> <24> DDR_M7_D0_[0..7] DDR_M7_D0_7 DDR0_DQ_7_0/DDR1_DQ_5_0/DDR3_DQ_1_0/DDR6_DQ_1_0 DDR1_CKE_0/DDR6_CA_5/DDR6_CA_6/DDR6_CA_0/NC DDR_M6_CA6 <24>
BT47 CC57 L58 T60
DDR_M3_D0_5 BU48 DDR1_DQ_2_6/DDR0_DQ_6_6/DDR1_DQ_2_6/DDR3_DQ_0_6 DDR0_BG_0/DDR2_CA_3/DDR2_CA_4/DDR2_CS_1/NC CE60 DDR_M2_CA4 <22> Ascending DDR_M7_D0_6 K57 DDR1_DQ_6_7/DDR1_DQ_6_7/DDR3_DQ_2_7/DDR7_DQ_0_7 DDR1_CKE_1/DDR6_CA_4/DDR6_CA_5/DDR6_CA_1/NC W60 DDR_M6_CA5 <24>
DDR_M3_D0_4 BT53 DDR1_DQ_2_5/DDR0_DQ_6_5/DDR1_DQ_2_5/DDR3_DQ_0_5 DDR0_BG_1/DDR2_CA_2/DDR2_CA_3/DDR2_CS_0/DDR1_CA_4 CH56 DDR_M2_CA3 <22> DDR_M7_D0_5 L56 DDR1_DQ_6_6/DDR1_DQ_6_6/DDR3_DQ_2_6/DDR7_DQ_0_6 DDR1_BG_0/DDR6_CA_3/DDR6_CA_4/DDR6_CS_1/DDR3_CA_4 U57 DDR_M6_CA4 <24> Ascending
DDR_M3_D0_3 DDR1_DQ_2_4/DDR0_DQ_6_4/DDR1_DQ_2_4/DDR3_DQ_0_4 DDR0_MA_12/DDR2_CA_1/DDR2_CA_1/DDR2_CA_5/DDR1_CA_12 DDR_M2_CA1 <22> DDR_M7_D0_4 DDR1_DQ_6_5/DDR1_DQ_6_5/DDR3_DQ_2_5/DDR7_DQ_0_5 DDR1_BG_1/DDR6_CA_2/DDR6_CA_3/DDR6_CS_0/NC DDR_M6_CA3 <24>
BY53 CH58 K60 AB58
DDR_M3_D0_2 DDR1_DQ_2_3/DDR0_DQ_6_3/DDR1_DQ_2_3/DDR3_DQ_0_3 DDR0_MA_9/DDR2_CA_0/DDR2_CA_0/DDR2_CA_6/DDR1_CA_7 DDR_M2_CA0 <22> DDR_M7_D0_3 DDR1_DQ_6_4/DDR1_DQ_6_4/DDR3_DQ_2_4/DDR7_DQ_0_4 DDR1_MA_12/DDR6_CA_1/DDR6_CA_1/DDR6_CA_5/DDR3_CA_7 DDR_M6_CA1 <24>
BW48 CC53 P60 AC60
DDR_M3_D0_1 DDR1_DQ_2_2/DDR0_DQ_6_2/DDR1_DQ_2_2/DDR3_DQ_0_2 NC/DDR3_CA_5/DDR3_CA_6/DDR3_CA_0/DDR1_CS_1 DDR_M3_CA0 <22> DDR_M7_D0_2 DDR1_DQ_6_3/DDR1_DQ_6_3/DDR3_DQ_2_3/DDR7_DQ_0_3 DDR1_MA_9/DDR6_CA_0/DDR6_CA_0/DDR6_CA_6/DDR3_CA_11 DDR_M6_CA0 <24>
CA47 CC47 N56 T53
DDR_M3_D0_0 BY50 DDR1_DQ_2_1/DDR0_DQ_6_1/DDR1_DQ_2_1/DDR3_DQ_0_1 NC/DDR3_CA_4/DDR3_CA_5/DDR3_CA_1/DDR1_CS_0 CE53 DDR_M3_CA1 <22> DDR_M7_D0_1 P57 DDR1_DQ_6_2/DDR1_DQ_6_2/DDR3_DQ_2_2/DDR7_DQ_0_2 NC/DDR7_CA_5/DDR7_CA_6/DDR7_CA_0/DDR3_CS_1 T47 DDR_M7_CA0 <24>
<22> DDR_M3_D1_[0..7] DDR_M3_D1_7 DDR1_DQ_2_0/DDR0_DQ_6_0/DDR1_DQ_2_0/DDR3_DQ_0_0 NC/DDR3_CA_3/DDR3_CA_4/DDR3_CS_1/DDR1_CA_0 DDR_M3_CS#1 <22> DDR_M7_D0_0 DDR1_DQ_6_1/DDR1_DQ_6_1/DDR3_DQ_2_1/DDR7_DQ_0_1 NC/DDR7_CA_4/DDR7_CA_5/DDR7_CA_1/DDR3_CS_0 DDR_M7_CA1 <24>
BJ50 CH46 Descending N58 W53
DDR_M3_D1_6 DDR1_DQ_3_7/DDR0_DQ_7_7/DDR1_DQ_3_7/DDR3_DQ_1_7 NC/DDR3_CA_2/DDR3_CA_3/DDR3_CS_0/DDR1_CA_6 DDR_M3_CS#0 <22> <24> DDR_M7_D1_[0..7] DDR_M7_D1_7 DDR1_DQ_6_0/DDR1_DQ_6_0/DDR3_DQ_2_0/DDR7_DQ_0_0 NC/DDR7_CA_3/DDR7_CA_4/DDR7_CS_1/DDR3_CA_0 DDR_M7_CS#1 <24>
BJ47 CK47 K50 AA46 Descending
DDR_M3_D1_5 BL48 DDR1_DQ_3_6/DDR0_DQ_7_6/DDR1_DQ_3_6/DDR3_DQ_1_6 DDR0_MA_10/DDR3_CA_1/DDR3_CA_1/DDR3_CA_5/DDR1_CA_8 CJ53 DDR_M3_CA5 <22> DDR_M7_D1_6 F58 DDR1_DQ_7_7/DDR1_DQ_7_7/DDR3_DQ_3_7/DDR7_DQ_1_7 NC/DDR7_CA_2/DDR7_CA_3/DDR7_CS_0/DDR3_CA_6 AC47 DDR_M7_CS#0 <24>
DDR_M3_D1_4 DDR1_DQ_3_5/DDR0_DQ_7_5/DDR1_DQ_3_5/DDR3_DQ_1_5 DDR0_BA_0/DDR3_CA_0/DDR3_CA_0/DDR3_CA_6/DDR1_CA_10 DDR_M3_CA6 <22> DDR_M7_D1_5 DDR1_DQ_7_6/DDR1_DQ_7_6/DDR3_DQ_3_6/DDR7_DQ_1_6 DDR1_MA_10/DDR7_CA_1/DDR7_CA_1/DDR7_CA_5/DDR3_CA_8 DDR_M7_CA5 <24>
BK53 F54 AC53
DDR_M3_D1_3 BP53 DDR1_DQ_3_4/DDR0_DQ_7_4/DDR1_DQ_3_4/DDR3_DQ_1_4 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 CV60 DDR_M7_D1_4 L48 DDR1_DQ_7_5/DDR1_DQ_7_5/DDR3_DQ_3_5/DDR7_DQ_1_5 DDR1_BA_0/DDR7_CA_0/DDR7_CA_0/DDR7_CA_6/DDR3_CA_10 DDR_M7_CA6 <24>
DDR_M3_D1_2 BN48 DDR1_DQ_3_3/DDR0_DQ_7_3/DDR1_DQ_3_3/DDR3_DQ_1_3 DDR0_MA_3/DDR0_CS_1/DDR0_CS_0/DDR0_CA_3/DDR0_CS_1 CR56 DDR_M0_CA3 <21> DDR_M7_D1_3 H56 DDR1_DQ_7_4/DDR1_DQ_7_4/DDR3_DQ_3_4/DDR7_DQ_1_4 DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AM57
DDR_M3_D1_1 BP47 DDR1_DQ_3_2/DDR0_DQ_7_2/DDR1_DQ_3_2/DDR3_DQ_1_2 DDR0_MA_4/DDR0_CS_0/DDR0_CA_2/DDR0_CA_2/DDR0_CA_12 CU48 DDR_M0_CA2 <21> DDR_M7_D1_2 K53 DDR1_DQ_7_3/DDR1_DQ_7_3/DDR3_DQ_3_3/DDR7_DQ_1_3 DDR1_MA_3/DDR4_CS_1/DDR4_CS_0/DDR4_CA_3/DDR2_CS_1 AJ56 DDR_M4_CA3 <23>
DDR_M3_D1_0 DDR1_DQ_3_1/DDR0_DQ_7_1/DDR1_DQ_3_1/DDR3_DQ_1_1 DDR0_MA_13/DDR1_CS_1/DDR1_CS_0/DDR1_CA_3/DDR0_CA_5 DDR_M1_CS#0 <21> DDR_M7_D1_1 DDR1_DQ_7_2/DDR1_DQ_7_2/DDR3_DQ_3_2/DDR7_DQ_1_2 DDR1_MA_4/DDR4_CS_0/DDR4_CA_2/DDR4_CA_2/DDR2_CA_12 DDR_M4_CA2 <23>
BP50 CM50 P50 AK48
DDR1_DQ_3_0/DDR0_DQ_7_0/DDR1_DQ_3_0/DDR3_DQ_1_0 DDR0_ODT_0/DDR1_CS_0/DDR1_CA_2/DDR1_CA_2/DDR0_CA_6 DDR_M1_CA2 <21> DDR_M7_D1_0 DDR1_DQ_7_1/DDR1_DQ_7_1/DDR3_DQ_3_1/DDR7_DQ_1_1 DDR1_MA_13/DDR5_CS_1/DDR5_CS_0/DDR5_CA_3/DDR2_CA_5 DDR_M5_CS#0 <23>
CJ57 P53 AE50
DDR0_ACT_N/DDR2_CS_1/DDR2_CS_0/DDR2_CA_3/DDR1_CA_9 CF56 DDR_M2_CS#0 <22> DDR1_DQ_7_0/DDR1_DQ_7_0/DDR3_DQ_3_0/DDR7_DQ_1_0 DDR1_ODT_0/DDR5_CS_0/DDR5_CA_2/DDR5_CA_2/DDR2_CA_6 AC57 DDR_M5_CA2 <23>
NC/DDR2_CS_0/DDR2_CA_2/DDR2_CA_2/DDR1_CA_2 DDR_M2_CA2 <22> DDR1_ACT_N/DDR6_CS_1/DDR6_CS_0/DDR6_CA_3/DDR3_CA_9 DDR_M6_CS#0 <24>
CH48 Y56
DDR0_PAR/DDR3_CS_1/DDR3_CS_0/DDR3_CA_3/DDR1_CA_3 DDR_M3_CA3 <22> NC/DDR6_CS_0/DDR6_CA_2/DDR6_CA_2/DDR3_CA_2 DDR_M6_CA2 <24>
CC50 AA48
DDR0_MA_2/DDR3_CS_0/DDR3_CA_2/DDR3_CA_2/DDR1_CA_1 DDR_M3_CA2 <22> DDR1_PAR/DDR7_CS_1/DDR7_CS_0/DDR7_CA_3/DDR3_CA_3 DDR_M7_CA3 <24>
T50
DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 DDR1_MA_2/DDR7_CS_0/DDR7_CA_2/DDR7_CA_2/DDR3_CA_1 DDR_M7_CA2 <24>
CV50
DDR0_CS_0/NC/DDR1_CS_1/DDR1_CA_4/DDR0_CA_4 CJ50 DDR_M1_CS#1 <21> DDR4 / LP4x / LP5_ascend / LP5_descend / DDR5 AM50
DDR0_MA_0/NC/DDR3_CS_1/DDR3_CA_4/DDR1_CA_5 CV57 DDR_M3_CA4 <22> DDR1_CS_0/NC/DDR5_CS_1/DDR5_CA_4/DDR2_CA_4 AC50 DDR_M5_CS#1 <23>
DDR0_MA_1/NC/DDR0_CS_1/DDR0_CA_4/DDR0_CS_0 CJ60 DDR_M0_CA4 <21> DDR1_MA_0/NC/DDR7_CS_1/DDR7_CA_4/DDR3_CA_5 AM60 DDR_M7_CA4 <24>
DDR0_MA_11/NC/DDR2_CS_1/DDR2_CA_4/DDR1_CA_11 DDR_M2_CS#1 <22> DDR1_MA_1/NC/DDR4_CS_1/DDR4_CA_4/DDR2_CS_0 DDR_M4_CA4 <23>
AB56
DDR0_ALERT# DDR1_MA_11/NC/DDR6_CS_1/DDR6_CA_4/DDR3_CA_12 DDR_M6_CS#1 <24>
BF61 RC342 1 @ 2 0_0201_5%
DDR0_ALERT_N BG60 1.0 remove DDR0_VREF_CA0 and TP288 BG57 DDR1_ALERT# RC343 1 @ 2 0_0201_5%
DDR0_VREF_CA0 DDR1_ALERT_N BG55
BG50 DDR_PG_CTRL 1 Trace width/Spacing >= 20mils DDR1_VREF_CA0
DDR_VTT_CTL DDR_DRAMRST# TP294 PAD~D
EE53 TP@ 1.0 remove DDR1_VREF_CA0 and TP293
DRAM_RESET#
A56
DDR_COMP_1 DDR_RCOMP ADL-P_BGA1744
B56 RC32 1 2
DDR_COMP_2 100_0201_1% @

ADL-P_BGA1744 Follow 633909_ADL_P_DDR4_SODIMM_1DPC_RVP_Rev0p7

@

B +1.065V_MEM UC1D B
REV0.6
AF27
AH20 RSVD_1
RSVD_2

1
AK22
RC33 AK40 RSVD_4
470_0402_5% AL30 RSVD_6
AL40 RSVD_7
Remove VTT CTRL RSVD_8
Due to LPDDR5 no need BG47

2
BG53 RSVD_9
DDR_DRAMRST# RC34 1 2 DDR_DRAMRST#_R DT42 RSVD_10
DDR_DRAMRST#_R <21,22,23,24> RSVD_13
0_0201_5% EE46
EF33 RSVD_15
CRB 0511 1
EH41 RSVD_16
CC5 RSVD_20
0.1U_0201_10V6K
2 XEMC@
ADL-P_BGA1744
627205_ADL P_PDG_Rev1.5 use 0.1U
20210905 change from 33P to 0.1u @
Reserve only (ESD request)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/5/30 2020/12/31 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(3/14)DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 8 of 121
5 4 3 2 1
 5 4 3 2 1

+3VALW_PRIM
check power level & TLS en or not? 1213 +3VALW_PRIM
SOC_GPP_B23 RC36 2 @ 1 4.7K_0201_5%
+3V_SPI SOC_GPP_C2
SOC_GPP_B23 RC465 1 @ 2 20K_0201_5% TLS CONFIDENTIALITY SOC_GPP_C2 4.7K_0201_5% 1 2 RC37
CPUNSSC CLOCK FREQ INTERNAL PD 20K
INTERNAL PD 20K HIGH: TLS CONFIDENTIALITY ENABLE 1 2 RC463
LOW: TLS CONFIDENTIALITY DISABLE(Default) 20K_0201_5% @
HIGH: 19.2 MHz (form internal divider)
LOW: 38.4 MHz (direct form crystal) (Default)
1

1
Internal PD 20K
RC38 RC39 RC40
4.7K_0201_5% 100K_0201_5% 100K_0201_5%
SOC_SPI_0_D0 1.A add RC800 and pop +3VS
BOOT HALT +3VALW_PRIM
2

2
INTERNAL PU RVP is different from EDS description 4.7K_0201_5% 1 @ 2 RC800
SOC_SPI_0_D0 HIGH: ENABLED
LOW: DISABLED SOC_SML0ALERT# 4.7K_0201_5% 1 @ 2 RC41
SOC_SPI_0_D2 SOC_SPI_0_D2
External pull-up is required. 20K_0201_5% 1 @ 2 RC464
SOC_SPI_0_D3 Recommend 100K if pulled up to 3.3V
75K if pulled up to 1.8V. 20200727
- Remove D0/D1/CLK intersheet UC1E SOC_SML0ALERT#
D INTERNAL PU INTERNAL PD 20K D
REV0.6
1

1
SOC_SPI_0_D3 SOC_SPI_0_CLK EG56 EL38 SOC_SMBCLK This is bit 0 (LSB) of a total of 4-bit encoded pin straps for boot configuration
External pull-up is required. SOC_SPI_0_D3 EC59 SPI0_CLK GPP_C0/SMBCLK EK38 SOC_SMBDATA Boot Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2 respectively).
RC313 RC312 RC311
Recommend 100K if pulled up to 3.3V SPI0_IO3 GPP_C1/SMBDATA
(Link to DDR)
4.7K_0201_5% 4.7K_0201_5% 100K_0201_5% SOC_SPI_0_D2 EC61 EN38 SOC_GPP_C2
@ @ @ 75K if pulled up to 1.8V. SOC_SPI_0_D1 EF59 SPI0_IO2 GPP_C2/SMBALERT#
INTERNAL PU SOC_SPI_0_D0 SPI0_MISO SOC_SML0CLK
EF57 EE38
SOC_SML0CLK <42,44,45>
2

1 SOC_SPI_0_CS#1 EG58 SPI0_MOSI GPP_C3/SML0CLK EF38 SOC_SML0DATA

T234 @ SPI0_CS1# GPP_C4/SML0DATA
(To
SOC_SML0DATA <42,44,45> TBT)
SOC_SPI_0_CS#0 EF61 EH38 SOC_SML0ALERT#
SOC_SPI_0_CS#2 EF56 SPI0_CS0# GPP_C5/SML0ALERT#
<66> SOC_SPI_0_CS#2 SPI0_CS2# SOC_SML1CLK
ET38
PROJECT_ID1 GPP_C6/SML1CLK SOC_SML1DATA SOC_SML1CLK <43,46> +3VS
FC28 ER38 (To PD controller)
GPP_E11/THC0_SPI1_CLK/GSPI0_CLK GPP_C7/SML1DATA SOC_GPP_B23 SOC_SML1DATA <43,46>
EF23 EF41
EE23 GPP_E2/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT# SOC_SMBDATA 1 2 2.2K_0402_5%
GPP_E1/THC0_SPI1_IO2
EMI RC42
RAM_ID0 EL23 DT49 ESPI_CLK RC50 1 EMC@ 2 33_0201_5% ESPI_CLK_R SOC_SMBCLK RC44 1 2 2.2K_0402_5%
+1.8VALW_PRIM GPP_E12/THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO GPP_A9/ESPI_CLK ESPI_IO3 ESPI_IO3_R ESPI_CLK_R <58>
EN23 DP52 RC51 1 2 33_0201_5%
PROJECT_ID0 GPP_E13/THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2 ESPI_IO2_R ESPI_IO3_R <58>
FA28 DT54 RC52 1 2 33_0201_5% 10P_0201_50V8J1 2 CC7
SOC_GPP_E17 GPP_E10/THC0_SPI1_CS#/GSPI0_CS0# GPP_A2/ESPI_IO2/SUSWARN#/SUSPWRDNACK ESPI_IO1 ESPI_IO1_R ESPI_IO2_R <58>
EY25 DT44 RC53 1 2 33_0201_5%
GPP_E17/THC0_SPI1_INT# GPP_A1/ESPI_IO1 ESPI_IO1_R <58>
1

SOC_GPP_E6 EH23 DP51 ESPI_IO0 RC54 1 2 33_0201_5% ESPI_IO0_R @RF@

GPP_E6/THC0_SPI1_RST# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0_R <58>
RC43 DP44 RF Suggestion
GPP_A4/ESPI_CS0# ESPI_CS# <58>
20K_0201_5% EN33 DT46
SOC_GPP_F15 EN36 GPP_F11/THC1_SPI2_CLK/GSPI1_CLK GPP_A23/ESPI_CS1# DT51 ESPI_RST#
05/13 Follow ADL_DDR4_RVP_rev07 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 GPP_A10/ESPI_RESET# ESPI_RST# <58>
GYRO_I2C_INT# EL36 DP47 +3VALW_PRIM
<60> GYRO_I2C_INT#
2

SOC_GPP_E6 ET33 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_A5/ESPI_ALERT0# DP54

<70> CR_PRSNT#_R GPP_F13/GSXSLOAD/THC1_SPI2_IO1/GSPI1_MISIO/I2C1A_SDA GPP_A6/ESPI_ALERT1# SOC_SML0CLK
EL31 499_0201_1% 1 2 RC45
GPP_F12/GSXDOUT/THC1_SPI2_IO0/GSPI1_MOSI/I2C1A_SCL
1

RAM_ID1 EL33 SOC_SML0DATA 499_0201_1% 1 2 RC46

RC48 Signal: SOC_GPP_E6 RAM_ID3 ET36 GPP_F16/GSXCLK/THC1_SPI2_CS#/GSP1_CS0# SOC_SML1CLK 1K_0201_5% 1 2 RC47
Usage: JTAG ODT Disable RAM_ID2 ER33 GPP_F18/THC1_SPI2_INT# SOC_SML1DATA 1K_0201_5% 1 2 RC49
4.7K_0201_5%
@ NO INTERNAL PU/PD GPP_F17/THC1_SPI2_RST#
0=> JTAG ODT is disabled 1 CL_CLK EE26
1=> JTAG ODT is enabled T324 @
2

1 CL_DATA EF26 CL_CLK CC9

T325 @ CL_RST# CL_DATA ESPI_CLK_R +1.8VALW_PRIM
T326 @ 1 EH26 1 2
CL_RST#
10P_0201_50V8J
XEMC@ ESPI_CS# RC55 2 @ 1 10K_0201_5%
SOC_SPI_0_CLK ADL-P_BGA1744
CC8 2 1 10P_0201_50V8J EMC Suggestion
@
XEMC@ EMC Suggestion
SOC_SPI_0_CLK RC56 2 GLITCH@1 100K_0201_5%
ESPI_RST# RC57 2 GLITCH@1 75K_0201_5%

+3VALW_PRIM
C C
DDS Strap(GPIO) BIOS Strap(GPIO)
+3VALW_PRIM +3VALW_PRIM
Follow ADL_DDR4_RVP_rev07 for Glitch

PROJECT ID
1

1
From EC MAF - Master Attached Flash
GPP_F15 RC64 RC65 (For share ROM) Single SPI Flash attached to SPI Bus
1

GSYNC@ 10K_0402_5% 10K_0402_5% Project_ID1 Project_ID0 EC FW access through eSPI Bus

DDS sku RC60 RC791
1
2

10K_0402_5% 10K_0402_5% PROJECT_ID0 HH67A

PROJECT_ID1 1 1
non DDS sku 0 SOC_GPP_F15 SOC_GPP_E17 TBD 1 0
1 2

1 2

NGSYNC@ TBD 0 1
1

RC63 RC792
10K_0402_5% 10K_0402_5% RC66 RC67 TBD
@ 10K_0402_5% 10K_0402_5% 0 0
@ @
2

X76918BOL58, ALT. GROUP PARTS LPDDR5 HYNIX 8G HH67A

X76DH8G@ X76DH8G@ X76DH8G@ X76DH8G@ X76DH8G@ X76DH8G@ X76DH8G@ X76DH8G@
UD1 UD2 UD3 UD4 RC785 RC786 RC61 RC62
Hynix8G Hynix8G Hynix8G Hynix8G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA0000E9Q10 SA0000E9Q10 SA0000E9Q10 SA0000E9Q10 SD028100280 SD028100280 SD028100280 SD028100280

X76918BOL59, ALT. GROUP PARTS LPDDR5 MICRON 8G HH67A

X76DM8G@ X76DM8G@ X76DM8G@ X76DM8G@ X76DM8G@ X76DM8G@ X76DM8G@ X76DM8G@
UD1 UD2 UD3 UD4 RC783 RC786 RC61 RC62 +3VALW_PRIM
Micron8G Micron8G Micron8G Micron8G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA0000EA520 SA0000EA520 SA0000EA520 SA0000EA520 SD028100280 SD028100280 SD028100280 SD028100280

X76918BOL60, ALT. GROUP PARTS LPDDR5 HYNIX 16G HH67A

1

* SPI0 1 load topology: *** SPI0 3 load topology:

1
X76DH16G@ X76DH16G@ X76DH16G@ X76DH16G@ X76DH16G@ X76DH16G@ X76DH16G@ X76DH16G@
UD1 UD2 UD3 UD4 RC785 RC786 RC61 RC59 RC783 RC784 RC58 RC59 R1 is required 33 ohm±5% for 1.8V, 62 ohm±5% for 3.3V. R1 is required 15 ohm±10% for 1.8V, 33 ohm±5% for 3.3V.
Hynix16G Hynix16G Hynix16G Hynix16G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R2 is required 10 ohm for 1.8V and 3.3V.
SA0000E9R10 SA0000E9R10 SA0000E9R10 SA0000E9R10 SD028100280 SD028100280 SD028100280 SD028100280 @ @ @ @ ** SPI0 2 load topology: It is an optional to have R2 on the channel. It can be removed to reduce BOM cost.
2

RAM_ID0
X76918BOL61, ALT. GROUP PARTS LPDDR5 MICRON 16G HH67A 2 R1 is required 33 ohm±5% for 1.8V, 56 ohm±5% for 3.3V.

2
B
RAM_ID1 B
X76DM16G@ X76DM16G@ X76DM16G@ X76DM16G@ X76DM16G@ X76DM16G@ X76DM16G@ X76DM16G@ RAM_ID2 R2 is required 5 ohm for 1.8V and 3.3V. **** CS# does not need series resistor
UD1 UD2 UD3 UD4 RC783 RC786 RC61 RC59 RAM_ID3 It is an optional to have R2 on the channel. It can be removed to reduce BOM cost.
Micron16G Micron16G Micron16G Micron16G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA0000EA720 SA0000EA720 SA0000EA720 SA0000EA720 SD028100280 SD028100280 SD028100280 SD028100280
+3VALW_PRIM 3mA +3V_SPI
X76918BOL62, ALT. GROUP PARTS LPDDR5 SAM 16G HH67A
1

1
X76DS16G@ X76DS16G@ X76DS16G@ X76DS16G@ X76DS16G@ X76DS16G@ X76DS16G@ X76DS16G@ RC785 RC786 RC61 RC62 RC68 1 @ 2 0_0402_5%
UD1 UD2 UD3 UD4 RC785 RC784 RC61 RC62 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
Samsung16G Samsung16G Samsung16G Samsung16G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ @ @ @
SA0000E9W10 SA0000E9W10 SA0000E9W10 SA0000E9W10 SD028100280 SD028100280 SD028100280 SD028100280 R1
2

X76918BOL63 , ALT. GROUP PARTS LPDDR5 HYNIX 32G HH67A SOC_SPI_0_CLK SOC_SPI_0_CLK_R1 SOC_SPI_0_CLK_R
X76DH32G@ X76DH32G@ X76DH32G@ X76DH32G@ X76DH32G@ X76DH32G@ X76DH32G@ X76DH32G@ RC769 1 @ 2 0_0201_5% RC70 1 2 62_0201_1%
UD1 UD2 UD3 UD4 RC785 RC784 RC61 RC59 SOC_SPI_0_D0 RC770 1 @ 2 0_0201_5% SOC_SPI_0_D0_R1 RC72 1 2 62_0201_1% SOC_SPI_0_D0_R
Hynix32G Hynix32G Hynix32G Hynix32G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% SOC_SPI_0_D1 RC771 1 @ 2 0_0201_5% SOC_SPI_0_D1_R1 RC74 1 2 62_0201_1% SOC_SPI_0_D1_R
SA0000E9S10 SA0000E9S10 SA0000E9S10

X76918BOL64 ,ALT. GROUP PARTS LPDDR5 MICRON 32G HH67A

X76DM32G@ X76DM32G@ X76DM32G@
SA0000E9S10

X76DM32G@
SD028100280

X76DM32G@
SD028100280

X76DM32G@
SD028100280

X76DM32G@
SD028100280

X76DM32G@
SOC_SPI_0_D2
SOC_SPI_0_D3
RC772 1
RC773 1
@
@
2
2
0_0201_5%
0_0201_5%
RC75
RC78
1
1
2
2
62_0201_1%
62_0201_1%
SOC_SPI_0_D2_R
SOC_SPI_0_D3_R
20210604
remove 16M SPI ROM
RAM_ID RAM_ID3 RAM_ID2 RAM_ID1 RAM_ID0 Rank PartNumber - Description
UD1 UD2 UD3 UD4 RC783 RC784 RC61 RC59
Micron32G Micron32G Micron32G Micron32G 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% Hynix8G SA0000E9Q10, S IC D5 16G/6400 H9JCNNNBK3MLYR-N6E ABO!
0 0 0 0 0 1R SOC_SPI_0_D1_R1 <66>
SA0000DUQ20 SA0000DUQ20 SA0000DUQ20 SA0000DUQ20 SD028100280 SD028100280 SD028100280 SD028100280
SOC_SPI_0_D0_R1 <66>
Micron8G 1 0 0 0 1 1R SA0000EA520, S IC D5 16G MT62F512M32D2DR-031 WT:BABO! SOC_SPI_0_CLK_R1 <66>
X76918BOL65 ,ALT. GROUP PARTS LPDDR5 SAM 32G HH67A Samsung16G 2 0 0 1 0 1R SA0000E9W10, S IC D5 32G/6400 K3LKBKB0BM-MGCP ABO !
X76DS32G@ X76DS32G@ X76DS32G@ X76DS32G@ X76DS32G@ X76DS32G@ X76DS32G@ X76DS32G@
UD1 UD2 UD3 UD4 RC785 RC786 RC58 RC59 TBD 3 0 0 1 1 1R
Samsung32G
SA0000E9Y10
Samsung32G
SA0000E9Y10
Samsung32G
SA0000E9Y10
Samsung32G
SA0000E9Y10
10K_0402_5%
SD028100280
10K_0402_5%
SD028100280
10K_0402_5%
SD028100280
10K_0402_5%
SD028100280 TBD
TBD
4 0 1 0 0 1R SPI ROM
5 0 1 0 1 1R
TBD 20210511 - 32M SPI ROM (WSON8)
6 0 1 1 0 1R +3V_SPI
TBD UC4
7 0 1 1 1 1R SOC_SPI_0_CS#0 1 8 +3V_SPI
/CS VCC
Hynix16G 8 1 0 0 0 2R SA0000E9R10, S IC D5 32G/6400 H9JCNNNCP3MLYR-N6E ABO!
SOC_SPI_0_D1_R 2 7 SOC_SPI_0_D3_R
IO1 IO3
Micron16 9 1 0 0 1 2R SA0000EA720, S IC D5 32G MT62F1G32D4DR-031 WT:B ABO !
SOC_SPI_0_D2_R 3 6 SOC_SPI_0_CLK_R
IO2 CLK
Hynix32G 10 1 0 1 0 2R SA0000E9S10, S IC D5 64G/6400 H9JCNNNFA5MLYR-N6E ABO!
A 4 5 SOC_SPI_0_D0_R A
GND IO0
Micron32G 11 1 0 1 1 2R SA0000DUQ20, S IC D5 2G32 MT62F2G32D8DR-031 WT:B ABO!
9
PAD
Samsung32G 12 1 1 0 0 2R SA0000E9Y10, S IC D5 64G/6400 K3LKCKC0BM-MGCP ABO !
XM25QH256BXIQTF_WSON8_8X6
TBD 13 1 1 0 1 2R SA00009RI10
TBD 14 1 1 1 0 2R change P/N from SA0000CW300 to SA00009RI10
TBD 15 1 1 1 1 2R

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(4/14)SPI,ESPI,SMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 9 of 121
5 4 3 2 1
 5 4 3 2 1

UC1G
REV0.6
EY34 ER56 HDA_BIT_CLK
GPP_D19/I2S_MCLK1_OUT GPP_R0/HDA_BCLK/I2S0_SCLK/DMIC_CLK_B0/HDAPROC_BCLK EP60 HDA_SYNC
1.0 remove level shift, R4091 and R4092 change to RS EV53 GPP_R1/HDA_SYNC/I2S0_SFRM/DMIC_CLK_B1 ER57 HDA_SDOUT
EY53 GPP_S0/SNDW0_CLK/I2S1_SCLK GPP_R2/HDA_SDO/I2S0_TXD/HDAPROC_SDO ER59 HDA_SDIN0
GPP_S1/SNDW0_DATA/I2S1_SFRM GPP_R3/HDA_SDI0/I2S0_RXD/HDAPROC_SDI
D D
0_0201_5% 2 @ 1 R4091 PCH_DMIC_CLK FA50 ER53 HDA_RST#
<38> PCH_DMIC_CLK_L PCH_DMIC_DATA GPP_S2/SNDW1_CLK/DMIC_CKL_A0/I2S1_TXD GPP_R4/HDA_RST#/I2S2_SCLK/DMIC_CLK_A0
0_0201_5% 2 @ 1 R4092 FC50 ET53
<38> PCH_DMIC_DATA_L GPP_S3/SNDW1_DATA/DMIC_DATA0/I2S1_RXD GPP_R5/HDA_SDI1/I2S2_SFRM/DMIC_DATA0 EB44
EV50 GPP_R6/I2S2_TXD/DMIC_CLK_A1 EB46
EY50 GPP_S4/SNDW2_CLK/DMIC_CLK_B0 GPP_R7/I2S2_RXD/DMIC_DATA1
GPP_S5/SNDW2_DATA/DMIC_CLK_B1 DV51
EW48 GPP_A11/PMC_I2C_SDA DV47 SOC_BT_ON R71 1 @ 2 0_0402_5%
GPP_S6/SNDW3_CLK/DMIC_CLK_A1 GPP_A13/PMC_I2C_SCL BT_ON <53>
EY48
GPP_S7/SNDW3_DATA/DMIC_DATA1 FA53 SNDW _RCOMP RC90 1 2 200_0201_1%
SNDW_RCOMP_1 FC53
SNDW_RCOMP_2

ADL-P_BGA1744
@

20200819
HDA_SDOUT HDA_SYNC CC12 @RF@1 2 22P_0201_50V8J
HDA for AUDIO - Remove RC180 BOM config , must pop of PDG . FLASH DESCRIPTOR SECURITY OVERRIDE
HDA_SDOUT_R RC91 1 2 33_0201_5% HDA_SDOUT INTERNAL PD 20K HDA_BIT_CLK CC13 @RF@1 2 22P_0201_50V8J
<56> HDA_SDOUT_R HDA_BIT_CLK_R RC92 1 2 33_0201_5% HDA_BIT_CLK
To Enable ME Override HIGH: OVERRIDEN
<56> HDA_BIT_CLK_R LOW: SECURITY MEASURES NOT OVERRIDEN (DEFAULT)
HDA_SYNC_R RC93 1 2 33_0201_5% HDA_SYNC HDA_SDOUT CC14 @RF@1 2 22P_0201_50V8J
<56> HDA_SYNC_R HDA_RST#_R HDA_RST#
C RC94 1 2 33_0201_5% C
<56> HDA_RST#_R HDA_SDIN0 HDA_SDIN0 CC15 @RF@1 2 22P_0201_50V8J
<56> HDA_SDIN0
HDA_RST# CC16 @RF@1 2 22P_0201_50V8J
R72 1 2 0_0201_5% HDA_SDOUT
<58> ME_EN
PCH_DMIC_CLK CC17 @RF@1 2 22P_0201_50V8J

100K_0201_5% 1 GLITCH@2 RC95 HDA_BIT_CLK PCH_DMIC_DATA CC18 @RF@1 2 22P_0201_50V8J

100K_0201_5% 1 GLITCH@2 RC96 HDA_RST# RC97 1 @ 2 100K_0201_5%

Close SOC

572631_ICL_PCH_LP_EDS_Vol_1_Rev_0p7
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Follow Need to sync with codec VDDIO
627205_ADL P_PDG for Glitch

CC19 2 1 10P_0201_50V8J HDA_BIT_CLK_R

XEMC@ EMC Suggestion

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(5/14)HDA,SNDW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 10 of 121
5 4 3 2 1
 5 4 3 2 1

+3VS
Follow
627205_ADL P_PDG_Rev0p7 for Glitch
CLKREQ_GPU# 10K_0201_5% 1 2 RC99
+3VALW UC1K CLKREQ_WLAN# 10K_0201_5% 1 2 RC100
REV0.6 CLKREQ_LAN# 10K_0201_5% 1 2 RC101
DP1 DY46 SATA_GP1 1 CLKREQ_SSD1# 10K_0201_5% 1 2 RC102
PM_SLP_S0# CLKOUT_PCIE_P6 GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B# @ T318 CLKREQ_SSD2#
RC106 1 2 100K_0201_5% DP3 EV22 5/28 remove SSD port3 10K_0201_5% 1 2 RC240
CLKOUT_PCIE_N6 GPP_E0/SATAXPCIE0/SATAGP0/SRCCLKREQ9# EY22 GPP_E16 1 CLKREQ_CR# 10K_0201_5% 1 2 RC796
SLP_SUS# CLK_PCIE_CR GPP_E16/RSVD_TP/SRCCLKREQ8# @ T319
RC450 1 GLITCH@2 100K_0201_5% <70> CLK_PCIE_CR DU5 EB54 1.0 intel recommend
RC451 1 GLITCH@2 100K_0201_5% PM_SLP_S5# CLK_PCIE_CR# DU6 CLKOUT_PCIE_P5 GPP_A8/SRCCLKREQ7# EF31 SOC_ALS_INT# 1K_0201_5% 1 @ 2 RC776
PM_SLP_S4# <70> CLK_PCIE_CR# CLKOUT_PCIE_N5 GPP_F19/SRCCLKREQ6# CLKREQ_CR#
RC108 1 GLITCH@2 100K_0201_5% ET43
PM_SLP_S3# CLK_PCIE_SSD2 GPP_H23/SRCCLKREQ5# CLKREQ_SSD2# CLKREQ_CR# <70> CarReader
RC110 1 GLITCH@2 100K_0201_5% DP5 ER48
PM_SLP_A# <69> CLK_PCIE_SSD2 CLK_PCIE_SSD2# CLKOUT_PCIE_P4 GPP_H19/SRCCLKREQ4# CLKREQ_SSD1# CLKREQ_SSD2# <69> SSD2
RC452 1 GLITCH@2 100K_0201_5% SSD2 DP6 FC34
PM_SLP_LAN# <69> CLK_PCIE_SSD2# CLKOUT_PCIE_N4/UFS_REF_CLK GPP_D8/SRCCLKREQ3# CLKREQ_LAN# CLKREQ_SSD1# <68> SSD1
RC453 1 GLITCH@2 100K_0201_5% FC31
PM_SLP_WLAN# CLK_PCIE_SSD1 GPP_D7/SRCCLKREQ2# CLKREQ_WLAN# CLKREQ_LAN# <51> GLAN +3VALW
RC454 1 GLITCH@2 100K_0201_5% DN10 FB36
<68> CLK_PCIE_SSD1 CLK_PCIE_SSD1# CLKOUT_PCIE_P3 GPP_D6/SRCCLKREQ1# CLKREQ_GPU# CLKREQ_WLAN# <53>WLAN
SSD1 DN11 FB29
<68> CLK_PCIE_SSD1# CLKOUT_PCIE_N3 GPP_D5/SRCCLKREQ0# CLKREQ_GPU# <26> dGPU
CLK_PCIE_LAN DR4 EV6 SOC_XTAL38.4_OUT
D <51> CLK_PCIE_LAN CLK_PCIE_LAN# CLKOUT_PCIE_P2 XTAL_OUT SOC_XTAL38.4_IN D
GLAN <51> CLK_PCIE_LAN# DR6 EV8
05/18 update CLKOUT_PCIE_N2 XTAL_IN PM_BATLOW# 10K_0201_5% 2 1 RC107
CLK_PCIE_WLAN DU1 EJ61 SUSCLK WAKE# 1K_0201_5% 1 2 RC109
+3VALW <53> CLK_PCIE_WLAN CLK_PCIE_WLAN# CLKOUT_PCIE_P1 GPD8/SUSCLK SUSCLK <53> LAN_WAKE#
WLAN <53> CLK_PCIE_WLAN#
DU3 10K_0201_5% 2 1 RC111
CLKOUT_PCIE_N1 EV58 SOC_RTCX2 SPIVCCIOSEL SPIVCCIOSEL 1K_0201_5% 1 @ 2 RC112
RC116 1 2 10K_0201_5% CLK_PEG_VGA DT10 RTCX2 EV56 SOC_RTCX1 3.3V / 1.8V SELECT FOR SPI
<25> CLK_PEG_VGA CLK_PEG_VGA# CLKOUT_PCIE_P0 RTCX1 HIGH: 1.8V
dGPU DT11 4.7K_0201_5% 2 1 RC113
SYS_RESET# <25> CLK_PEG_VGA# CLKOUT_PCIE_N0 SOC_RTCRST# LOW: 3.3V
CC20 2 1 FA55 1.0 SPIVCCIOSEL PD change from 10K to 4.7K
XCLK_BIASREF DJ3 RTCRST# SOC_SRTCRST# Follow 633909_ADL_P_DDR4_RVP_Rev_0p7 by intel recommend and PDG
XEMC@ 0.1U_0201_10V6K 2 1 FB56
RC114 60.4_0402_1% XCLK_BIASREF SRTCRST#
CC21 2 1 SYS_PWROK EB52 SUSCLK 1K_0201_5% 1 @ 2 RC115
XEMC@ 0.1U_0201_10V6K GPP_A7/SRCCLK_OE7# EW23 SOC_ALS_INT#
GPP_E15/RSVD_TP/SRCCLK_OE8# SOC_ALS_INT# <60>
CC121 2 1 PCH_PWROK
Follow
XEMC@ 0.1U_0201_10V6K
ADL-P_BGA1744 633909_ADL_P_DDR4_SODIMM_1DPC_RVP
CC22 1 2 SOC_PLTRST# @ +3VALW
EMC@ 100P_0201_50V8J

1
05/27 update
ESD Suggestion Signal: TBT_RETIMER_RESET# RC794
Usage: Reserved 4.7K_0201_5%
This strap has a 20 kohm ± 30% internal pull-down. @
This strap should sample LOW. CPU_C10_GATE# 1 2
There should NOT be any on-board device driving it to opposite direction during strap sampling.

2
+3VALW RC118 100K_0201_5%
Notes: TBT_RETIMER_RESET#
RC468 1 2 100K_0201_5% AC_PRESENT_R 1. The internal pull-down is disabled after DSW_PWROK is high.
2. This signal is in the DSW well. Follow

1
RC469 1 2 100K_0201_5% PCH_DPWROK SLP_DRAM# 1 2
RC795 RC120 100K_0201_5%
LA-L111P R01(DDR4)
RC470 1 2 100K_0201_5% SYS_PWROK UC1L 20K_0201_5%
REV0.6 +3VALW_PRIM @
RC471 1 2 100K_0201_5% PCH_PWROK SLP_SUS# EN53 EM61 PBTN_OUT#_R EC_VCCST_PG 1 2
<58> SLP_SUS#

2
SLP_SUS# GPD3/PWRBTN# EM56 PM_BATLOW# CC23 XEMC@
PM_SLP_S5# EG60 GPD0/BATLOW# EJ59 AC_PRESENT_R SOC_PD_INT# RT1126 2 1 10K_0201_5% 0.1U_0201_10V6K
20210825 PM_SLP_S4# EP56 GPD10/SLP_S5# GPD1/ACPRESENT 5/25
follow HH514 add <16,91> PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# SOC_PD_INT# ESD Suggestion
EM59 EA56
<16> PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3# GPP_B11/PMCALERT# CPU_C10_GATE# SOC_PD_INT# <43,46> SOC_RTCX1
EM57 ER46
PM_SLP_WLAN# EJ57 GPD6/SLP_A# GPP_H18/PROC_C10_GATE# ET48 SX_EXIT_HOLDOFF# 1
+RTCVCC GPD9/SLP_WLAN# GPP_H3/SX_EXIT_HOLDOFF# @ T351
PM_SLP_S0# DW59 ET51 WAKE# SOC_RTCX2
<66> PM_SLP_S0# PM_SLP_LAN# GPP_B12/SLP_S0# WAKE#
EK53
C SOC_SRTCRST# SLP_LAN# LAN_WAKE# RC129 C
RC124 1 2 20K_0201_5% EP58
EC_RSMRST# EH53 GPD2/LAN_WAKE# EJ56 LAN_DISABLE_N 2 1
<58> EC_RSMRST# SYS_RESET# RSMRST# GPD11/LANPHYPC LAN_DISABLE_N <51>
CC24 1 2 1U_0201_6.3V6M CLR ME EK26
SOC_PLTRST# DW57 SYS_RESET# EK60 TBT_RETIMER_RESET#
GPP_B13/PLTRST# GPD7 10M_0201_1%

2
PCH_DPWROK EE48 FA22 SLP_DRAM#
<11,58> PCH_DPWROK SYS_PWROK DSW_PWROK GPP_E8/SLP_DRAM#
EK23 RC127 RC133
SOC_RTCRST# <58> SYS_PWROK PCH_PWROK SYS_PWROK EC_VCCST_PG
RC125 1 2 20K_0201_5% EH51 DJ8 @ 0_0201_5% @ 0_0201_5%
SOC_RTCRST# <58> <58> PCH_PWROK PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE VCCST_OVERRIDE_R
DK4 1 @ 2
CC25 1 2 1U_0201_6.3V6M SM_INTRUDER# DY44 VCCST_OVERRIDE RC126 0_0201_5%

1
SPIVCCIOSEL EL53 INTRUDER# EH28 GPP_F20 1
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# @ T320
JCMOS1 1 @ 2 0_0603_5% CLR CMOS EH31
T242 @ 1 H_PROCPWRGD BG11 GPP_F21/EXT_PWR_GATE2# YC1 use special footprint for co-lay

SOC_RTCX2_R

SOC_RTCX1_R
PROCPWRGD
SM_INTRUDER# YC1
RC128 1 2 1M_0201_5%
PDG 6.2.5 2 1
ADL-P_BGA1744
INTRUDER# should have a weak external pull-up to VccRTC 32.768KHZ_12.5_X1A000171000118
@ 2012@
VCCSTPWRGOOD_TGSS VCCST_OVERRIDE_R YC3
RC130 1 @ 2 0_0201_5% <15> VCCSTPWRGOOD_TGSS 1 @ 2 SJ100015U00
RC131 0_0201_5%
RC132 1 2 100K_0201_5% EC_RSMRST# 2 1
32.768KHZ_12.5PF_X1A00014100030
CC173 1 2 0.1U_0201_10V6K 3215@
XEMC@ ESD function <58> AC_PRESENT RC134 1 @ 2 0_0201_5% AC_PRESENT_R 2 SJ10000PW00 2
RC135 1 @ 2 0_0201_5% PBTN_OUT#_R CC26 CC27
<58> PBTN_OUT#
18P_0201_50V8J 18P_0201_50V8J
DC2 1 1
+1.05V_PROC PM_SLP_S4# 2 1

From EC(open-drain) RB751S-40_SOD523-2 tCPU22/ tPCH28b

1

RC137 DC3
1K_0201_5% EC_VCCST_PG_R 2 SOC_XTAL38.4_IN
DC4 1 PM_SLP_S3#
PM_SLP_S3# 2 PCH_PWROK 3 SOC_XTAL38.4_OUT
2

EC_VCCST_PG_R RC138 1 2 60.4_0201_1% EC_VCCST_PG 1 PCH_DPWROK RC136 1 2 200K _0201_1%

<58> EC_VCCST_PG_R SLP_SUS# PCH_DPWROK <11,58>
3 LRB715FT1G_SOT323-3
@

1
LRB715FT1G_SOT323-3
tPLT17 05/18 follow TD team RC139 RC140
B 33_0201_5% EMI 33_0201_5% B
DC14 DC5 EMC@ EMC@
+1.8V_PROC_EN follow TD team change pop RC143 2 1 SLP_SUS#
<58,97> VR_ON
VR_ON 2 1 PM_SLP_S3#

2
20210719

SOC_XTAL38.4_OUT_R

SOC_XTAL38.4_IN_R
RB751S-40_SOD523-2 RB751S-40_SOD523-2
SUSP# RC141 1 @ 2 0_0201_5% +3VALW
<16,38,39,40,58,69,72,78,85,91> SUSP# SCS00006300 @
UC5
PM_SLP_S3# RC143 1 2 0_0201_5% 1 5 DC13 DC15
A VCC EC_RSMRST# 2 EC_RSMRST# 2
VCCIN_AUX_CORE_VID 2 1 SPOK_3V 1 SPOK_5V
B PCH_DPWROK SPOK_3V <58,87,90> PCH_DPWROK SPOK_5V <43,46,58,87,88>
3 3
3 4 YC2
GND Y +1.8V_PROC_EN <90> LRB715FT1G_SOT323-3 LRB715FT1G_SOT323-3 1 3
20210825
U74LVC1G08G-AL5-R_SOT353-5 SCS00008E00 DVT add for tPCH12/tPCH14 2 2 4 2
CC28
RC144 1 @ 2 0_0201_5% 10P_0201_50V8J 38.4MHZ_10PF_8Y38420005 CC29
10P_0201_50V8J
1 1

+3VALW 1.0 add MOS for auto load leakage

3.3V
VCCST_EN
2

RC798 EC_VCCST_PG_R
10K_0201_5%
DC6 PCH PLTRST Buffer
6

2 RC150 1 @ 2 0_0201_5%
<17,95> VCCIN_AUX_CORE_VID0
1

1 3.3V EC_VCCST_PG_R# 2
D
G QC2B
3 VCCIN_AUX_CORE_VID <16> 3.3V S
PJT138KA 2N SOT363-6
<17,95> VCCIN_AUX_CORE_VID1
3

+3VS
1

PM_SLP_S3#
D
LRB715FT1G_SOT323-3 5 G CC174 @
S 1 2
PJT138KA 2N SOT363-6
4

5
+3VALW_PRIM QC2A UC8 0.1U_0201_10V6K
SOC_PLTRST# 1

P
100K_0201_5% 1 2 RC147 VCCST_OVERRIDE_LS VCCST_OVERRIDE_LS <16> B 4 PLT_RST_R#
VCCST_OVERRIDE_N Y PLT_RST_R# <26,42,44,45,51,53,66,68,69,70>
100K_0201_5% 1 2 RC148 2
A

G
2
Gate

1
6 NL17SZ08EDFT2G SOT-353 5P AND GATE

3
100K_0201_5% 1 2 RC149 VCCST_OVERRIDE_R D 1 VR_ON RC455 SA0000BJI00
A Drain 100K_0201_5% A
3 @ GLITCH@
VCCST_OVERRIDE_N 2 Source QC3

2
G LBSS139WT1G_SC70-3
SB00001GC00
3 QC1A
D S PJT7838_SOT363-6
1

VCCST_OVERRIDE_R 5
G

QC1B
S
4
PJT7838_SOT363-6 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

TGL use single MOS for sequnce THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(6/14)CLK,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 11 of 121
5 4 3 2 1
 5 4 3 2 1

+3VS

UC1F
REV0.6
RC456 1 @ 2 10K_0201_5% SOC_DGPU_HOLD_RST# UART_2_CTXD_DRXD EN48 EY28 PANEL_OD_EN
<58> UART_2_CTXD_DRXD UART_2_CRXD_DTXD EN46 GPP_H11/UART0_TXD/M2_SKT2_CFG1 GPP_D14/ISH_UART0_TXD/I2C4B_SCL EV28 SOC_SLP_DS0# PANEL_OD_EN <38>
<58> UART_2_CRXD_DTXD GPP_H10/UART0_RXD/M2_SKT2_CFG0 GPP_D13/ISH_UART0_RXD/I2C4B_SDA SOC_SLP_DS0# <44>
RC797 1 VGA@ 2 10K_0201_5% SOC_DGPU_PWR_EN EL41 EY36 SOC_SLP_DS2#
SOC_GC6_FB_EN EK41 GPP_H13/I2C7_SCL/UART0_CTS#/M2_SKT2_CFG3/ISH_GP7B/DEVSLP1B GPP_D16/ISH_UART0_CTS#/I2C7B_SCL EW36 SOC_SLP_DS2# <42>
1.0 add RC797 for SOC_DGPU_PWR_EN GPP_H12/I2C7_SDA/UART0_RTS#/M2_SKT2_CFG2/ISH_GP6B/DEVSLP0B GPP_D15/ISH_UART0_RTS#/I2C7B_SDA
D SOC_DGPU_PWR_EN PSR2_MODE D
EW30 FA34
<26> SOC_DGPU_PWR_EN SOC_DGPU_HOLD_RST# EV34 GPP_D18/UART1_TXD/ISH_UART1_TXD GPP_D3/ISH_GP3/BK3/SBK3 EY30 PEN_PDCT# PSR2_MODE <39>
<26> SOC_DGPU_HOLD_RST# GPP_D17/UART1_RXD/ISH_UART1_RXD GPP_D2/ISH_GP2/BK2/SBK2 PEN_IRQ# PEN_PDCT# <60>
20200722 - Add for TBT4 EY31
I2C_0_SCL EH46 GPP_D1/ISH_GP1/BK1/SBK1 EV31 PEN_RST# PEN_IRQ# <60>
<60> I2C_0_SCL I2C_0_SDA GPP_H5/I2C0_SCL GPP_D0/ISH_GP0/BK0/SBK0 PEN_RST# <60>
ALS <60> I2C_0_SDA EF46
GPP_H4/I2C0_SDA DR61 GPP_RCOMP RC151 1 2
+3VS I2C_1_SCL EH43 GPPC_RCOMP 200_0201_1%
<66> I2C_1_SCL I2C_1_SDA GPP_H7/I2C1_SCL
TouchPad EF43
<66> I2C_1_SDA GPP_H6/I2C1_SDA
(For R-BOM) I2C_2_SCL DT57
<60> I2C_2_SCL I2C_2_SDA GPP_B6/ISH_I2C0_SCL/I2C2_SCL
Gyro DT56
For EC Debug UART / MIPI60 <60> I2C_2_SDA GPP_B5/ISH_I2C0_SDA/I2C2_SDA
RC153 1 2 49.9K_0201_1% UART_2_CRXD_DTXD I2C_3_SCL DR56
<38> I2C_3_SCL I2C_3_SDA GPP_B8/ISH_I2C1_SCL/I2C3_SCL
TouchScreen DR58
UART_2_CTXD_DRXD <38> I2C_3_SDA GPP_B7/ISH_I2C1_SDA/I2C3_SDA
RC154 1 2 49.9K_0201_1%
I2C_4_SCL EN43
<60> I2C_4_SCL I2C_4_SDA GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
EMR EL43
<60> I2C_4_SDA GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
+3VS check power domain DN60
DN57 GPP_B17/I2C5_SCL/ISH_I2C2_SCL
RC774 1 ALS@ 2 1K_0201_5% I2C_0_SCL GPP_B16/I2C5_SDA/ISH_I2C2_SDA
RC775 1 ALS@ 2 1K_0201_5% I2C_0_SDA

1 Gyro@ 2 1K_0201_5% I2C_2_SCL ADL-P_BGA1744

RC777
RC778 1 Gyro@ 2 1K_0201_5% I2C_2_SDA @

RC779 1 TS@ 2 1K_0201_5% I2C_3_SCL

RC780 1 TS@ 2 1K_0201_5% I2C_3_SDA

RC781 1 EMR@ 2 1K_0201_5% I2C_4_SCL

RC782 1 EMR@ 2 1K_0201_5% I2C_4_SDA

+3VALW_PRIM Track Pad

RC156 1 2 1K_0201_5% I2C_1_SCL
RC157 1 2 1K_0201_5% I2C_1_SDA 20200824
C
To dGPU Connect to SOC GPIO - Remove GPU_EVENT# , GN20 not used .
C

SOC_GC6_FB_EN RC160 1 @ 2 0_0201_5% GC6_FB_EN3V3 GC6_FB_EN3V3 <26>

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(7/14)GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 12 of 121
5 4 3 2 1
 5 4 3 2 1

UC1H
REV0.6
PCIE4_A_CTX_DRX_P3 A20 C33 PCIE5_CTX_GRX_P7 0.22U_0402_16V7K 2 1 VGA@ CC30
<68> PCIE4_A_CTX_DRX_P3 PCIEX4_A_TX_P_3 PCIEX8_TX_P_7 PCIE5_CTX_C_GRX_P7 <25>
PCIE4_A_CTX_DRX_N3 C20 D33 PCIE5_CTX_GRX_N7 0.22U_0402_16V7K 2 1 VGA@ CC31
<68> PCIE4_A_CTX_DRX_N3 PCIE4_A_CRX_DTX_P3 PCIEX4_A_TX_N_3 PCIEX8_TX_N_7 PCIE5_CTX_GRX_P6 PCIE5_CTX_C_GRX_N7 <25>
M22 J33 0.22U_0402_16V7K 2 1 VGA@ CC32
<68> PCIE4_A_CRX_DTX_P3 PCIEX4_A_RX_P_3 PCIEX8_TX_P_6 PCIE5_CTX_C_GRX_P6 <25>
PCIE4_A_CRX_DTX_N3 M24 G33 PCIE5_CTX_GRX_N6 0.22U_0402_16V7K 2 1 VGA@ CC33
<68> PCIE4_A_CRX_DTX_N3 PCIEX4_A_RX_N_3 PCIEX8_TX_N_6 PCIE5_CTX_C_GRX_N6 <25>
C30 PCIE5_CTX_GRX_P5 0.22U_0402_16V7K 2 1 VGA@ CC34
PCIEX8_TX_P_5 PCIE5_CTX_C_GRX_P5 <25>
PCIE4_A_CTX_DRX_P2 G20 D30 PCIE5_CTX_GRX_N5 0.22U_0402_16V7K 2 1 VGA@ CC35
<68> PCIE4_A_CTX_DRX_P2 PCIE4_A_CTX_DRX_N2 PCIEX4_A_TX_P_2 PCIEX8_TX_N_5 PCIE5_CTX_GRX_P4 PCIE5_CTX_C_GRX_N5 <25>
F20 J30 0.22U_0402_16V7K 2 1 VGA@ CC36
<68> PCIE4_A_CTX_DRX_N2 PCIE4_A_CRX_DTX_P2 PCIEX4_A_TX_N_2 PCIEX8_TX_P_4 PCIE5_CTX_GRX_N4 PCIE5_CTX_C_GRX_P4 <25>
V22 G30 0.22U_0402_16V7K 2 1 VGA@ CC37
<68> PCIE4_A_CRX_DTX_P2 PCIE4_A_CRX_DTX_N2 PCIEX4_A_RX_P_2 PCIEX8_TX_N_4 PCIE5_CTX_GRX_P3 PCIE5_CTX_C_GRX_N4 <25>
D
U22 C26 0.22U_0402_16V7K 2 1 VGA@ CC38 PCIE5_CTX_C_GRX_P3 <25> D
<68> PCIE4_A_CRX_DTX_N2 PCIEX4_A_RX_N_2 PCIEX8_TX_P_3 D26 PCIE5_CTX_GRX_N3 0.22U_0402_16V7K 2 1 VGA@ CC39
PCIE4_A_CTX_DRX_P1 A17 PCIEX8_TX_N_3 PCIE5_CTX_GRX_P2 PCIE5_CTX_C_GRX_N3 <25>
J26 0.22U_0402_16V7K 2 1 VGA@ CC40 PCIE5_CTX_C_GRX_P2 <25>
<68> PCIE4_A_CTX_DRX_P1 PCIE4_A_CTX_DRX_N1 C17 PCIEX4_A_TX_P_1 PCIEX8_TX_P_2 G26 PCIE5_CTX_GRX_N2 0.22U_0402_16V7K 2 1 VGA@ CC41
<68> PCIE4_A_CTX_DRX_N1 PCIE4_A_CRX_DTX_P1 AC22 PCIEX4_A_TX_N_1 PCIEX8_TX_N_2 PCIE5_CTX_GRX_P1 PCIE5_CTX_C_GRX_N2 <25>
C23 0.22U_0402_16V7K 2 1 VGA@ CC42
<68> PCIE4_A_CRX_DTX_P1 PCIE4_A_CRX_DTX_N1 AA22 PCIEX4_A_RX_P_1 PCIEX8_TX_P_1 PCIE5_CTX_GRX_N1 PCIE5_CTX_C_GRX_P1 <25>
D23 0.22U_0402_16V7K 2 1 VGA@ CC43 PCIE5_CTX_C_GRX_N1 <25>
<68> PCIE4_A_CRX_DTX_N1 PCIEX4_A_RX_N_1 PCIEX8_TX_N_1 J23 PCIE5_CTX_GRX_P0 0.22U_0402_16V7K 2 1 VGA@ CC44
PCIE4_A_CTX_DRX_P0 PCIEX8_TX_P_0 PCIE5_CTX_GRX_N0 PCIE5_CTX_C_GRX_P0 <25>
G17 G23 0.22U_0402_16V7K 2 1 VGA@ CC45 PCIE5_CTX_C_GRX_N0 <25>
<68> PCIE4_A_CTX_DRX_P0 PCIE4_A_CTX_DRX_N0 F17 PCIEX4_A_TX_P_0 PCIEX8_TX_N_0
<68> PCIE4_A_CTX_DRX_N0 PCIE4_A_CRX_DTX_P0 PCIEX4_A_TX_N_0 PCIE5_CRX_GTX_P7
dGPU
M18 M39 0.22U_0402_16V7K 2 1 VGA@ CC46
<68> PCIE4_A_CRX_DTX_P0 PCIE4_A_CRX_DTX_N0 PCIEX4_A_RX_P_0 PCIEX8_RX_P_7 PCIE5_CRX_GTX_N7 PCIE5_CRX_C_GTX_P7 <25>
M19 M37 0.22U_0402_16V7K 2 1 VGA@ CC47
<68> PCIE4_A_CRX_DTX_N0 PCIEX4_A_RX_N_0 PCIEX8_RX_N_7 U37 PCIE5_CRX_GTX_P6 2 1 PCIE5_CRX_C_GTX_N7 <25>
0.22U_0402_16V7K VGA@ CC48
PCIE4_RCONP_N F6 PCIEX8_RX_P_6 V37 PCIE5_CRX_GTX_N6 2 1 PCIE5_CRX_C_GTX_P6 <25>
0.22U_0402_16V7K VGA@ CC49
PCIEX4_RCOMP_N PCIEX8_RX_N_6 PCIE5_CRX_GTX_P5 PCIE5_CRX_C_GTX_N6 <25>
A6 AA37 0.22U_0402_16V7K 2 1 VGA@ CC50
PCIE4_A_RCOMP_P PCIEX4_A_RCOMP_P_1 PCIEX8_RX_P_5 PCIE5_CRX_GTX_N5 PCIE5_CRX_C_GTX_P5 <25>
2.2K_0201_1%1 RC165 2 C6 AC37 0.22U_0402_16V7K 2 1 VGA@ CC51 PCIE5_CRX_C_GTX_N5 <25>
A5 PCIEX4_A_RCOMP_P_2 PCIEX8_RX_N_5 U32 PCIE5_CRX_GTX_P4 0.22U_0402_16V7K 2 1 VGA@ CC52
PCIE4_B_RCOMP_P PCIEX4_B_RCOMP_P_1 PCIEX8_RX_P_4 PCIE5_CRX_GTX_N4 PCIE5_CRX_C_GTX_P4 <25>
2.2K_0201_1%1 RC166 2 D6 V32 0.22U_0402_16V7K 2 1 VGA@ CC53 PCIE5_CRX_C_GTX_N4 <25>
PCIEX4_B_RCOMP_P_2 PCIEX8_RX_N_4 AA32 PCIE5_CRX_GTX_P3 0.22U_0402_16V7K 2 1 VGA@ CC54
PCIE4_B_CTX_DRX_P3 PCIEX8_RX_P_3 PCIE5_CRX_GTX_N3 PCIE5_CRX_C_GTX_P3 <25>
A14 AC32 0.22U_0402_16V7K 2 1 VGA@ CC55
<69> PCIE4_B_CTX_DRX_P3 PCIE4_B_CTX_DRX_N3 PCIEX4_B_TXP_3 PCIEX8_RX_N_3 PCIE5_CRX_GTX_P2 PCIE5_CRX_C_GTX_N3 <25>
C14 M29 0.22U_0402_16V7K 2 1 VGA@ CC56
<69> PCIE4_B_CTX_DRX_N3 PCIE4_B_CRX_DTX_P3 PCIEX4_B_TXN_3 PCIEX8_RX_P_2 PCIE5_CRX_GTX_N2 PCIE5_CRX_C_GTX_P2 <25>
V17 M27 0.22U_0402_16V7K 2 1 VGA@ CC57
<69> PCIE4_B_CRX_DTX_P3 PCIE4_B_CRX_DTX_N3 U17 PCIEX4_B_RXP_3 PCIEX8_RX_N_2 U27 PCIE5_CRX_GTX_P1 2 1 PCIE5_CRX_C_GTX_N2 <25>
0.22U_0402_16V7K VGA@ CC58 PCIE5_CRX_C_GTX_P1 <25>
<69> PCIE4_B_CRX_DTX_N3 PCIEX4_B_RXN_3 PCIEX8_RX_P_1 V27 PCIE5_CRX_GTX_N1 0.22U_0402_16V7K 2 1 VGA@ CC59
PCIEX8_RX_N_1 PCIE5_CRX_C_GTX_N1 <25>
PCIE4_B_CTX_DRX_P2 G14 AA27 PCIE5_CRX_GTX_P0 0.22U_0402_16V7K 2 1 VGA@ CC60
<69> PCIE4_B_CTX_DRX_P2 PCIE4_B_CTX_DRX_N2 F14 PCIEX4_B_TXP_2 PCIEX8_RX_P_0 PCIE5_CRX_GTX_N0 PCIE5_CRX_C_GTX_P0 <25>
AC27 0.22U_0402_16V7K 2 1 VGA@ CC61
<69> PCIE4_B_CTX_DRX_N2 PCIE4_B_CRX_DTX_P2 AC17 PCIEX4_B_TXN_2 PCIEX8_RX_N_0 PCIE5_CRX_C_GTX_N0 <25>
<69> PCIE4_B_CRX_DTX_P2 PCIE4_B_CRX_DTX_N2 AA17 PCIEX4_B_RXP_2 A8
<69> PCIE4_B_CRX_DTX_N2 PCIEX4_B_RXN_2 PCIEX8_RCOMP_P_1 C8 PCIE5_RCOMPP 1 RC167 2 150_0201_1%
PCIE4_B_CTX_DRX_P1 A11 PCIEX8_RCOMP_P_2 D8 PCIE5_RCOMPN
<69> PCIE4_B_CTX_DRX_P1 PCIE4_B_CTX_DRX_N1 C11 PCIEX4_B_TXP_1 PCIEX8_RCOMP_N
<69> PCIE4_B_CTX_DRX_N1 PCIE4_B_CRX_DTX_P1 PCIEX4_B_TXN_1
M13
<69> PCIE4_B_CRX_DTX_P1 PCIE4_B_CRX_DTX_N1 M14 PCIEX4_B_RXP_1
<69> PCIE4_B_CRX_DTX_N1 PCIEX4_B_RXN_1
PCIE4_B_CTX_DRX_P0 G11
<69> PCIE4_B_CTX_DRX_P0 PCIE4_B_CTX_DRX_N0 F11 PCIEX4_B_TXP_0
<69> PCIE4_B_CTX_DRX_N0 PCIE4_B_CRX_DTX_P0 PCIEX4_B_TXN_0
V12
C <69> PCIE4_B_CRX_DTX_P0 PCIE4_B_CRX_DTX_N0 U12 PCIEX4_B_RXP_0 C
<69> PCIE4_B_CRX_DTX_N0 PCIEX4_B_RXN_0

ADL-P_BGA1744
@

UC1I
REV0.6
PCIE_CTX_DRX_P12 DY10 EM5 USB20_P10
<51> PCIE_CTX_DRX_P12 PCIE_CTX_DRX_N12 PCIE12_TXP/SATA1_TXP USB2P_10 USB20_N10 USB20_P10 <53>
DY11 EM6 BT
<51> PCIE_CTX_DRX_N12 PCIE_CRX_DTX_P12 EA4 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_N10 <53>
GLAN (Gen2) <51> PCIE_CRX_DTX_P12 PCIE_CRX_DTX_N12 PCIE12_RXP/SATA1_RXP USB20_P9
EA6 EL18
<51> PCIE_CRX_DTX_N12 PCIE12_RXN/SATA1RXN USB2P_9 USB20_N9 USB20_P9 <66>
EN18 FP
USB2N_9 USB20_N9 <66>
EB10
EB11 PCIE11_TXP/SATA0_TXP EN1 USB20_P8
EC5 PCIE11_TXN/SATA0_TXN USB2P_8 EN3 USB20_N8 USB20_P8 <63>
EC6 PCIE11_RXP/SATA0_RXP USB2N_8 USB20_N8 <63> Per Key
PCIE11_RXN/SATA0_RXN ER16 USB20_P7
PCIE_CTX_DRX_P10 USB2P_7 USB20_N7 USB20_P7 <38>
ED10 ET16 camera
<70> PCIE_CTX_DRX_P10 PCIE_CTX_DRX_N10 ED11 PCIE10_TXP/UFS11_TXP USB2N_7 USB20_N7 <38>
<70> PCIE_CTX_DRX_N10 PCIE_CRX_DTX_P10 PCIE10_TXN/UFS11_TXN USB20_P6
Card reader (Gen1) EC1 EP4
<70> PCIE_CRX_DTX_P10 PCIE_CRX_DTX_N10 PCIE10_RXP/UFS11_RXP USB2P_6 USB20_N6 USB20_P6 <60>
EC3 EP6 3D Lens
<70> PCIE_CRX_DTX_N10 PCIE10_RXN/UFS11_RXN USB2N_6 USB20_N6 <60>
EF10 FA15 USB20_P5
EF11 PCIE9_TXP/UFS10_TXP USB2P_5 FC15 USB20_N5 USB20_P5 <60>
EF5 PCIE9_TXN/UFS10_TXN USB2N_5 USB20_N5 <60> eyetracker
EF6 PCIE9_RXP/UFS10_RXP ER5 USB20_P4
PCIE9_RXN/UFS10_RXN USB2P_4 USB20_N4 USB20_P4 <46>
ER6 USB3.1 TBT Port (MB)
USB2N_4 USB20_N4 <46>
EH10
EH11 PCIE8_TXP ER18 USB20_P3
PCIE8_TXN USB2P_3 USB20_N3 USB20_P3 <72>
EF1 ET18 USB3.1 Type-A Port (MB)
PCIE8_RXP USB2N_3 USB20_N3 <72>
EF3
PCIE8_RXN EH16 USB20_P2
B EL10 USB2P_2 EK16 USB20_N2 USB20_P2 <43> B
EL11 PCIE7_TXP USB2N_2 USB20_N2 <43> USB3.1 TBT Port (MB)
EG4 PCIE7_TXN EL16 USB20_P1
PCIE7_RXP USB2P_1 USB20_N1 USB20_P1 <71>
EG6 EN16 USB3.1 Type-A Port (MB)
PCIE7_RXN USB2N_1 USB20_N1 <71>
EN10 FC25 SOC_GPP_E9 1 T248
EN11 PCIE6_TXP GPP_E9/USB_OC0#/ISH_GP4 DY51 @
EJ5 PCIE6_TXN GPP_A16/USB_OC3#/ISH_GP5
EJ6 PCIE6_RXP FA25 DEVSLP1 1 @ T249
PCIE6_RXN GPP_E5/DEVSLP1/SRCCLK_OE6# FC22 SOC_DG_BB_FORCE_PWR RC89 1 2
ER10 GPP_E4/DEVSLP0/SRCCLK_OE9# SOC_DG_BB_FORCE_PWR_R <42,43,44,45,46>
33_0201_5%
ER11 PCIE5_TXP DY1 PCIE_RCOMPP RC168 1 2 100_0201_1%
EJ1 PCIE5_TXN MPHY_RCOMPP DY3 PCIE_RCOMPN
EJ3 PCIE5_RXP MPHY_RCOMPN
PCIE5_RXN EF18 USB2_VBUSSENSE RC169 1 2 10K_0201_1%
PCIE_CTX_DRX_P4 FB10 USB_VBUSSENSE EF16 USB2_ID RC170 1 2 10K_0201_1%
<53> PCIE_CTX_DRX_P4 PCIE_CTX_DRX_N4 FA9 PCIE4_TXP/USB32_4_TXP USB_ID FB20 USB2_COMP RC171 1 2 113_0201_1%
<53> PCIE_CTX_DRX_N4 PCIE_CRX_DTX_P4 PCIE4_TXN/USB32_4_TXN USB2_COMP
WLAN (Gen2) EV16
<53> PCIE_CRX_DTX_P4 PCIE_CRX_DTX_N4 EY16 PCIE4_RXP/USB32_4_RXP DL8 1 T251
<53> PCIE_CRX_DTX_N4 PCIE4_RXN/USB32_4_RXN UFS_RESET# @
EW11
EY11 PCIE3_TXP/USB32_3_TXP
EW17 PCIE3_TXN/USB32_3_TXN
EY17 PCIE3_RXP/USB32_3_RXP
PCIE3_RXN/USB32_3_RXN
USB3_CTX_DRX_P2 FA12
<72> USB3_CTX_DRX_P2 USB3_CTX_DRX_N2 FC12 PCIE2_TXP/USB32_2_TXP
USB3.1 Type-A <72> USB3_CTX_DRX_N2 USB3_CRX_DTX_P2 PCIE2_TXN/USB32_2_TXN
FA18
(MB JUSB2) <72> USB3_CRX_DTX_P2 USB3_CRX_DTX_N2 FC18 PCIE2_RXP/USB32_2_RXP
<72> USB3_CRX_DTX_N2 PCIE2_RXN/USB32_2_RXN
USB3_CTX_DRX_P1 EV12
<71> USB3_CTX_DRX_P1 USB3_CTX_DRX_N1 EY12 PCIE1_TXP/USB32_1_TXP
USB3.1 Type-A <71> USB3_CTX_DRX_N1 USB3_CRX_DTX_P1 PCIE1_TXN/USB32_1_TXN
EV19
(MB JUSB1) <71> USB3_CRX_DTX_P1 USB3_CRX_DTX_N1 EY19 PCIE1_RXP/USB32_1_RXP
<71> USB3_CRX_DTX_N1 PCIE1_RXN/USB32_1_RXN
A A
ADL-P_BGA1744
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(8/14)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 13 of 121
5 4 3 2 1
 5 4 3 2 1

D D

UC1J
REV0.6
AD41 FC46 CNV_CTX_DRX_P1
CSI_D_DP_1/CSI_C_DP_2 CNV_WT_D1P CNV_CTX_DRX_P1 <53>
AB41 FA46 CNV_CTX_DRX_N1
CSI_D_DN_1/CSI_C_DN_2 CNV_WT_D1N CNV_CTX_DRX_N1 <53>
AG41 EV43 CNV_CTX_DRX_P0
CSI_D_DP_0/CSI_C_DP_3 CNV_WT_D0P CNV_CTX_DRX_P0 <53>
AF41 EY43 CNV_CTX_DRX_N0
CSI_D_DN_0/CSI_C_DN_3 CNV_WT_D0N CNV_CTX_DRX_N0 <53>
J41 EV47 CLK_CNV_CTX_DRX_P
CSI_D_CLK_P CNV_WT_CLKP CLK_CNV_CTX_DRX_P <53>
L41 EY47 CLK_CNV_CTX_DRX_N
CSI_D_CLK_N CNV_WT_CLKN CLK_CNV_CTX_DRX_N <53>
P44 EV40 CNV_CRX_DTX_P1
CSI_C_DP_1 CNV_WR_D1P CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 <53>
M44 EY40
CSI_C_DN_1 CNV_WR_D1N CNV_CRX_DTX_P0 CNV_CRX_DTX_N1 <53>
T41 EW42
CSI_C_DP_0 CNV_WR_D0P CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 <53>
P41 EY42
CSI_C_DN_0 CNV_WR_D0N CLK_CNV_CRX_DTX_P CNV_CRX_DTX_N0 <53> +1.8VALW _PRIM
J44 FA43 CLK_CNV_CRX_DTX_P <53>
K44 CSI_C_CLK_P CNV_WR_CLKP FC43 CLK_CNV_CRX_DTX_N
CSI_C_CLK_N CNV_WR_CLKN CLK_CNV_CRX_DTX_N <53>
W41 FC40 CNV_W T_RCOMP RC172 1 2 150_0201_1% CNV_BRI_CRX_DTX 20K_0201_5% 1 @ 2 RC173
AA41 CSI_B_DP_1 CNV_WT_RCOMP
C38 CSI_B_DN_1 EK33 CNV_BRI_CRX_DTX CNV_RGI_CRX_DTX 20K_0201_5% 1 @ 2 RC174
CSI_B_DP_0 GPP_F1/CNV_BRI_RSP/UART2_RXD CNV_BRI_CTX_DRX CNV_BRI_CRX_DTX <53>
A38 EH33 CNV_BRI_CTX_DRX <53>
G39 CSI_B_DN_0 GPP_F0/CNV_BRI_DT/UART2_RTS# ER31 CNV_RGI_CRX_DTX
CSI_B_CLK_P GPP_F3/CNV_RGI_RSP/UART2_CTS# CNV_RGI_CTX_DRX CNV_RGI_CRX_DTX <53>
C F39 EN31 CNV_RGI_CTX_DRX <53>
C
CSI_B_CLK_N GPP_F2/CNV_RGI_DT/UART2_TXD
C36 EF36 CLKREQ_CNV# +1.8VALW _PRIM
CSI_A_DP_1/CSI_B_DP_2 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ CLKREQ_CNV# <53> CNV_BRI_CTX_DRX
A36 EH36
G37 CSI_A_DN_1/CSI_B_DN_2 GPP_F6/CNV_PA_BLANKING ET31 CNV_RF_RESET# XTAL SEL
CSI_A_DP_0/CSI_B_DP_3 GPP_F4/CNV_RF_RESET# CNV_RF_RESET# <53> INTERNAL PD 20K
E37
F36 CSI_A_DN_0/CSI_B_DN_3 LOW = 38.4 MHZ (DEFAULT)
CSI_A_CLK_P HIGH = 24MHZ (25 MHZ WHEN XTAL FREQ DIVIDER NON ZERO)

1
G36
CSI_A_CLK_N RC175
RC176 1 2 CSI_RCOMP A55 100K_0201_5%
150_0201_1% B54 CSI_RCOMP_1
CSI_RCOMP_2

2
ET41 CNV_RGI_CTX_DRX
ER41 GPP_H22/IMGCLKOUT3
EN41 GPP_H21/IMGCLKOUT2 CNV_RGI_CTX_DRX
FA31 GPP_H20/IMGCLKOUT1 M.2 CNVI MODES
GPP_D4/IMGCLKOUT0/BK4/SBK4 LOW = Integrated CNVi enable.
HIGH = Integrated CNVi disable.

1
NO INTERNAL PU/PD
RC177
ADL-P_BGA1744
4.7K_0201_5%
@ @

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(9/14)CSI,CNVi
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 14 of 121
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE EMI CAPS-PLACE

0604 rename
UC1M < 5mm from SOC VCCIN
BA44
REV0.6
CF8
0.1uF *1
VCCCORE_1 VCCCORE_51
D
BB43
BB45 VCCCORE_2 VCCCORE_52
CF9
CG14 +VCC_CORE
100pF *1 D
VCCCORE_3 VCCCORE_53
BC44
BD43 VCCCORE_4 VCCCORE_54
CG4
CH1
15pF *1
BD45
BE44
VCCCORE_5
VCCCORE_6
VCCCORE_55
VCCCORE_56
CH3
CK11
3pF *1

15P_0201_50V8J

3P_0201_50V8C
100P_0201_50V8J
1 1 1 1

0.1U_0201_10V6K
BH43 VCCCORE_7 VCCCORE_57 CK12

EMC@ CC62

EMC@ CC63

EMC@ CC64

EMC@ CC65
BK43 VCCCORE_8 VCCCORE_58 CK4
BK44 VCCCORE_9 VCCCORE_59 CK6
BL45 VCCCORE_10 VCCCORE_60 CK8 2 2 2 2
BM44 VCCCORE_11 VCCCORE_61 CK9
BN11 VCCCORE_12 VCCCORE_62 CL1
BN12 VCCCORE_13 VCCCORE_63 CL14
BN45 VCCCORE_14 VCCCORE_64 CL3
BP14 VCCCORE_15 VCCCORE_65 CM11
BR11 VCCCORE_16 VCCCORE_66 CM12
BR12 VCCCORE_17 VCCCORE_67 CM4
BT14 VCCCORE_18 VCCCORE_68 CM6
VCCCORE_19 VCCCORE_69 626549_ADL_P_BEP_plus_TDK_Rev0p71
BT44 CM8
BU11 VCCCORE_20 VCCCORE_70 CM9
BU12 VCCCORE_21 VCCCORE_71 CN1
BU43 VCCCORE_22 VCCCORE_72 CN14
BU45 VCCCORE_23 VCCCORE_73 CN3
BV14 VCCCORE_24 VCCCORE_74 CP1 +1.05V_PROC
BV44 VCCCORE_25 VCCCORE_75 CP11
BW12 VCCCORE_26 VCCCORE_76 CP12
BW43 VCCCORE_27 VCCCORE_77 CP3
BW45 VCCCORE_28 VCCCORE_78 CP4
VCCCORE_29 VCCCORE_79

1
BY1 CP6
BY44 VCCCORE_30
VCCCORE_31
VCCCORE_80
VCCCORE_81
CP8 SVID DATA RC179
C CA1 CP9 100_0201_1% C
CA3 VCCCORE_32 VCCCORE_82 CR4
CB12 VCCCORE_33 VCCCORE_83

2
CC14 VCCCORE_34 CT3
VCCCORE_35 VCC_SENSE VCC_SENSE_VCCIN <97> SOC_SVID_DAT
CC3 CT1 SOC_SVID_DAT <97>
VCCCORE_36 VSS_SENSE VSS_SENSE_VCCIN <97>
CD11
CD12 VCCCORE_37 R9 SOC_SVID_DAT
CD6 VCCCORE_38 VIDSOUT U9 SOC_SVID_CLK +1.05VO_PROC_OUT
CD8 VCCCORE_39 VIDSCK W9 SOC_SVID_ALERT# +1.05V_PROC
CD9 VCCCORE_40 VIDALERT#
CE1 VCCCORE_41 AU14
VCCCORE_42 VCC1P05_PROC_OUT_3

1
CE14
CE3 VCCCORE_43
VCCCORE_44 VCCST_PWRGD_SX
DJ6 VCCSTPW RGOOD_TGSS
VCCSTPW RGOOD_TGSS <11>
SVID ALERT RC181
CE4 56_0201_1%
CF1 VCCCORE_45
CF11 VCCCORE_46

2
CF12 VCCCORE_47
CF3 VCCCORE_48 SOC_SVID_ALERT#
VCCCORE_49 SOC_SVID_ALERT# <97>
CF6
VCCCORE_50

+1.05V_PROC
ADL-P_BGA1744
@

SVID CLOCK

1
RC183
100_0201_1%
@
B B

2
SOC_SVID_CLK
SOC_SVID_CLK <97>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(10/14)Power, SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 15 of 121
5 4 3 2 1
 5 4 3 2 1

+1.065V_MEM UC1O +VCC_GT

REV0.6 0604 rename
AD61 CP44
AG61 VDD2_1 VCCGT_1 CR45
AN61 VDD2_2 VCCGT_2 CT44
AP41 VDD2_3 VCCGT_3 CU43
EMC CAPS-PLACE 1.A add AP44 VDD2_4 VCCGT_4 CU45
AR43 VDD2_5 VCCGT_5 CV4
< 4mm from SOC VDDQ AR45 VDD2_6 VCCGT_6 CV44
+1.065V_MEM +1.065V_MEM +1.065V_MEM VDD2_7 VCCGT_7
with each pair < 12mm Apart AT44
AU43 VDD2_8 VCCGT_8
CW1
CW11
VDD2_9 VCCGT_9
15pF* 3 (EMI@) AU45
AV44 VDD2_10 VCCGT_10
CW12
CW3
3pF* 3 (EMI@) AY61
BH61
VDD2_11
VDD2_12
VCCGT_11
VCCGT_12
CW6
CW8

1U_0201_10V6M

1U_0201_10V6M
3P_0201_50V8C

3P_0201_50V8C
15P_0201_50V8J

15P_0201_50V8J
1 1 1 1 VDD2_13 VCCGT_13

1
BR61 CW9

EMC@ CC66

EMC@ CC67

EMC@ CC68

EMC@ CC69

CC70

CC71
CA61 VDD2_14 VCCGT_14 CY14
D CC44 VDD2_15 VCCGT_15 CY4 D

2
2 2 2 2 CD43 VDD2_16 VCCGT_16 CY44
CD61 VDD2_17 VCCGT_17 DA1
CE44 VDD2_18 VCCGT_18 DA3
CF43 VDD2_19 VCCGT_19 DA43
CF45 VDD2_20 VCCGT_20 DB45
CG44 VDD2_21 VCCGT_21 DC1
CH45 VDD2_22 VCCGT_22 DC11
627333_ADL_P_DDR4_RVP_TDK_Rev0p7 VDD2_23 VCCGT_23
CK61 DC12
CN61 VDD2_24 VCCGT_24 DC3
CW61 VDD2_25 VCCGT_25 DC4
DF61 VDD2_26 VCCGT_26 DC44
J61 VDD2_27 VCCGT_27 DC6
R61 VDD2_28 VCCGT_28 DC8
+1.05VO_PROC_OUT V61 VDD2_29 VCCGT_29 DC9
VDD2_30 VCCGT_30 DD1
AR14 VCCGT_31 DD14
AT12 VCC1P05_PROC_OUT_1
VCCGT_32 DD3
VCC1P05_PROC_OUT_2
VCCGT_33 DD43
T253 TP@ 1 CM44 VCCGT_34 DD45
+1.8V_PROC T254 TP@ 1 EA14 RSVD_TP_33 VCCGT_35 DE11
RSVD_TP_49 VCCGT_36 DE12
E61 VCCGT_37 DE4
G61 VCC1P8_PROC_8 VCCGT_38 DE6
H59 VCC1P8_PROC_9 VCCGT_39 DE8
AH44 VCC1P8_PROC_10 VCCGT_40 DE9
AJ45 VCC1P8_PROC_1 VCCGT_41 DF1
AK44 VCC1P8_PROC_2 VCCGT_42 DF14
AL45 VCC1P8_PROC_3 VCCGT_43 DF3
AM41 VCC1P8_PROC_4 VCCGT_44 DG4
AM44 VCC1P8_PROC_5 VCCGT_45
AN43 VCC1P8_PROC_6
VCC1P8_PROC_7
CV1
<97> VCC_SENSE_VCCIN_GT VCCGT_SENSE
CV3
<97> VSS_SENSE_VCCIN_GT VSSGT_SENSE

ADL-P_BGA1744
@

C C

627205_ADL_P_PDG_Rev1.2
+1.05VO_OUT_FET +1.05VO_OUT_FET +1.05V_PROC
+1.05VO_OUT_FET_JP1
JPC1
1
1 2
2 +1.05V_PROC RC185 1 @ 2 0_0402_5%
1U_0201_6.3V6M

Imax : 0.500 A JUMP_43X79 1

CC72

@
For Power consumption UC6
Measurement 1 +1.05V_PROC_R
2 2 VIN1 +1.05V_PROC
+5VALW VIN2 Imax : 0.500 A
CC73 7 6 +1.05V_PROC_R RC186 1 @ 2 0_0603_5%
0.1U_0201_16V6K VIN thermal VOUT
2 @ 1 3 CC74 1
VBIAS 0.1U_0201_10V6K
+1.05V_PROC_EN_LS 1 @ 2+1.05V_PROC_EN_LS_R 4 5
20210824 RC186 change from 0402 to 0603
RC187 ON GND
2
1U_0201_6.3V6M

0_0201_5% 1
CC75

B EM5201V_DFN8_3X3 B

@
2
I (Max) : 0.500 A(+1.05V_PROC)
RDS(Typ) : 3.5 mohm
V drop : 0.00175V

+1.05V_PROC Enable 1uF* 6

<58,84,91> SYSON
SYSON RC188 1 @ 2 0_0201_5% 10uF * 3
PM_SLP_S4# RC189 1 @ 2 0_0201_5%
uF * 2
<11,91> PM_SLP_S4#
SUSP# RC190 1 @ 2 0_0201_5%
Layout Follow 627205_ADL_P_PDG_Rev0p7
<11,38,39,40,58,69,72,78,85,91> SUSP#
PM_SLP_S3# RC191 1 2 0_0201_5%
<11> PM_SLP_S3#
+1.065V_MEM +1.065V_MEM

+3VALW

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
+1.8V_PROC

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
CC76

CC77

CC78

CC79

CC80

CC81
1 1 1 1 1 1 1 1 1 1 1

CC82

CC83

CC84

CC85

CC86
DC7
1 2
CC87 1 +1.05V_PROC_EN_LS @ @
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
3 2 2 2 2 2 2 2 2 2 2 2
1U_0201_10V6M

0.1U_0201_10V6K 1 1 1 1

1
@
CC88

CC89

CC90

CC91

CC92

CC93
5

UC7 2 LRB715FT1G_SOT323-3 @ @ @ @
VCCST_OVERRIDE_LS 2
G Vcc

<11> VCCST_OVERRIDE_LS
2

2
A 4 VCCST_STG_COM_EN 2 2 2 2
VCCIN_AUX_CORE_VID 1 Y
<11> VCCIN_AUX_CORE_VID B TOP side BOT side
A 74AUP1G32GW _TSSOP5 TOP side A
3

1 @ 2
RC192 0_0201_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(11/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 16 of 121
5 4 3 2 1
 5 4 3 2 1

+1.8V_PRIM_MCP +1.8V_VCCA_CLKLDO
+3VALW TO +3V_PRIM @
L7 1 2
1354mA +1.8VALW_PRIM +1.8V_PRIM_MCP 4.7UH_UHP252012BF-4R7M_20%
+3VALW +3VALW_PRIM

2
JPC2 I Max = 0.17A EMC@
1 2 RC256 1 RS@ 2 0_0805_5% RC195
1 2 RC196 1 2 0_0402_5%
JUMP_43X39 0_0402_5%
@ 1

1
CC95 +3VALW +3VALW_DSW
4.7U_0402_6.3V6M 1
D 2 D
RC197 1 @ 2 0_0402_5% I Max = 0.202A CC94
47U_0603_6.3V6M
2

+VCCIN_AUX UC1N +1.8V_PRIM_MCP

REV0.6
EMI CAPS-PLACE AL20
VCCIN_AUX_1 VCCPRIM_1P8_1
DW20
AL32 DW22
< 5mm from SOC VCCIN_AUX AN20 VCCIN_AUX_2 VCCPRIM_1P8_2 DW27
AN22 VCCIN_AUX_3 VCCPRIM_1P8_3 DW30
+VCCIN_AUX AN30 VCCIN_AUX_4 VCCPRIM_1P8_4 DY21
AN32 VCCIN_AUX_5 VCCPRIM_1P8_5 DY23
AN37 VCCIN_AUX_6 VCCPRIM_1P8_6 DY26
VCCIN_AUX_7 VCCPRIM_1P8_7 Note: VCCPGPPR follow HDA interface
AP17 DY28
AP27 VCCIN_AUX_8 VCCPRIM_1P8_8 DY31
CC96

CC97

CC98

CC99

EMC@ CC100

EMC@ CC101

1 1 1 1 1 1
10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J

AP30 VCCIN_AUX_9 VCCPRIM_1P8_9 EB18

AP32 VCCIN_AUX_10 VCCPRIM_1P8_12 EB21
AP37 VCCIN_AUX_11 VCCPRIM_1P8_13 EB23
2 2 2 2 2 2 VCCIN_AUX_12 VCCPRIM_1P8_14
EMC@

EMC@

EMC@

EMC@

B3 EB28
D3 VCCIN_AUX_13 VCCPRIM_1P8_15 EC14
E1 VCCIN_AUX_14 VCCPRIM_1P8_16 EC16
F1 VCCIN_AUX_33 VCCPRIM_1P8_17 EC23
F3 VCCIN_AUX_36 VCCPRIM_1P8_18 EC26
G3 VCCIN_AUX_37 VCCPRIM_1P8_19 EE14
H4 VCCIN_AUX_38 VCCPRIM_1P8_20 EE28
J1 VCCIN_AUX_39 VCCPRIM_1P8_21 EG14
C J3 VCCIN_AUX_40 VCCPRIM_1P8_22 FB33 +3VALW_PRIM C
L1 VCCIN_AUX_41 VCCPRIM_1P8_23
L3 VCCIN_AUX_42 DV41
N3 VCCIN_AUX_43 VCCPRIM_3P3_1 DW40
VCCIN_AUX_44 VCCPRIM_3P3_2 EB33
DH45 VCCPRIM_3P3_3 EC31
DJ41 VCCIN_AUX_15 VCCPRIM_3P3_5 EC33
DJ44 VCCIN_AUX_16 VCCPRIM_3P3_6 EE31
DK40 VCCIN_AUX_17 VCCPRIM_3P3_7 +0.85VO_VCCLDOSTD
DK43 VCCIN_AUX_18 FB45
DK45 VCCIN_AUX_19 RSVD_24
+VCCIN_AUX_FIL DL44 VCCIN_AUX_20 FB52 +1.8V_VCCA_CLKLDO
DM1 VCCIN_AUX_21 VCCLDOSTD_0P85
+1.05VO_VNNBYPASS DM14 VCCIN_AUX_22 EJ14 +1.24VO_VCCDPHY
DM43 VCCIN_AUX_23 VCCA_CLKLDO_1P8_1 EM14
DP41 VCCIN_AUX_24 VCCA_CLKLDO_1P8_2
DP42 VCCIN_AUX_25 FB39
1 VCCIN_AUX_26 VCCDPHY_1P24
1

DR14
CC171

CC479
47U_0603_6.3V6M

10U_0402_6.3V6M

+1.05VO_EXTBYPASS DR40 VCCIN_AUX_27 BN43 1 TP@T255

VCCIN_AUX_28 RSVD_TP_28
1

DT41 AY11 1 TP@T256

100K_0201_5%

2 DU14 VCCIN_AUX_29 RSVD_TP_18 BP44 1 TP@T257

RC73

DU40 VCCIN_AUX_30 RSVD_TP_29 BL12 1 TP@T258

DV2 VCCIN_AUX_31 RSVD_TP_27 CN43 1 TP@T259
@ ED2 VCCIN_AUX_32 RSVD_TP_34 BJ11 1 TP@T260 +1.05VO_OUT_PCH
100K_0201_5%

VCCIN_AUX_34 RSVD_TP_24
1

EL2
VCCIN_AUX_35
TOP side 5/17 Follow TD team P1 EB36 +1.05VO_VCCDSW
RC71

VCCIN_AUX_FLTR VCCPRIM1P05_OUT_PCH_1 EC36

@ AH30 VCCPRIM1P05_OUT_PCH_3 EE41 +1.05VO_OUT_PCH
<95> VSS_SENSE_VCCIN_AUX VSSINAUX_SENSE VCCDSW_1P05 +1.24V_MIPI
AF30 V1 1 TP@T261
<95> VCC_SENSE_VCCIN_AUX
2

VCCINAUX_SENSE VCC_MIPILP EB38

EF21 VCCPRIM1P05_OUT_PCH_2 EE36 +RTCVCC
EH21 VCC_VNNEXT_1P05_1 VCCPRIM1P05_OUT_PCH_4 +3VALW_DSW
VCC_VNNEXT_1P05_2 EC38 +3VALW_PRIM
EE18 VCCRTC EB42
EE21 VCC_V1P05EXT_1P05_1 VCCPDSW_3P3 EE33
B VCC_V1P05EXT_1P05_2 VCCPGPPR +1.8V_PRIM_MCP B

<7,43,46> VCCIN_AUX_CORE_ALERT#_R RC200 1 @ 2 0_0201_5% VCCIN_AUX_CORE_ALERT# DT59 EB41

1 VNN_CTRL EK31 GPP_B2/VRALERT# VCCPRIM_3P3_4 DY41
T262 @ 1 V1.05P_CTRL EL28 GPP_F22/VNN_CTRL VCCPRIM_1P8_10 DY42 +1.05V_PROC
T263 @ GPP_F23/V1P05_CTRL VCCPRIM_1P8_11
VCCIN_AUX_CORE_VID0 EA60 EU1
<11,95> VCCIN_AUX_CORE_VID0 GPP_B0/CORE_VID0 VCC1P05_PROC_1
VCCIN_AUX_CORE_VID1 EA58 EU4 +1.05VO_OUT_FET
<11,95> VCCIN_AUX_CORE_VID1 GPP_B1/CORE_VID1 VCC1P05_PROC_2
EV3
VCC1P05_OUT_FET_1 EW1
VCC1P05_OUT_FET_2 EY1 +1.05VO_PROC_OUT
VCC1P05_OUT_FET_3
AM15
VCC_DISPIO
BJ12 1 TP@T264
RSVD_TP_25 BK14 1 TP@T265
RSVD_TP_26 BF14 1 TP@T266
RSVD_TP_21

ADL-P_BGA1744
@
RTC Battery +RTCBATT

MAX. 8000mil JRTC1

1
+RTCBATT 2 1
W=20mil 2
+1.8V_PRIM_MCP +3VALW_PRIM
+3VALW_DSW +1.05VO_VCCDSW +0.85VO_VCCLDOSTD +1.24VO_VCCDPHY +1.05V_PROC 1 2 3
+RTCVCC 4 GND
RC203 1K_0402_5% DC8 W=40mil
+CHGRTC 2 GND
2mA
0.1U_0201_10V6K

1
CC107

ACES_50271-0020N-001
1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1 1 1 1 1 1
4.7U_0402_6.3V6M

CC103 CC104 1 1 1 3
CONN@

1U_0201_6.3V6M
@ CC102 1U_0201_10V6M 2.2U_0201_6.3V6M @ @
CC105

CC106

CC108

CC109

CC110

0.1U_0201_10V6K
1U_0201_10V6M
A
2 2 2 2 2 2 W=20mil
LRB715FT1G_SOT323-3 2 1 SP02000RO00 A
2 2 2

CC111

CC112
1 2

PLACE CAP CLOSEST POSSIBLE TO THE BGA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(12/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 17 of 121
5 4 3 2 1
 5 4 3 2 1

UC1R UC1S
UC1P UC1Q REV0.6 REV0.6
REV0.6 REV0.6 DC47 ED58 F56 M36
A3 AL15 BF58 CD58 DC54 VSS_295 VSS_369 ED6 F59 VSS_443 VSS_517 M47
D D
A10 VSS_7 VSS_74 AL17 BG1 VSS_149 VSS_222 CE51 DC57 VSS_296 VSS_370 ED60 F9 VSS_444 VSS_518 M57
A21 VSS_1 VSS_75 AL22 BG12 VSS_150 VSS_223 CE55 DC59 VSS_297 VSS_371 ED8 FA40 VSS_445 VSS_519 M59
A23 VSS_2 VSS_76 AL4 BG44 VSS_151 VSS_224 CF47 DE44 VSS_298 VSS_372 EE16 FA7 VSS_446 VSS_520 N1
A25 VSS_3 VSS_77 AL41 BG52 VSS_152 VSS_225 CF49 DE51 VSS_299 VSS_373 EE43 FB1 VSS_447 VSS_521 N4
A26 VSS_4 VSS_78 AL54 BG9 VSS_153 VSS_226 CF54 DE55 VSS_300 VSS_374 EE51 FB14 VSS_448 VSS_522 N40
A28 VSS_5 VSS_79 AM11 BH4 VSS_154 VSS_227 CG57 DF43 VSS_301 VSS_375 EF13 FB26 VSS_449 VSS_523 N41
A30 VSS_6 VSS_80 AM3 BH46 VSS_155 VSS_228 CG59 DF46 VSS_302 VSS_376 EF8 FB42 VSS_450 VSS_524 N48
A31 VSS_8 VSS_81 AM51 BH48 VSS_156 VSS_229 CH11 DF48 VSS_303 VSS_377 EH13 FB48 VSS_451 VSS_525 N54
A33 VSS_9 VSS_82 AM55 BH58 VSS_157 VSS_230 CH12 DF58 VSS_304 VSS_378 EH8 FB59 VSS_452 VSS_526 N9
A40 VSS_10 VSS_83 AM9 BJ51 VSS_158 VSS_231 CH54 DG11 VSS_305 VSS_379 EK21 FB61 VSS_453 VSS_527 P11
A47 VSS_11 VSS_84 AN17 BJ55 VSS_159 VSS_232 CH6 DG12 VSS_306 VSS_380 EK28 FC2 VSS_454 VSS_528 P16
A53 VSS_12 VSS_85 AN40 BJ6 VSS_160 VSS_233 CH8 DG51 VSS_307 VSS_381 EK36 FC55 VSS_455 VSS_529 P21
A60 VSS_13 VSS_86 AN46 BJ8 VSS_161 VSS_234 CH9 DG55 VSS_308 VSS_382 EK43 FC56 VSS_456 VSS_530 P26
AA11 VSS_14 VSS_87 AN48 BJ9 VSS_162 VSS_235 CJ14 DG6 VSS_309 VSS_383 EK51 FC58 VSS_457 VSS_531 P3
AA21 VSS_15 VSS_88 AN58 BL11 VSS_163 VSS_236 CJ4 DG8 VSS_310 VSS_384 EK56 FC60 VSS_458 VSS_532 P31
AA26 VSS_16 VSS_89 AP1 BL4 VSS_164 VSS_237 CJ44 DG9 VSS_311 VSS_385 EK58 G21 VSS_459 VSS_533 P35
AA31 VSS_17 VSS_90 AP15 BL54 VSS_165 VSS_238 CK1 DH4 VSS_312 VSS_386 EL13 G25 VSS_460 VSS_534 P47
AA35 VSS_18 VSS_91 AP20 BL9 VSS_166 VSS_239 CK3 DH54 VSS_313 VSS_387 EL4 G28 VSS_461 VSS_535 P51
AA40 VSS_19 VSS_92 AP22 BM1 VSS_167 VSS_240 CK43 DJ47 VSS_314 VSS_388 EL6 G31 VSS_462 VSS_536 P55
AA44 VSS_20 VSS_93 AP25 BM14 VSS_168 VSS_241 CK46 DJ57 VSS_315 VSS_389 EL8 G34 VSS_463 VSS_537 R12
AA57 VSS_21 VSS_94 AP35 BM47 VSS_169 VSS_242 CK48 DJ59 VSS_316 VSS_390 EN13 G42 VSS_464 VSS_538 R17
AA59 VSS_22 VSS_95 AP51 BM57 VSS_170 VSS_243 CK51 DK14 VSS_317 VSS_391 EN8 G43 VSS_465 VSS_539 R22
AB16 VSS_23 VSS_96 AP55 BM59 VSS_171 VSS_244 CK55 DK54 VSS_318 VSS_392 EP14 G50 VSS_466 VSS_540 R27
AB21 VSS_24 VSS_97 AP9 BN1 VSS_172 VSS_245 CK58 DL10 VSS_319 VSS_393 ER1 H1 VSS_467 VSS_541 R32
AB26 VSS_25 VSS_98 AR4 BN54 VSS_173 VSS_246 CM52 DL11 VSS_320 VSS_394 ER13 H13 VSS_468 VSS_542 R37
AB31 VSS_26 VSS_99 AR54 BN9 VSS_174 VSS_247 CN46 DL13 VSS_321 VSS_395 ER21 H16 VSS_469 VSS_543 R44
AB35 VSS_27 VSS_100 AT47 BP4 VSS_175 VSS_248 CN58 DM4 VSS_322 VSS_396 ER28 H18 VSS_470 VSS_544 R48
AB54 VSS_28 VSS_101 AT57 BP51 VSS_176 VSS_249 CP51 DM41 VSS_323 VSS_397 ER3 H34 VSS_471 VSS_545 R58
C AC4 VSS_29 VSS_102 AT59 BP55 VSS_177 VSS_250 CP55 DM46 VSS_324 VSS_398 ER36 H37 VSS_472 VSS_546 T1 C
AC40 VSS_30 VSS_103 AT6 BR43 VSS_178 VSS_251 CR43 DM48 VSS_325 VSS_399 ER43 H52 VSS_473 VSS_547 T11
AC44 VSS_31 VSS_104 AT8 BR46 VSS_179 VSS_252 CR47 DM51 VSS_326 VSS_400 ER51 H58 VSS_474 VSS_548 T16
AC51 VSS_32 VSS_105 AU54 BR48 VSS_180 VSS_253 CR49 DM55 VSS_327 VSS_401 ER61 H6 VSS_475 VSS_549 T21
AC55 VSS_33 VSS_106 AV11 BR58 VSS_181 VSS_254 CR54 DM58 VSS_328 VSS_402 ER8 H8 VSS_476 VSS_550 T26
AC6 VSS_34 VSS_107 AV4 BR6 VSS_182 VSS_255 CT11 DM6 VSS_329 VSS_403 EU11 H9 VSS_477 VSS_551 T3
AC8 VSS_35 VSS_108 AV9 BR8 VSS_183 VSS_256 CT57 DM61 VSS_330 VSS_404 EU56 J11 VSS_478 VSS_552 T31
AD21 VSS_36 VSS_109 AW1 BR9 VSS_184 VSS_257 CT59 DN13 VSS_331 VSS_405 EU58 J14 VSS_479 VSS_553 T35
AD26 VSS_37 VSS_110 AW14 BT4 VSS_185 VSS_258 CT6 DN40 VSS_332 VSS_406 EU8 J17 VSS_480 VSS_554 T40
AD31 VSS_38 VSS_111 AW51 BT51 VSS_186 VSS_259 CT8 DN8 VSS_333 VSS_407 EV14 J20 VSS_481 VSS_555 T52
AD35 VSS_39 VSS_112 AW55 BT55 VSS_187 VSS_260 CT9 DP46 VSS_334 VSS_408 EV20 J21 VSS_482 VSS_556 U16
AD46 VSS_40 VSS_113 AY1 BU54 VSS_188 VSS_261 CU4 DP49 VSS_335 VSS_409 EV26 J25 VSS_483 VSS_557 U21
AD48 VSS_41 VSS_114 AY43 BU9 VSS_189 VSS_262 CU54 DT13 VSS_336 VSS_410 EV33 J28 VSS_484 VSS_558 U26
AD58 VSS_42 VSS_115 AY46 BV1 VSS_190 VSS_263 CV14 DT52 VSS_337 VSS_411 EV39 J31 VSS_485 VSS_559 U31
AE12 VSS_43 VSS_116 AY48 BV47 VSS_191 VSS_264 CW43 DT8 VSS_338 VSS_412 EV4 J36 VSS_486 VSS_560 U35
AE17 VSS_44 VSS_117 AY51 BV57 VSS_192 VSS_265 CW46 DV13 VSS_339 VSS_413 EV45 J39 VSS_487 VSS_561 U44
AE22 VSS_45 VSS_118 AY55 BV59 VSS_193 VSS_266 CW48 DV4 VSS_340 VSS_414 EV52 J47 VSS_488 VSS_562 U46
AE27 VSS_46 VSS_119 AY58 BW4 VSS_194 VSS_267 CW51 DV44 VSS_341 VSS_415 EV59 J48 VSS_489 VSS_563 V3
AE32 VSS_47 VSS_120 AY9 BW54 VSS_195 VSS_268 CW55 DV49 VSS_342 VSS_416 EW61 J51 VSS_490 VSS_564 V40
AE37 VSS_48 VSS_121 B34 BW9 VSS_196 VSS_269 CW58 DV56 VSS_344 VSS_417 EY14 J55 VSS_491 VSS_565 V41
AE40 VSS_49 VSS_122 B4 BY3 VSS_197 VSS_270 CY51 DV58 VSS_345 VSS_418 EY20 K4 VSS_492 VSS_566 V51
AE44 VSS_50 VSS_123 B43 C1 VSS_198 VSS_271 CY55 DV6 VSS_346 VSS_419 EY26 L12 VSS_493 VSS_567 V55
AE52 VSS_51 VSS_124 B50 C21 VSS_199 VSS_272 D11 DV8 VSS_347 VSS_420 EY3 L13 VSS_494 VSS_568 V58
AE9 VSS_52 VSS_125 B58 C25 VSS_200 VSS_273 D14 DW14 VSS_348 VSS_421 EY33 L15 VSS_495 VSS_569 W1
AF4 VSS_53 VSS_126 B61 C28 VSS_201 VSS_274 D17 DW25 VSS_349 VSS_422 EY39 L17 VSS_496 VSS_570 W11
AF46 VSS_54 VSS_127 BA4 C31 VSS_202 VSS_275 D20 DW35 VSS_350 VSS_423 EY4 L18 VSS_497 VSS_571 W16
AG1 VSS_55 VSS_128 BB12 C34 VSS_203 VSS_276 D21 DY13 VSS_351 VSS_424 EY45 L20 VSS_498 VSS_572 W21
AG51 VSS_56 VSS_130 BB54 C40 VSS_204 VSS_277 D25 DY33 VSS_352 VSS_425 EY52 L22 VSS_499 VSS_573 W26
AG55 VSS_57 VSS_131 BB6 C47 VSS_205 VSS_278 D28 DY36 VSS_353 VSS_426 EY56 L23 VSS_500 VSS_574 W31
B AG58 VSS_58 VSS_132 BB8 C9 VSS_206 VSS_279 D31 DY38 VSS_354 VSS_427 EY58 L27 VSS_501 VSS_575 W35 B
AH9 VSS_59 VSS_133 BB9 CA14 VSS_207 VSS_280 D4 DY52 VSS_355 VSS_428 EY59 L30 VSS_502 VSS_576 W44
AJ3 VSS_60 VSS_134 BC14 CA43 VSS_208 VSS_281 D53 DY8 VSS_356 VSS_429 EY6 L33 VSS_503 VSS_577 Y12
AJ41 VSS_61 VSS_135 BC47 CA46 VSS_209 VSS_282 D56 E43 VSS_357 VSS_430 EY9 L35 VSS_504 VSS_578 Y17
AJ47 VSS_62 VSS_136 BC57 CA48 VSS_210 VSS_283 D58 E50 VSS_358 VSS_431 F21 L36 VSS_505 VSS_579 Y22
AJ49 VSS_63 VSS_137 BC59 CA51 VSS_211 VSS_284 D59 EB13 VSS_359 VSS_432 F23 L38 VSS_506 VSS_580 Y27
AJ54 VSS_64 VSS_138 BD4 CA55 VSS_212 VSS_285 D9 EB26 VSS_360 VSS_433 F26 L40 VSS_507 VSS_581 Y32
AK20 VSS_65 VSS_139 BD54 CA58 VSS_213 VSS_286 DA11 EB31 VSS_361 VSS_434 F28 L54 VSS_508 VSS_582 Y37
AK25 VSS_66 VSS_140 BE1 CB4 VSS_214 VSS_287 DA12 EB8 VSS_362 VSS_435 F30 L9 VSS_509 VSS_583 Y4
AK30 VSS_67 VSS_141 BE12 CB6 VSS_215 VSS_288 DA6 EC21 VSS_363 VSS_436 F33 M16 VSS_510 VSS_584 Y45
AK37 VSS_68 VSS_143 BE51 CB8 VSS_216 VSS_289 DA8 EC28 VSS_364 VSS_437 F4 M21 VSS_511 VSS_585 Y47
AK4 VSS_69 VSS_144 BE55 CB9 VSS_217 VSS_290 DA9 ED13 VSS_365 VSS_438 F40 M26 VSS_512 VSS_586 Y49
AK57 VSS_70 VSS_145 BE9 CC1 VSS_218 VSS_291 DB14 ED4 VSS_366 VSS_439 F46 M31 VSS_513 VSS_587 Y54
AK59 VSS_71 VSS_146 BF46 CC52 VSS_219 VSS_292 DB4 ED56 VSS_367 VSS_440 F47 M32 VSS_514 VSS_588
AK9 VSS_72 VSS_147 BF48 CD46 VSS_220 VSS_293 DB54 VSS_368 VSS_441 F52 1 M34 VSS_515
VSS_73 VSS_148 VSS_221 VSS_294 VSS_442 T267 TP@ VSS_516

ADL-P_BGA1744 ADL-P_BGA1744 ADL-P_BGA1744 ADL-P_BGA1744

@ @ @ @
follow RVP

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(13/14)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 18 of 121
5 4 3 2 1
 5 4 3 2 1

+VCC_CFG_PU_OUT UC1U
REV0.6
RC210 1 @ 2 1K_0201_5% CFG0 CFG15 AF37 A58 1
CFG_15 RSVD_TP_1 TP@ T270
RC204 1 @ 2 1K_0201_5% CFG1 CFG14 AH35 B59 1
CFG_14 RSVD_TP_19 TP@ T268
RC205 1 2 1K_0201_5% CFG2 CFG13 AF35 D61 1 TP@ T269
RC206 1 @ 2 1K_0201_5% CFG3 CFG12 AH37 CFG_13 RSVD_TP_37
CFG11 AH25 CFG_12 AF40 1
CFG_11 RSVD_TP_4 TP@ T271
CFG10 AF20 AH40 1
CFG_10 RSVD_TP_5 TP@ T272
CFG9 AH22
CFG8 AK17 CFG_9 DG44 1
CFG_8 RSVD_TP_38 TP@ T273
RC207 1 @ 2 1K_0201_5% CFG4 CFG7 AJ15 DH43 1 TP@ T274
RC208 1 @ 2 1K_0201_5% CFG5 CFG6 AH17 CFG_7 RSVD_TP_40
RC209 1 @ 2 1K_0201_5% CFG6 1.0 CFG5 and CFG6 unstuff follow intel command nad PDG CFG5 AG15 CFG_6 BB11
RC211 1 @ 2 1K_0201_5% CFG7 CFG4 AD11 CFG_5 VSS_129 BE11
CFG3 AC12 CFG_4 VSS_142
D CFG_3 D
CFG2 AA12 FB3
CFG1 AD16 CFG_2 RSVD_23 FC6
CFG0 AA16 CFG_1 RSVD_25
CFG_0 DY5 1
CFG_RCOMP RSVD_TP_47 TP@ T275
RC212 1 @ 2 1K_0201_5% CFG8 F8 DY6 1 TP@ T276
RC213 1 2 1K_0201_5% CFG9 CFG_RCOMP RSVD_TP_48
RC214 1 2 1K_0201_5% CFG10 T277 TP@ 1 AF22 FC9
CFG_17 RSVD_27

1
RC215 1 @ 2 1K_0201_5% CFG11 1 AF17 FC7
T323 TP@ CFG_16 RSVD_26

RC216
BPM#3 AF12 FB4 1 TP@ T278
BPM#2 AH12 BPM#_3 RSVD_TP_54 FC4 1

49.9_0201_1%
BPM#_2 RSVD_TP_56 TP@ T279
BPM#1 AK12

2
BPM#0 AL12 BPM#_1 DT61 ADR_COMPLETE
RC217 1 @ 2 10K_0201_5% CFG12 BPM#_0 GPP_B18/ADR_COMPLETE
RC218 1 @ 2 10K_0201_5% CFG13 AK27 R4
RC219 1 2 1K_0201_5% CFG14 AH27 RSVD_5 RSVD_28 AC9 1
RSVD_3 RSVD_TP_3 TP@ T280 ADR_COMPLETE
RC220 1 2 1K_0201_5% CFG15
AY12 DL1
1 AT9 VSS RSVD_11 DL3
T281 TP@ RSVD_TP_16 RSVD_12
T282 TP@
1 AT11
1 AP11 RSVD_TP_15 EU61

20K_0201_5%
T283 TP@ RSVD_TP_13 RSVD_22

1
T284 TP@
1 AP12 EC18
1 BA14 RSVD_TP_14 RSVD_14

RC221
T285 TP@ RSVD_TP_20 DV46 @
+VCC_CFG_PU_OUT 1 CT12 VSS_343 DV42 1
T286 TP@ RSVD_TP_36 TP_4 TP@ T287
T288 TP@
1 CR14 DT47 1 TP@ T289

2
1 EK18 RSVD_TP_35 TP_1 CB11 1
T290 TP@ RSVD_TP_52 RSVD_TP_31 TP@ T291
1 EH18 BW11 1
T292 TP@ RSVD_TP_51 RSVD_TP_30 TP@ T293
RC222 1 2 10K_0201_5% BPM#0
RC223 1 2 10K_0201_5% BPM#1 T294 TP@
1 AL25 AK35 1 TP@ T295
RC224 1 2 10K_0201_5% BPM#2 1 AN25 RSVD_TP_6 SKTOCC#
T296 TP@ RSVD_TP_10
RC225 1 2 10K_0201_5% BPM#3 AN27 1 TP@ T297
RSVD_TP_11 AL27 1
RSVD_TP_7 TP@ T298
AL35 1 TP@ T299
C RSVD_TP_8 AN35 1 C
RSVD_TP_12 TP@ T300
EL51 1
GPP_T3 TP@ T301
EN51 1
GPP_T2 TP@ T302

RC226 1 @ 2 1K_0201_5% CFG15

1 2 ADL-P_BGA1744
RC227 @ 1K_0201_5% CFG14
RC228 1 @ 2 1K_0201_5% CFG13 Signal: CFG12, 13 PD 1K follow RVP @
RC229 1 @ 2 1K_0201_5% CFG12 633909_ADL_P_DDR4_SODIMM_1DPC_RVP_TDK_Rev0p7
RC230 1 @ 2 1K_0201_5% CFG11
RC231 1 @ 2 1K_0201_5% CFG10
RC232 1 @ 2 1K_0201_5% CFG8

RC233 1 @ 2 1K_0201_5% CFG7 UC1T

RC234 1 @ 2 1K_0201_5% CFG6 REV0.6
RC235 1 @ 2 1K_0201_5% CFG5 EF48 BF43 1
RSVD_17 RSVD_TP_22 TP@ T303
RC236 1 2 1K_0201_5% CFG4 AA9 1
RSVD_TP_2 TP@ T304
RC237 1 @ 2 1K_0201_5% CFG3 EF51 DJ9 1 TP@ T305 +VCC_CFG_PU_OUT
RC238 1 @ 2 1K_0201_5% CFG1 RSVD_18 RSVD_TP_43
RC239 1 @ 2 1K_0201_5% CFG0 T306 TP@
1 FB58 DJ12 1 TP@ T307
1 EY61 RSVD_TP_55 RSVD_TP_42 AV12
T308 TP@ RSVD_TP_53 VCC_CFG_PU_OUT CH43 1
RSVD_TP_32 TP@ T309
EH48 DH14 1 TP@ T310
EF53 RSVD_21 RSVD_TP_39 DW32 1
Signal: CFG4 (Ref : MoW WW37) RSVD_19 RSVD_TP_44 TP@ T311
The CFG [4] pin is made Reserved. Pull -Down termination BH14 1 TP@ T312
1 DJ11 RSVD_TP_23 DW37 1
recommendation is added wherever applicable. T313 TP@ RSVD_TP_41 RSVD_TP_45 TP@ T314
AL37 1
RSVD_TP_9 TP@ T315
T316 TP@
1 EB16
1 DY18 RSVD_TP_50
T317 TP@ RSVD_TP_46

ADL-P_BGA1744
B @ B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADL-P(14/14)RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 19 of 121
5 4 3 2 1
 5 4 3 2 1

D D

C C

Reserve Page
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/06/07 Deciphered Date 2024/06/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for SOC/PCH/FCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 20 of 121
5 4 3 2 1
 5 4 3 2 1

DDRA (0,1)
+0.5V_VDDQ
UD1-1 UD1
1 2 H15 J9
ZQ_A CK_C_A DDR_M0_CLK# <8>
RD2 240_0201_1% H9
DDR_DRAMRST#_R CK_T_A DDR_M0_CLK <8> +1.8V_MEM +1.065V_MEM
H1 +0.5V_VDDQ
<8,22,23,24> DDR_DRAMRST#_R RESET# P7
CK_T_B DDR_M1_CLK <8>
N7
CK_C_B DDR_M1_CLK# <8>
G4
<8> DDR_M0_CA0 CA0_A

1
H5 CD67 CD68 CD69 CD70 CD71 CD72 CD73 CD74 CD75 CD76 CD77 CD78 CD79 CD80 CD323 CD322
<8> DDR_M0_CA1 CA1_A
G8 A4
D <8> DDR_M0_CA2 CA2_A DMI0_A D

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
H11 A12
<8> DDR_M0_CA3

2
G10 CA3_A DMI1_A
<8> DDR_M0_CA4 CA4_A
H13 AA12 SHORTEST PATH TO GND
<8> DDR_M0_CA5 CA5_A DMI0_B
G12 AA4
<8> DDR_M0_CA6 CA6_A DMI1_B
R12
<8> DDR_M1_CA0 CA0_B
P11 H7
<8> DDR_M1_CA1 CA1_B CS0_A DDR_M0_CS#0 <8>
R8 G6
<8> DDR_M1_CA2 CA2_B CS1_A DDR_M0_CS#1 <8>
P5
<8> DDR_M1_CA3 CA3_B +1.8V_MEM
R6 P9 +0.5V_VDDQ
<8> DDR_M1_CA4 CA4_B CS0_B DDR_M1_CS#0 <8> +1.065V_MEM
P3 R10 ESD
<8> DDR_M1_CA5 CA5_B CS1_B DDR_M1_CS#1 <8>
R4
<8> DDR_M1_CA6 CA6_B
1 1 2 2 2 2 1 1
D5 CD305 CD310 CC822 CC823 CC824 CC825 1 1 CD90 CD312
WCK0_C_A DDR_M0_W CK_N <8>
B3 E4 RF@ XEMC@ XEMC@ XEMC@ XEMC@ CD306 CD311 RF@
<8> DDR_M0_DQS0 RDQS0_T_A WCK0_T_A

10P_0201_50V8J

10P_0201_50V8J
10U_0402_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

10U_0402_6.3V6M
C4 RF@
<8> DDR_M0_DQS#0 RDQS0_C_A 2 2 1 1 1 1 2 2

10P_0201_50V8J
10U_0402_6.3V6M
D11
Y13 WCK1_C_A E12 2 2
<8> DDR_M1_DQS0 RDQS0_T_B WCK1_T_A DDR_M0_W CK_P <8>
W12
<8> DDR_M1_DQS#0 RDQS0_C_B
V11
WCK0_C_B DDR_M1_W CK_N <8>
Y3 U12
<8> DDR_M1_DQS1 RDQS1_T_B WCK0_T_B
W4
<8> DDR_M1_DQS#1 RDQS1_C_B V5
WCK1_C_B U4
WCK1_T_B DDR_M1_W CK_P <8>
B13
<8> DDR_M0_DQS1 RDQS1_T_A
C12
<8> DDR_M0_DQS#1 RDQS1_C_A

<8> DDR_M0_D0_[0..7] DDR_M0_D0_0 D1 V15 DDR_M1_D0_3 DDR_M1_D0_[0..7] <8>

6 caps per DRAM, 2 per short edge and 1 per long edge close to VDD2H/VDD2L BGA's
DDR_M0_D0_3 C2 DQ0_A DQ0_B W14 DDR_M1_D0_0
DDR_M0_D0_2 E2 DQ1_A DQ1_B U14 DDR_M1_D0_1
DDR_M0_D0_1 D3 DQ2_A DQ2_B V13 DDR_M1_D0_2
DDR_M0_D0_7 B5 DQ3_A DQ3_B Y11 DDR_M1_D0_5
DDR_M0_D0_5 C6 DQ4_A DQ4_B W10 DDR_M1_D0_7
DDR_M0_D0_4 E6 DQ5_A DQ5_B U10 DDR_M1_D0_4
DDR_M0_D0_6 F5 DQ6_A DQ6_B T11 DDR_M1_D0_6
<8> DDR_M0_D1_[0..7] DDR_M0_D1_5 DQ7_A DQ7_B DDR_M1_D1_4 DDR_M1_D1_[0..7] <8>
D15 V1
DDR_M0_D1_7 C14 DQ8_A DQ8_B W2 DDR_M1_D1_6
DDR_M0_D1_6 E14 DQ9_A DQ9_B U2 DDR_M1_D1_7 20210426, follow ESD request
DDR_M0_D1_4 D13 DQ10_A DQ10_B V3 DDR_M1_D1_5
DDR_M0_D1_1 B11 DQ11_A DQ11_B Y5 DDR_M1_D1_2 +0.5V_VDDQ +0.5V_VDDQ
C DDR_M0_D1_3 DQ12_A DQ12_B DDR_M1_D1_0 C
C10 W6
DDR_M0_D1_0 E10 DQ13_A DQ13_B U6 DDR_M1_D1_3
DDR_M0_D1_2 F11 DQ14_A DQ14_B T5 DDR_M1_D1_1
DQ15_A DQ15_B 1 CD45 1 CD46 1 CD47 1 CD48 1 CD49 1 CD50 1 CD91 2 2
CC831 CC832
XEMC@ XEMC@

15P_0201_50V8J

15P_0201_50V8J

15P_0201_50V8J

15P_0201_50V8J

15P_0201_50V8J

15P_0201_50V8J

15P_0201_50V8J

0.1U_0201_10V6K

0.1U_0201_10V6K
2 2 2 2 2 2 2 1 1
MT62F2G32D8DR031W _TFBGA315~D

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@
@

+1.8V_MEM UD1-2
+1.065V_MEM A5 L12
A11 VSS0 VSS51 L13
B4 VSS1 VSS52 L14
+0.5V_VDDQ B8 VSS2 VSS53 L15 +0.5V_VDDQ
UD1-3 UD1-4 B12 VSS3 VSS54 M7
C1 A7 J4 A3 C5 VSS4 VSS55 M8 CD27 CD28 CD43 CD44 CD65 CD66 CD81
C15 VDD1_0 VDD2H_0 A8 J6 RFU_0 VDDQ_0 A13 C8 VSS5 VSS56 M9
VDD1_1 VDD2H_1 RFU_1 VDDQ_1 VSS6 VSS57 1 1 1 1 1 1 1
W1 A9 P1 B2 C11 N1
W15 VDD1_2 VDD2H_2 B7 P15 RFU_2 VDDQ_2 B14 D2 VSS7 VSS58 N3
+1.065V_MEM VDD1_3 VDD2H_3 RFU_3 VDDQ_3 VSS8 VSS59

3P_0201_50V8C

3P_0201_50V8C

3P_0201_50V8C

3P_0201_50V8C

3P_0201_50V8C

3P_0201_50V8C

3P_0201_50V8C
B9 C3 D6 N4
A6 VDD2H_4 C7 VDDQ_4 C13 D7 VSS9 VSS60 N6 2 2 2 2 2 2 2
A10 VDD2L_0 VDD2H_5 C9 A1 VDDQ_5 D4 D9 VSS10 VSS61 N8
VDD2L_1 VDD2H_6 NC_0 VDDQ_6 VSS11 VSS62

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@
B6 D8 A2 D12 D10 N9
B10 VDD2L_2 VDD2H_7 E7 A14 NC_1 VDDQ_7 E5 D14 VSS12 VSS63 N10
H2 VDD2L_3 VDD2H_8 E9 A15 NC_2 VDDQ_8 E11 E1 VSS13 VSS64 N12
H14 VDD2L_4 VDD2H_9 F6 B1 NC_3 VDDQ_9 F1 E3 VSS14 VSS65 N13
J2 VDD2L_5 VDD2H_10 F7 B15 NC_4 VDDQ_10 F3 E8 VSS15 VSS66 N15
J14 VDD2L_6 VDD2H_11 F9 Y1 NC_5 VDDQ_11 F4 E13 VSS16 VSS67 P4
N2 VDD2L_7 VDD2H_12 F10 Y15 NC_6 VDDQ_12 F12 E15 VSS17 VSS68 P6
N14 VDD2L_8 VDD2H_13 J5 AA1 NC_7 VDDQ_13 F13 F2 VSS18 VSS69 P8
P2 VDD2L_9 VDD2H_14 J11 AA2 NC_8 VDDQ_14 F15 F8 VSS19 VSS70 P10
P14 VDD2L_10 VDD2H_15 K1 AA14 NC_9 VDDQ_15 G1 F14 VSS20 VSS71 P12
Y6 VDD2L_11 VDD2H_16 K2 AA15 NC_10 VDDQ_16 G2 G3 VSS21 VSS72 P13 EMI CAPS
VDD2L_12 VDD2H_17 NC_11 VDDQ_17 VSS22 VSS73
Y10
AA6 VDD2L_13 VDD2H_18
K3
K4 VDDQ_18
G14
G15
G5
G7 VSS23 VSS74
R3
R5
PLACE AS PER THE GUIDELINES FROM EMC PDG
AA10 VDD2L_14 VDD2H_19 K5 VDDQ_19 R1 G9 VSS24 VSS75 R7
VDD2L_15 VDD2H_20 K6 VDDQ_20 R2 G11 VSS25 VSS76 R9
M12 VDD2H_21 K10 VDDQ_21 R14 G13 VSS26 VSS77 R11
M13 VDD2H_41 VDD2H_22 K11 VDDQ_22 R15 H3 VSS27 VSS78 R13
M14 VDD2H_42 VDD2H_23 K12 VDDQ_23 T1 H4 VSS28 VSS79 T2
B B
M15 VDD2H_43 VDD2H_24 K13 VDDQ_24 T3 H6 VSS29 VSS80 T8
N5 VDD2H_44 VDD2H_25 K14 VDDQ_25 T4 H8 VSS30 VSS81 T14
N11 VDD2H_45 VDD2H_26 K15 VDDQ_26 T12 H10 VSS31 VSS82 U1
T6 VDD2H_46 VDD2H_27 L6 VDDQ_27 T13 H12 VSS32 VSS83 U3
T7 VDD2H_47 VDD2H_28 L7 VDDQ_28 T15 J1 VSS33 VSS84 U8
T9 VDD2H_48 VDD2H_29 L8 VDDQ_29 U5 J3 VSS34 VSS85 U13
T10 VDD2H_49 VDD2H_30 L9 VDDQ_30 U11 J7 VSS35 VSS86 U15
U7 VDD2H_50 VDD2H_31 L10 VDDQ_31 V4 J8 VSS36 VSS87 V2
U9 VDD2H_51 VDD2H_32 M1 VDDQ_32 V12 J10 VSS37 VSS88 V6
V8 VDD2H_52 VDD2H_33 M2 VDDQ_33 W3 J12 VSS38 VSS89 V7
W7 VDD2H_53 VDD2H_34 M3 VDDQ_34 W13 J13 VSS39 VSS90 V9
W9 VDD2H_54 VDD2H_35 M4 VDDQ_35 Y2 J15 VSS40 VSS91 V10
Y7 VDD2H_55 VDD2H_36 M5 VDDQ_36 Y14 K7 VSS41 VSS92 V14
Y9 VDD2H_56 VDD2H_37 M6 VDDQ_37 AA3 K8 VSS42 VSS93 W5
AA7 VDD2H_57 VDD2H_38 M10 VDDQ_38 AA13 K9 VSS43 VSS94 W8
AA8 VDD2H_58 VDD2H_39 M11 VDDQ_39 L1 VSS44 VSS95 W11
AA9 VDD2H_59 VDD2H_40 L2 VSS45 VSS96 Y4
VDD2H_60 L3 VSS46 VSS97 Y8
MT62F2G32D8DR031W _TFBGA315~D-X L4 VSS47 VSS98 Y12
L5 VSS48 VSS99 AA5
@

MT62F2G32D8DR031W _TFBGA315~D-X L11 VSS49 VSS100 AA11

VSS50 VSS101
@

MT62F2G32D8DR031W _TFBGA315~D-X
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/5/30 Deciphered Date 2018/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPDDR5 Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 21 of 121
5 4 3 2 1
 5 4 3 2 1

+0.5V_VDDQ
DDRB (2,3)
RD21 1 2 240_0201_1% H15
UD2-1

ZQ_A CK_C_A
J9
H9
DDR_M2_CLK# <8>
UD2
DDR_DRAMRST#_R CK_T_A DDR_M2_CLK <8>
H1
<8,21,23,24> DDR_DRAMRST#_R RESET# P7
CK_T_B DDR_M3_CLK <8> +1.8V_MEM +1.065V_MEM
N7 +0.5V_VDDQ
CK_C_B DDR_M3_CLK# <8>
G4
<8> DDR_M2_CA0 CA0_A
H5
<8> DDR_M2_CA1 CA1_A
G8 A4
<8> DDR_M2_CA2 CA2_A DMI0_A

1
H11 A12 CD332 CD330 CD329 CD335 CD338 CD334 CD345 CD341 CD344 CD339 CD336 CD337 CD342 CD326 CD325 CD324
<8> DDR_M2_CA3 CA3_A DMI1_A
G10
D <8> DDR_M2_CA4 CA4_A D

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
H13 AA12 SHORTEST PATH TO GND
<8> DDR_M2_CA5

2
G12 CA5_A DMI0_B AA4
<8> DDR_M2_CA6 CA6_A DMI1_B
R12
<8> DDR_M3_CA0 CA0_B
P11 H7
<8> DDR_M3_CA1 CA1_B CS0_A DDR_M2_CS#0 <8>
R8 G6
<8> DDR_M3_CA2 CA2_B CS1_A DDR_M2_CS#1 <8>
P5
<8> DDR_M3_CA3 CA3_B
R6 P9
<8> DDR_M3_CA4 CA4_B CS0_B DDR_M3_CS#0 <8>
P3 R10
<8> DDR_M3_CA5 CA5_B CS1_B DDR_M3_CS#1 <8> +1.8V_MEM +1.065V_MEM
R4 +0.5V_VDDQ
<8> DDR_M3_CA6 CA6_B
D5
WCK0_C_A DDR_M2_W CK_N <8>
<8> DDR_M2_DQS0
B3 E4 1 1 1 1 1 1
C4 RDQS0_T_A WCK0_T_A CD328 CD343 CD333 CD340 CD331 CD327
<8> DDR_M2_DQS#0 RDQS0_C_A D11 RF@ RF@ RF@
WCK1_C_A

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
<8> DDR_M3_DQS0 Y13 E12
RDQS0_T_B WCK1_T_A DDR_M2_W CK_P <8> 2 2 2 2 2 2
W12
<8> DDR_M3_DQS#0 RDQS0_C_B
V11
WCK0_C_B DDR_M3_W CK_N <8>
<8> DDR_M3_DQS1
Y3 U12
W4 RDQS1_T_B WCK0_T_B
<8> DDR_M3_DQS#1 RDQS1_C_B V5
WCK1_C_B U4
WCK1_T_B DDR_M3_W CK_P <8>
B13
<8> DDR_M2_DQS1 RDQS1_T_A
C12
<8> DDR_M2_DQS#1 RDQS1_C_A

<8> DDR_M2_D0_[0..7] DDR_M2_D0_0 DDR_M3_D0_2 DDR_M3_D0_[0..7] <8>

D1 V15
DDR_M2_D0_3
DDR_M2_D0_2
C2
E2
DQ0_A
DQ1_A
DQ0_B
DQ1_B
W14
U14
DDR_M3_D0_0
DDR_M3_D0_1
6 caps per DRAM, 2 per short edge and 1 per long edge close to VDD2H/VDD2L BGA's
DDR_M2_D0_1 D3 DQ2_A DQ2_B V13 DDR_M3_D0_3
DDR_M2_D0_7 B5 DQ3_A DQ3_B Y11 DDR_M3_D0_4
DDR_M2_D0_5 C6 DQ4_A DQ4_B W10 DDR_M3_D0_7 +1.065V_MEM
DDR_M2_D0_4 E6 DQ5_A DQ5_B U10 DDR_M3_D0_5
DDR_M2_D0_6 F5 DQ6_A DQ6_B T11 DDR_M3_D0_6
<8> DDR_M2_D1_[0..7] DDR_M2_D1_4 DQ7_A DQ7_B DDR_M3_D1_4 DDR_M3_D1_[0..7] <8>
D15 V1
DDR_M2_D1_6 C14 DQ8_A DQ8_B W2 DDR_M3_D1_5
DQ9_A DQ9_B 1 1

1
DDR_M2_D1_5 E14 U2 DDR_M3_D1_6 CD394 CD393 CD400 @
DDR_M2_D1_7 D13 DQ10_A DQ10_B V3 DDR_M3_D1_7
DQ11_A DQ11_B

10U_0402_6.3V6M

1U_0201_10V6M

10U_0402_6.3V6M
DDR_M2_D1_1 B11 Y5 DDR_M3_D1_2

2
DDR_M2_D1_3 C10 DQ12_A DQ12_B W6 DDR_M3_D1_0 2 2
DDR_M2_D1_0 E10 DQ13_A DQ13_B U6 DDR_M3_D1_3
C DDR_M2_D1_2 DQ14_A DQ14_B DDR_M3_D1_1 C
F11 T5
DQ15_A DQ15_B

MT62F2G32D8DR031W _TFBGA315~D
@
Near UD2
1.A add

+1.8V_MEM UD2-2
A5 L12
A11 VSS0 VSS51 L13
+1.065V_MEM +0.5V_VDDQ B4 VSS1 VSS52 L14
UD2-4 B8 VSS2 VSS53 L15
UD2-3 J4 A3 B12 VSS3 VSS54 M7
C1 A7 J6 RFU_0 VDDQ_0 A13 C5 VSS4 VSS55 M8
C15 VDD1_0 VDD2H_0 A8 P1 RFU_1 VDDQ_1 B2 C8 VSS5 VSS56 M9
W1 VDD1_1 VDD2H_1 A9 P15 RFU_2 VDDQ_2 B14 C11 VSS6 VSS57 N1
W15 VDD1_2 VDD2H_2 B7 RFU_3 VDDQ_3 C3 D2 VSS7 VSS58 N3
+1.065V_MEM VDD1_3 VDD2H_3 B9 VDDQ_4 C13 D6 VSS8 VSS59 N4
A6 VDD2H_4 C7 A1 VDDQ_5 D4 D7 VSS9 VSS60 N6
A10 VDD2L_0 VDD2H_5 C9 A2 NC_0 VDDQ_6 D12 D9 VSS10 VSS61 N8
B6 VDD2L_1 VDD2H_6 D8 A14 NC_1 VDDQ_7 E5 D10 VSS11 VSS62 N9
B10 VDD2L_2 VDD2H_7 E7 A15 NC_2 VDDQ_8 E11 D14 VSS12 VSS63 N10
H2 VDD2L_3 VDD2H_8 E9 B1 NC_3 VDDQ_9 F1 E1 VSS13 VSS64 N12
H14 VDD2L_4 VDD2H_9 F6 B15 NC_4 VDDQ_10 F3 E3 VSS14 VSS65 N13
J2 VDD2L_5 VDD2H_10 F7 Y1 NC_5 VDDQ_11 F4 E8 VSS15 VSS66 N15
J14 VDD2L_6 VDD2H_11 F9 Y15 NC_6 VDDQ_12 F12 E13 VSS16 VSS67 P4
N2 VDD2L_7 VDD2H_12 F10 AA1 NC_7 VDDQ_13 F13 E15 VSS17 VSS68 P6
N14 VDD2L_8 VDD2H_13 J5 AA2 NC_8 VDDQ_14 F15 F2 VSS18 VSS69 P8
P2 VDD2L_9 VDD2H_14 J11 AA14 NC_9 VDDQ_15 G1 F8 VSS19 VSS70 P10
P14 VDD2L_10 VDD2H_15 K1 AA15 NC_10 VDDQ_16 G2 F14 VSS20 VSS71 P12
Y6 VDD2L_11 VDD2H_16 K2 NC_11 VDDQ_17 G14 G3 VSS21 VSS72 P13
Y10 VDD2L_12 VDD2H_17 K3 VDDQ_18 G15 G5 VSS22 VSS73 R3
AA6 VDD2L_13 VDD2H_18 K4 VDDQ_19 R1 G7 VSS23 VSS74 R5
AA10 VDD2L_14 VDD2H_19 K5 VDDQ_20 R2 G9 VSS24 VSS75 R7
VDD2L_15 VDD2H_20 K6 VDDQ_21 R14 G11 VSS25 VSS76 R9
M12 VDD2H_21 K10 VDDQ_22 R15 G13 VSS26 VSS77 R11
M13 VDD2H_41 VDD2H_22 K11 VDDQ_23 T1 H3 VSS27 VSS78 R13
B B
M14 VDD2H_42 VDD2H_23 K12 VDDQ_24 T3 H4 VSS28 VSS79 T2
M15 VDD2H_43 VDD2H_24 K13 VDDQ_25 T4 H6 VSS29 VSS80 T8
N5 VDD2H_44 VDD2H_25 K14 VDDQ_26 T12 H8 VSS30 VSS81 T14
N11 VDD2H_45 VDD2H_26 K15 VDDQ_27 T13 H10 VSS31 VSS82 U1
T6 VDD2H_46 VDD2H_27 L6 VDDQ_28 T15 H12 VSS32 VSS83 U3
T7 VDD2H_47 VDD2H_28 L7 VDDQ_29 U5 J1 VSS33 VSS84 U8
T9 VDD2H_48 VDD2H_29 L8 VDDQ_30 U11 J3 VSS34 VSS85 U13
T10 VDD2H_49 VDD2H_30 L9 VDDQ_31 V4 J7 VSS35 VSS86 U15
U7 VDD2H_50 VDD2H_31 L10 VDDQ_32 V12 J8 VSS36 VSS87 V2
U9 VDD2H_51 VDD2H_32 M1 VDDQ_33 W3 J10 VSS37 VSS88 V6
V8 VDD2H_52 VDD2H_33 M2 VDDQ_34 W13 J12 VSS38 VSS89 V7
W7 VDD2H_53 VDD2H_34 M3 VDDQ_35 Y2 J13 VSS39 VSS90 V9
W9 VDD2H_54 VDD2H_35 M4 VDDQ_36 Y14 J15 VSS40 VSS91 V10
Y7 VDD2H_55 VDD2H_36 M5 VDDQ_37 AA3 K7 VSS41 VSS92 V14
Y9 VDD2H_56 VDD2H_37 M6 VDDQ_38 AA13 K8 VSS42 VSS93 W5
AA7 VDD2H_57 VDD2H_38 M10 VDDQ_39 K9 VSS43 VSS94 W8
AA8 VDD2H_58 VDD2H_39 M11 L1 VSS44 VSS95 W11
AA9 VDD2H_59 VDD2H_40 L2 VSS45 VSS96 Y4
VDD2H_60 MT62F2G32D8DR031W _TFBGA315~D-X L3 VSS46 VSS97 Y8
L4 VSS47 VSS98 Y12
@ VSS48 VSS99
L5 AA5
MT62F2G32D8DR031W _TFBGA315~D-X L11 VSS49 VSS100 AA11
VSS50 VSS101
@

MT62F2G32D8DR031W _TFBGA315~D-X
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/5/30 Deciphered Date 2018/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPDDR5 Channel B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 22 of 121
5 4 3 2 1
 A B C D E

DDRC (4,5)
+0.5V_VDDQ

RD4
1 2 H15
240_0201_1%
UD3-1

ZQ_A CK_C_A
J9
H9
DDR_M4_CLK# <8>
UD3
DDR_DRAMRST#_R CK_T_A DDR_M4_CLK <8>
H1
<8,21,22,24> DDR_DRAMRST#_R RESET# P7 DDR_M5_CLK <8>
CK_T_B N7 +1.8V_MEM +1.065V_MEM +0.5V_VDDQ
1 CK_C_B DDR_M5_CLK# <8> 1
<8> DDR_M4_CA0 G4
H5 CA0_A
<8> DDR_M4_CA1 CA1_A
<8> DDR_M4_CA2
G8 A4
CA2_A DMI0_A

1
<8> DDR_M4_CA3
H11 A12 CD354 CD352 CD351 CD357 CD360 CD356 CD367 CD363 CD366 CD361 CD358 CD359 CD364 CD348 CD347 CD346
G10 CA3_A DMI1_A
<8> DDR_M4_CA4 CA4_A

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
<8> DDR_M4_CA5 H13 AA12

2
G12 CA5_A DMI0_B AA4
<8> DDR_M4_CA6 CA6_A DMI1_B
R12
<8> DDR_M5_CA0 CA0_B
P11 H7
<8> DDR_M5_CA1 CA1_B CS0_A DDR_M4_CS#0 <8>
<8> DDR_M5_CA2 R8 G6 DDR_M4_CS#1 <8>
P5 CA2_B CS1_A
<8> DDR_M5_CA3 CA3_B
<8> DDR_M5_CA4
R6 P9 DDR_M5_CS#0 <8>
P3 CA4_B CS0_B R10
<8> DDR_M5_CA5 CA5_B CS1_B DDR_M5_CS#1 <8> +1.8V_MEM +1.065V_MEM
<8> DDR_M5_CA6
R4 +0.5V_VDDQ
CA6_B
D5
WCK0_C_A DDR_M4_W CK_N <8>
B3 E4 1 1 1 1 1 1
<8> DDR_M4_DQS0 RDQS0_T_A WCK0_T_A
C4 CD350 CD365 CD355 CD362 CD353 CD349
<8> DDR_M4_DQS#0 RDQS0_C_A D11 RF@ RF@ RF@
WCK1_C_A

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
Y13 E12 DDR_M4_W CK_P <8>
<8> DDR_M5_DQS0 RDQS0_T_B WCK1_T_A 2 2 2 2 2 2
W12
<8> DDR_M5_DQS#0 RDQS0_C_B
V11
WCK0_C_B DDR_M5_W CK_N <8>
Y3 U12
<8> DDR_M5_DQS1 RDQS1_T_B WCK0_T_B
W4
<8> DDR_M5_DQS#1 RDQS1_C_B V5
WCK1_C_B U4
WCK1_T_B DDR_M5_W CK_P <8>
B13
<8> DDR_M4_DQS1 RDQS1_T_A
C12
<8> DDR_M4_DQS#1 RDQS1_C_A

<8> DDR_M4_D1_[0..7] DDR_M4_D0_0 DDR_M5_D0_3 DDR_M5_D0_[0..7] <8>

D1 V15
DDR_M4_D0_3
DDR_M4_D0_2
C2
E2
DQ0_A
DQ1_A
DQ0_B
DQ1_B
W14
U14
DDR_M5_D0_1
DDR_M5_D0_0
6 caps per DRAM, 2 per short edge and 1 per long edge close to VDD2H/VDD2L BGA's
DDR_M4_D0_1 D3 DQ2_A DQ2_B V13 DDR_M5_D0_2
<8,23> DDR_M4_D0_[0..7] DDR_M4_D0_7 DQ3_A DQ3_B DDR_M5_D0_5
B5 Y11
DDR_M4_D0_5 C6 DQ4_A DQ4_B W10 DDR_M5_D0_7
DDR_M4_D0_4 E6 DQ5_A DQ5_B U10 DDR_M5_D0_4
DDR_M4_D0_6 F5 DQ6_A DQ6_B T11 DDR_M5_D0_6
<8,23> DDR_M4_D0_[0..7] DDR_M4_D1_4 DQ7_A DQ7_B DDR_M5_D1_4 DDR_M5_D1_[0..7] <8>
D15 V1
DDR_M4_D1_5 C14 DQ8_A DQ8_B W2 DDR_M5_D1_6
2 DDR_M4_D1_6 DQ9_A DQ9_B DDR_M5_D1_7 2
E14 U2
DDR_M4_D1_7 D13 DQ10_A DQ10_B V3 DDR_M5_D1_5 +1.065V_MEM
DDR_M4_D1_0 B11 DQ11_A DQ11_B Y5 DDR_M5_D1_2
DDR_M4_D1_3 C10 DQ12_A DQ12_B W6 DDR_M5_D1_0
DDR_M4_D1_1 E10 DQ13_A DQ13_B U6 DDR_M5_D1_3
DDR_M4_D1_2 F11 DQ14_A DQ14_B T5 DDR_M5_D1_1
DQ15_A DQ15_B 1

1
CD395 CD396 CD397 @

10U_0402_6.3V6M

1U_0201_10V6M

22U_0603_6.3V6M
2

2
2
MT62F2G32D8DR031W _TFBGA315~D
@

UD3-2 +1.8V_MEM
A5 L12 +1.065V_MEM
A11 VSS0 VSS51 L13
B4 VSS1 VSS52 L14 +0.5V_VDDQ
B8
B12
VSS2
VSS3
VSS53
VSS54
L15
M7 UD3-3 J4
UD3-4
A3
Near UD3
C5 VSS4 VSS55 M8 C1 A7 J6 RFU_0 VDDQ_0 A13
C8 VSS5 VSS56 M9 C15 VDD1_0 VDD2H_0 A8 P1 RFU_1 VDDQ_1 B2 1.A add
C11 VSS6 VSS57 N1 W1 VDD1_1 VDD2H_1 A9 P15 RFU_2 VDDQ_2 B14
D2 VSS7 VSS58 N3 W15 VDD1_2 VDD2H_2 B7 RFU_3 VDDQ_3 C3
D6 VSS8 VSS59 N4 +1.065V_MEM VDD1_3 VDD2H_3 B9 VDDQ_4 C13
D7 VSS9 VSS60 N6 A6 VDD2H_4 C7 A1 VDDQ_5 D4
D9 VSS10 VSS61 N8 A10 VDD2L_0 VDD2H_5 C9 A2 NC_0 VDDQ_6 D12
D10 VSS11 VSS62 N9 B6 VDD2L_1 VDD2H_6 D8 A14 NC_1 VDDQ_7 E5
D14 VSS12 VSS63 N10 B10 VDD2L_2 VDD2H_7 E7 A15 NC_2 VDDQ_8 E11
E1 VSS13 VSS64 N12 H2 VDD2L_3 VDD2H_8 E9 B1 NC_3 VDDQ_9 F1
E3 VSS14 VSS65 N13 H14 VDD2L_4 VDD2H_9 F6 B15 NC_4 VDDQ_10 F3
E8 VSS15 VSS66 N15 J2 VDD2L_5 VDD2H_10 F7 Y1 NC_5 VDDQ_11 F4
E13 VSS16 VSS67 P4 J14 VDD2L_6 VDD2H_11 F9 Y15 NC_6 VDDQ_12 F12
E15 VSS17 VSS68 P6 N2 VDD2L_7 VDD2H_12 F10 AA1 NC_7 VDDQ_13 F13
F2 VSS18 VSS69 P8 N14 VDD2L_8 VDD2H_13 J5 AA2 NC_8 VDDQ_14 F15
F8 VSS19 VSS70 P10 P2 VDD2L_9 VDD2H_14 J11 AA14 NC_9 VDDQ_15 G1
F14 VSS20 VSS71 P12 P14 VDD2L_10 VDD2H_15 K1 AA15 NC_10 VDDQ_16 G2
G3 VSS21 VSS72 P13 Y6 VDD2L_11 VDD2H_16 K2 NC_11 VDDQ_17 G14
G5 VSS22 VSS73 R3 Y10 VDD2L_12 VDD2H_17 K3 VDDQ_18 G15
G7 VSS23 VSS74 R5 AA6 VDD2L_13 VDD2H_18 K4 VDDQ_19 R1
G9 VSS24 VSS75 R7 AA10 VDD2L_14 VDD2H_19 K5 VDDQ_20 R2
G11 VSS25 VSS76 R9 VDD2L_15 VDD2H_20 K6 VDDQ_21 R14
3 3
G13 VSS26 VSS77 R11 M12 VDD2H_21 K10 VDDQ_22 R15
H3 VSS27 VSS78 R13 M13 VDD2H_41 VDD2H_22 K11 VDDQ_23 T1
H4 VSS28 VSS79 T2 M14 VDD2H_42 VDD2H_23 K12 VDDQ_24 T3
H6 VSS29 VSS80 T8 M15 VDD2H_43 VDD2H_24 K13 VDDQ_25 T4
H8 VSS30 VSS81 T14 N5 VDD2H_44 VDD2H_25 K14 VDDQ_26 T12
H10 VSS31 VSS82 U1 N11 VDD2H_45 VDD2H_26 K15 VDDQ_27 T13
H12 VSS32 VSS83 U3 T6 VDD2H_46 VDD2H_27 L6 VDDQ_28 T15
J1 VSS33 VSS84 U8 T7 VDD2H_47 VDD2H_28 L7 VDDQ_29 U5
J3 VSS34 VSS85 U13 T9 VDD2H_48 VDD2H_29 L8 VDDQ_30 U11
J7 VSS35 VSS86 U15 T10 VDD2H_49 VDD2H_30 L9 VDDQ_31 V4
J8 VSS36 VSS87 V2 U7 VDD2H_50 VDD2H_31 L10 VDDQ_32 V12
J10 VSS37 VSS88 V6 U9 VDD2H_51 VDD2H_32 M1 VDDQ_33 W3
J12 VSS38 VSS89 V7 V8 VDD2H_52 VDD2H_33 M2 VDDQ_34 W13
J13 VSS39 VSS90 V9 W7 VDD2H_53 VDD2H_34 M3 VDDQ_35 Y2
J15 VSS40 VSS91 V10 W9 VDD2H_54 VDD2H_35 M4 VDDQ_36 Y14
K7 VSS41 VSS92 V14 Y7 VDD2H_55 VDD2H_36 M5 VDDQ_37 AA3
K8 VSS42 VSS93 W5 Y9 VDD2H_56 VDD2H_37 M6 VDDQ_38 AA13
K9 VSS43 VSS94 W8 AA7 VDD2H_57 VDD2H_38 M10 VDDQ_39
L1 VSS44 VSS95 W11 AA8 VDD2H_58 VDD2H_39 M11
L2 VSS45 VSS96 Y4 AA9 VDD2H_59 VDD2H_40
L3 VSS46 VSS97 Y8 VDD2H_60 MT62F2G32D8DR031W _TFBGA315~D-X
L4 VSS47 VSS98 Y12
VSS48 VSS99 @
L5 AA5
L11 VSS49 VSS100 AA11 MT62F2G32D8DR031W _TFBGA315~D-X
VSS50 VSS101
@

MT62F2G32D8DR031W _TFBGA315~D-X
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/5/30 Deciphered Date 2018/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPDDR5 Channel C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 23 of 121
A B C D E
 5 4 3 2 1

DDRD (6,7) UD4

+0.5V_VDDQ
UD4-1
+1.8V_MEM +1.065V_MEM +0.5V_VDDQ
RD23 1 2 240_0201_1%H15 J9 DDR_M6_CLK# <8>
ZQ_A CK_C_A H9
DDR_DRAMRST#_R CK_T_A DDR_M6_CLK <8>
H1
<8,21,22,23> DDR_DRAMRST#_R RESET#

1
P7 CD376 CD374 CD373 CD379 CD382 CD378 CD389 CD385 CD388 CD383 CD380 CD381 CD386 CD370 CD369 CD368
CK_T_B DDR_M7_CLK <8>
N7 DDR_M7_CLK# <8>
CK_C_B

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
G4
<8> DDR_M6_CA0

2
H5 CA0_A
<8> DDR_M6_CA1 CA1_A
<8> DDR_M6_CA2
G8 A4
H11 CA2_A DMI0_A A12
D <8> DDR_M6_CA3 CA3_A DMI1_A D
<8> DDR_M6_CA4 G10
H13 CA4_A AA12
<8> DDR_M6_CA5 CA5_A DMI0_B
<8> DDR_M6_CA6
G12 AA4
CA6_A DMI1_B
R12
<8> DDR_M7_CA0 CA0_B +1.8V_MEM +1.065V_MEM
<8> DDR_M7_CA1 P11 H7 DDR_M6_CS#0 <8> +0.5V_VDDQ 1.A add
R8 CA1_B CS0_A G6 near PJM5 near UD4
<8> DDR_M7_CA2 CA2_B CS1_A DDR_M6_CS#1 <8>
P5
<8> DDR_M7_CA3 CA3_B
R6 P9 1 1 1 1 1 1 @
<8> DDR_M7_CA4 CA4_B CS0_B DDR_M7_CS#0 <8>

1
P3 R10 CD372 CD387 CD377 CD384 CD375 CD371 CD390 CD391 CD392
<8> DDR_M7_CA5 CA5_B CS1_B DDR_M7_CS#1 <8>
<8> DDR_M7_CA6 R4 RF@ RF@ RF@
CA6_B

10P_0201_50V8J

10P_0201_50V8J

10P_0201_50V8J
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
2

2
D5 2 2 2 2 2 2
WCK0_C_A DDR_M6_W CK_N <8>
B3 E4
<8> DDR_M6_DQS1 RDQS0_T_A WCK0_T_A
C4
<8> DDR_M6_DQS#1 RDQS0_C_A D11
Y13 WCK1_C_A E12
<8> DDR_M7_DQS0 RDQS0_T_B WCK1_T_A DDR_M6_W CK_P <8>
W12
<8> DDR_M7_DQS#0 RDQS0_C_B
V11 DDR_M7_W CK_N <8>
Y3 WCK0_C_B U12
<8> DDR_M7_DQS1 RDQS1_T_B WCK0_T_B
W4
<8> DDR_M7_DQS#1 RDQS1_C_B V5
WCK1_C_B U4
<8> DDR_M6_DQS0
B13
C12 RDQS1_T_A
WCK1_T_B DDR_M7_W CK_P <8>
6 caps per DRAM, 2 per short edge and 1 per long edge close to VDD2H/VDD2L BGA's
<8> DDR_M6_DQS#0 RDQS1_C_A

<8> DDR_M6_D1_[0..7] DDR_M6_D1_3 DDR_M7_D0_2 DDR_M7_D0_[0..7] <8>

D1 V15
DDR_M6_D1_0 C2 DQ0_A DQ0_B W14 DDR_M7_D0_0
DDR_M6_D1_1 E2 DQ1_A DQ1_B U14 DDR_M7_D0_3
DDR_M6_D1_2 D3 DQ2_A DQ2_B V13 DDR_M7_D0_1
DDR_M6_D1_7 B5 DQ3_A DQ3_B Y11 DDR_M7_D0_5
DDR_M6_D1_4 C6 DQ4_A DQ4_B W10 DDR_M7_D0_7
DDR_M6_D1_5 E6 DQ5_A DQ5_B U10 DDR_M7_D0_4
DDR_M6_D1_6 F5 DQ6_A DQ6_B T11 DDR_M7_D0_6
<8> DDR_M6_D0_[0..7] DDR_M6_D0_4 DQ7_A DQ7_B DDR_M7_D1_5 DDR_M7_D1_[0..7] <8> +1.065V_MEM
D15 V1
DDR_M6_D0_7 C14 DQ8_A DQ8_B W2 DDR_M7_D1_6
DDR_M6_D0_6 E14 DQ9_A DQ9_B U2 DDR_M7_D1_2
DDR_M6_D0_5 D13 DQ10_A DQ10_B V3 DDR_M7_D1_3
DQ11_A DQ11_B 1 1
DDR_M6_D0_1 B11 Y5 DDR_M7_D1_7 CD398 CD399
DDR_M6_D0_3 C10 DQ12_A DQ12_B W6 DDR_M7_D1_4
C DQ13_A DQ13_B Near UC1.AR43 Near UC1.CE44 C

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
DDR_M6_D0_0 E10 U6 DDR_M7_D1_0
DDR_M6_D0_2 F11 DQ14_A DQ14_B T5 DDR_M7_D1_1 2 2
DQ15_A DQ15_B

MT62F2G32D8DR031W _TFBGA315~D
@

UD4-2 1.A add

+1.8V_MEM A5 L12
+1.065V_MEM A11 VSS0 VSS51 L13
+0.5V_VDDQ B4 VSS1 VSS52 L14
UD4-4 B8 VSS2 VSS53 L15
J4 A3 B12 VSS3 VSS54 M7
UD4-3 J6 RFU_0 VDDQ_0 A13 C5 VSS4 VSS55 M8
C1 A7 P1 RFU_1 VDDQ_1 B2 C8 VSS5 VSS56 M9
C15 VDD1_0 VDD2H_0 A8 P15 RFU_2 VDDQ_2 B14 C11 VSS6 VSS57 N1
W1 VDD1_1 VDD2H_1 A9 RFU_3 VDDQ_3 C3 D2 VSS7 VSS58 N3
W15 VDD1_2 VDD2H_2 B7 VDDQ_4 C13 D6 VSS8 VSS59 N4
+1.065V_MEM VDD1_3 VDD2H_3 B9 A1 VDDQ_5 D4 D7 VSS9 VSS60 N6
A6 VDD2H_4 C7 A2 NC_0 VDDQ_6 D12 D9 VSS10 VSS61 N8
A10 VDD2L_0 VDD2H_5 C9 A14 NC_1 VDDQ_7 E5 D10 VSS11 VSS62 N9
B6 VDD2L_1 VDD2H_6 D8 A15 NC_2 VDDQ_8 E11 D14 VSS12 VSS63 N10
B10 VDD2L_2 VDD2H_7 E7 B1 NC_3 VDDQ_9 F1 E1 VSS13 VSS64 N12
H2 VDD2L_3 VDD2H_8 E9 B15 NC_4 VDDQ_10 F3 E3 VSS14 VSS65 N13
H14 VDD2L_4 VDD2H_9 F6 Y1 NC_5 VDDQ_11 F4 E8 VSS15 VSS66 N15
J2 VDD2L_5 VDD2H_10 F7 Y15 NC_6 VDDQ_12 F12 E13 VSS16 VSS67 P4
J14 VDD2L_6 VDD2H_11 F9 AA1 NC_7 VDDQ_13 F13 E15 VSS17 VSS68 P6
N2 VDD2L_7 VDD2H_12 F10 AA2 NC_8 VDDQ_14 F15 F2 VSS18 VSS69 P8
N14 VDD2L_8 VDD2H_13 J5 AA14 NC_9 VDDQ_15 G1 F8 VSS19 VSS70 P10
P2 VDD2L_9 VDD2H_14 J11 AA15 NC_10 VDDQ_16 G2 F14 VSS20 VSS71 P12
P14 VDD2L_10 VDD2H_15 K1 NC_11 VDDQ_17 G14 G3 VSS21 VSS72 P13
Y6 VDD2L_11 VDD2H_16 K2 VDDQ_18 G15 G5 VSS22 VSS73 R3
Y10 VDD2L_12 VDD2H_17 K3 VDDQ_19 R1 G7 VSS23 VSS74 R5
AA6 VDD2L_13 VDD2H_18 K4 VDDQ_20 R2 G9 VSS24 VSS75 R7
AA10 VDD2L_14 VDD2H_19 K5 VDDQ_21 R14 G11 VSS25 VSS76 R9
VDD2L_15 VDD2H_20 K6 VDDQ_22 R15 G13 VSS26 VSS77 R11
M12 VDD2H_21 K10 VDDQ_23 T1 H3 VSS27 VSS78 R13
M13 VDD2H_41 VDD2H_22 K11 VDDQ_24 T3 H4 VSS28 VSS79 T2
B B
M14 VDD2H_42 VDD2H_23 K12 VDDQ_25 T4 H6 VSS29 VSS80 T8
M15 VDD2H_43 VDD2H_24 K13 VDDQ_26 T12 H8 VSS30 VSS81 T14
N5 VDD2H_44 VDD2H_25 K14 VDDQ_27 T13 H10 VSS31 VSS82 U1
N11 VDD2H_45 VDD2H_26 K15 VDDQ_28 T15 H12 VSS32 VSS83 U3
T6 VDD2H_46 VDD2H_27 L6 VDDQ_29 U5 J1 VSS33 VSS84 U8
T7 VDD2H_47 VDD2H_28 L7 VDDQ_30 U11 J3 VSS34 VSS85 U13
T9 VDD2H_48 VDD2H_29 L8 VDDQ_31 V4 J7 VSS35 VSS86 U15
T10 VDD2H_49 VDD2H_30 L9 VDDQ_32 V12 J8 VSS36 VSS87 V2
U7 VDD2H_50 VDD2H_31 L10 VDDQ_33 W3 J10 VSS37 VSS88 V6
U9 VDD2H_51 VDD2H_32 M1 VDDQ_34 W13 J12 VSS38 VSS89 V7
V8 VDD2H_52 VDD2H_33 M2 VDDQ_35 Y2 J13 VSS39 VSS90 V9
W7 VDD2H_53 VDD2H_34 M3 VDDQ_36 Y14 J15 VSS40 VSS91 V10
W9 VDD2H_54 VDD2H_35 M4 VDDQ_37 AA3 K7 VSS41 VSS92 V14
Y7 VDD2H_55 VDD2H_36 M5 VDDQ_38 AA13 K8 VSS42 VSS93 W5
Y9 VDD2H_56 VDD2H_37 M6 VDDQ_39 K9 VSS43 VSS94 W8
AA7 VDD2H_57 VDD2H_38 M10 L1 VSS44 VSS95 W11
AA8 VDD2H_58 VDD2H_39 M11 L2 VSS45 VSS96 Y4
AA9 VDD2H_59 VDD2H_40 MT62F2G32D8DR031W _TFBGA315~D-X L3 VSS46 VSS97 Y8
VDD2H_60 L4 VSS47 VSS98 Y12
@ VSS48 VSS99
L5 AA5
L11 VSS49 VSS100 AA11
MT62F2G32D8DR031W _TFBGA315~D-X VSS50 VSS101
@

MT62F2G32D8DR031W _TFBGA315~D-X
@

Follow Intel RVP for LP5 sequence #631600

Remove TD LPDDR5 sequence control circuit

A
Due to PWR IC can meet LPDDR5 sequence A

+1.8V_MEM

+1.065V_MEM
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2021/5/30 Deciphered Date 2018/10/01 Title

+0.5V_VDDQ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPDDR5 Channel D&Seq.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 24 of 121
5 4 3 2 1
 5 4 3 2 1

AMD FP6 only support x8

UV1A
GN20-E7

+1.8VSDGPU_AON BGA2714
COMMON

+PEX_VDD

2
1/24 PCI_EXPRESS
RV501 VGA@
10K_0201_5% BR31 PEX_WAKE

1 CV21

1 CV22
10/20 PEX_DVDD BF32
change net name from VGA_CLKREQ#_R to CLKREQ_PCIE#0_R PLTRST_VGA#_1V8

CV18

CV19

CV20

22U_0603_6.3V6M

22U_0603_6.3V6M
BT30 PEX_RST PEX_DVDD BF34
<26> PLTRST_VGA#_1V8

VGA@ CV10

VGA@ CV11

VGA@ CV12

VGA@ CV13

VGA@ CV14

VGA@ CV15

VGA@ CV16

VGA@ CV17
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
BF35

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PEX_DVDD 1 1 1 1 1 1 1 1 1 1 1
D CLKREQ_PCIE#0_R BP31 BF37 D
<26> CLKREQ_PCIE#0_R PEX_CLKREQ PEX_DVDD
Intel/AMD naming PEX_DVDD BG32
CLK_PEG_VGA

VGA@

VGA@

VGA@
BJ30 PEX_REFCLK PEX_DVDD BG34
<11> CLK_PEG_VGA

VGA@ 2

VGA@ 2
CLK_PEG_VGA# BK30 BG35 2 2 2 2 2 2 2 2 2 2 2
<11> CLK_PEG_VGA# PEX_REFCLK PEX_DVDD
PEX_DVDD BG37
PCIE5_CRX_C_GTX_P0 BL31 PEX_TX0 PEX_DVDD BH32
<13> PCIE5_CRX_C_GTX_P0
PCIE5_CRX_C_GTX_N0 BM31 PEX_TX0 PEX_DVDD BH34
<13> PCIE5_CRX_C_GTX_N0
PEX_DVDD BH35
PCIE5_CTX_C_GRX_P0 BR32 PEX_RX0 PEX_DVDD BH37 Under GPU Near GPU
<13> PCIE5_CTX_C_GRX_P0 PCIE5_CTX_C_GRX_N0 BT32 PEX_RX0
<13> PCIE5_CTX_C_GRX_N0
PCIE5_CRX_C_GTX_P1 BJ32 PEX_TX1 1U_0402*6(X6S) 10U_0805*3
<13> PCIE5_CRX_C_GTX_P1
PCIE5_CRX_C_GTX_N1 BK32 PEX_TX1 4.7U_0603*2(X6S) 22U_0805*2
<13> PCIE5_CRX_C_GTX_N1
PEX_CVDD BF31
PCIE5_CTX_C_GRX_P1 BP33 PEX_RX1 PEX_CVDD BG31
<13> PCIE5_CTX_C_GRX_P1 PCIE5_CTX_C_GRX_N1 BR33 PEX_RX1 PEX_CVDD BH31
<13> PCIE5_CTX_C_GRX_N1
PCIE5_CRX_C_GTX_P2 BL33 PEX_TX2
<13> PCIE5_CRX_C_GTX_P2
PCIE5_CRX_C_GTX_N2 BM33 PEX_TX2
<13> PCIE5_CRX_C_GTX_N2
PCIE5_CTX_C_GRX_P2 BR34 PEX_RX2
<13> PCIE5_CTX_C_GRX_P2 PCIE5_CTX_C_GRX_N2 BT34 PEX_RX2
<13> PCIE5_CTX_C_GRX_N2
PCIE5_CRX_C_GTX_P3 BJ34 PEX_TX3
+1.8VSDGPU_AON
<13> PCIE5_CRX_C_GTX_P3
PCIE5_CRX_C_GTX_N3 BK34 PEX_TX3
<13> PCIE5_CRX_C_GTX_N3
PCIE5_CTX_C_GRX_P3 BP35 PEX_RX3
<13> PCIE5_CTX_C_GRX_P3 PCIE5_CTX_C_GRX_N3 BR35 PEX_RX3
<13> PCIE5_CTX_C_GRX_N3
PCIE5_CRX_C_GTX_P4 BL35 PEX_TX4
<13> PCIE5_CRX_C_GTX_P4
PCIE5_CRX_C_GTX_N4 BM35 PEX_TX4
<13> PCIE5_CRX_C_GTX_N4

VGA@ CV23

VGA@ CV24

VGA@ CV25

VGA@ CV26

VGA@ CV27

VGA@ CV28

VGA@ CV29

VGA@ CV30

VGA@ CV31

VGA@ CV32

VGA@ CV33
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
PCIE5_CTX_C_GRX_P4 BR36 PEX_RX4
<13> PCIE5_CTX_C_GRX_P4 PCIE5_CTX_C_GRX_N4 BT36 PEX_RX4
C <13> PCIE5_CTX_C_GRX_N4 C
PCIE5_CRX_C_GTX_P5 BJ36 2 2 2 2 2 2 2 2 2 2 2
<13> PCIE5_CRX_C_GTX_P5 PEX_TX5
PCIE5_CRX_C_GTX_N5 BK36 PEX_TX5
<13> PCIE5_CRX_C_GTX_N5
PCIE5_CTX_C_GRX_P5 BP37 PEX_RX5 PEX_HVDD BF38
<13> PCIE5_CTX_C_GRX_P5 PCIE5_CTX_C_GRX_N5 BR37 PEX_RX5 PEX_HVDD BF40
<13> PCIE5_CTX_C_GRX_N5
PEX_HVDD BF41
PCIE5_CRX_C_GTX_P6 BL37 PEX_TX6 PEX_HVDD BG38
<13> PCIE5_CRX_C_GTX_P6
PCIE5_CRX_C_GTX_N6 BM37 PEX_TX6 PEX_HVDD BG40 Under GPU
<13> PCIE5_CRX_C_GTX_N6
PEX_HVDD BG41
PCIE5_CTX_C_GRX_P6 BR38 PEX_RX6 PEX_HVDD BG43
<13> PCIE5_CTX_C_GRX_P6 PCIE5_CTX_C_GRX_N6

1 CV37

1 CV38
BT38 PEX_RX6 PEX_HVDD BG44 1U_0402*9(X6S)
<13> PCIE5_CTX_C_GRX_N6 4.7U_0603*2(X6S)

CV34

VGA@ CV2812

CV36

22U_0603_6.3V6M

22U_0603_6.3V6M
PEX_HVDD BH38
PCIE5_CRX_C_GTX_P7

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
<13> PCIE5_CRX_C_GTX_P7 BJ38 PEX_TX7 PEX_HVDD BH40 1 1 1
PCIE5_CRX_C_GTX_N7 BK38 PEX_TX7 PEX_HVDD BH41
<13> PCIE5_CRX_C_GTX_N7
PEX_HVDD BH43
PCIE5_CTX_C_GRX_P7

VGA@

VGA@
BP39 PEX_RX7 PEX_HVDD BH44
<13> PCIE5_CTX_C_GRX_P7

VGA@ 2

VGA@ 2
PCIE5_CTX_C_GRX_N7 BR39 2 2 2
<13> PCIE5_CTX_C_GRX_N7 PEX_RX7

BL39 PEX_TX8
BM39 PEX_TX8
PEX_PLL_HVDD BF43
BR40 PEX_RX8
BT40 PEX_RX8 Near GPU 10U_0805*3
22U_0805*2
BJ40 PEX_TX9
BK40 PEX_TX9
+PEX_PLL_HVDD +1.8VSDGPU_AON
BP41 PEX_RX9
BR41 PEX_RX9 1 @ 2
RV529 0_0402_5%
BL41 PEX_TX10
BM41 PEX_TX10

CV452
B B

1U_0201_6.3V6M
BR42 PEX_RX10 1
BT42 PEX_RX10

VGA@
BJ42 PEX_TX11
BK42 2
PEX_TX11

BP43 PEX_RX11
BR43 PEX_RX11

BL43 PEX_TX12
BM43 PEX_TX12

BR44 PEX_RX12
BT44 PEX_RX12

BJ44 PEX_TX13
BK44 PEX_TX13

BP45 PEX_RX13
BR45 PEX_RX13

BL45 PEX_TX14
BM45 PEX_TX14 PEX_CVDD_SENSE BK46

BR46 PEX_RX14
BT46 PEX_RX14

BL47 PEX_TX15
BM47 PEX_TX15

BP47 PEX_RX15 PEX_TERMP BT50 PEX_TERMP 1 2

BR47 PEX_RX15 VGA@ RV11
2.49K_0402_1%
A A
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 25 of 122
5 4 3 2 1
 5 4 3 2 1
UV1Q
GN20-E7
BGA2714
COMMON

12/24 MISC 1 +1.8VSDGPU_AON +1.8VSDGPU_AON +1.8VSDGPU_AON

VGA_OVERT# BK7 BL8 VGA_I2CS_SCL RV14 1 VGA@ 2 1.8K_0402_1% GPIO4_EN RV21 1 VGA@ 2 10K_0201_5%
OVERT I2CS_SCL To PWR

5
I2CS_SDA BL7 VGA_I2CS_SDA RV15 1 VGA@ 2 1.8K_0402_1% QV13A VGA@ NVVDD_PSI RV22 1 VGA@ 2 10K_0201_5%
PJT138KA 2N SOT363-6 VRAM_VDD_CTL RV516 1 @ 2 10K_0201_5%

G
BG8 TS_VREF 10/23 VGA_I2CC_SCL 4 3 VGA_ALERT# RV518 1 VGA@ 2 10K_0201_5%
VGA_I2CC_SCL check eDP conn side PU <36> VGA_I2CC_SCL VGA_I2CC_SCL_PW R <36,103> ACIN_BUF
BM7 2 VGA@ 1 2.2K_0402_5% 1 2

D
I2CC_SCL RV12 RV514 VGA@ 10K_0201_5%

2
I2CC_SDA BN7 VGA_I2CC_SDA RV13 2 VGA@ 1 2.2K_0402_5% QV13B VGA@ GPIO22_ADC_MUX_SEL RV515 1 VGA@ 2 10K_0201_5%
PJT138KA 2N SOT363-6

G
VGA_I2CC_SDA 1 6 FBVDDQ_PSI RV117 1 VGA@ 2 10K_0201_5%
<36> VGA_I2CC_SDA VGA_I2CC_SDA_PW R <36,103>
BN8 VGA_I2CB_SCL 2 VGA@ 1 4.7K_0402_5% VGA_OVERT# 1 VGA@ 2 10K_0201_5%

D
I2CB_SCL RV16 RV418
I2CB_SDA BM8 VGA_I2CB_SDA RV17 2 VGA@ 1 4.7K_0402_5% FRM_LCK# RV448 1 VGA@ 2 10K_0201_5%
+1.8VSDGPU_AON +1.8VSDGPU_AON
10/30 Intel/AMD naming
BR8 THERMDN
RV16 RV17 change to 4.7K
GC6_FB_EN1V8 RV20 1 VGA@ 2 10K_0201_5%

5
D BP8 QV41A VGA@ QV2A VGA@ NVVDD_PSI RV23 1 @ 2 10K_0201_5% D
THERMDP
10/06 PJT138KA 2N SOT363-6
To eDP conn PJT138KA 2N SOT363-6
To PCH/ EC VRAM_VDD_CTL RV517 1 @ 2 10K_0201_5%

G
Add GPIO3 for eDP SW VGA_I2CB_SCL 4 3 VGA_I2CS_SCL 4 3 VRAM_VREF_CTL RV519 1 VGA@ 2 100K_0201_5%
Add GPIO7 for PWM VGA_I2CB_SCL_Q <38> EC_SMB_CK1 <58,66>

D
2

2
BP2 NVVDD_VID Add GPIO11 for ENVDD QV41B VGA@ QV2B VGA@
GPIO0 NVVDD_VID <103> Add GPIO13 for EDP_BL_EN
BN3 GC6_FB_EN1V8 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6 FBVDDQ_PSI RV530 1 @ 2 10K_0201_5%

G
GPIO1 Add GPIO16 for PWM SW
BN2 VGA_I2CB_SDA 1 6 VGA_I2CS_SDA 1 6
GPIO2 Add GPIO17 for eDP HPD VGA_I2CB_SDA_Q <38> EC_SMB_DA1 <58,66>
BP10 BM4 DGPU_EDP_SW

D
<36> ADC_IN_P ADC_IN GPIO3 Add GPIO21 for ENBKL
BR10 ADC_IN GPIO4 BM3 GPIO4_EN NVVDD/MSVDD merged change GPIO14(DP HPD) to DPIP0_HPD
<36> ADC_IN_N FRM_LCK# Add GPIO18 for DPIP2_HPD DGPU_EDP_SW
GPIO5 BM2 RV673 1 VGA@ 2 10K_0201_5%
GPIO6 BM1 NVVDD_PSI DGPU_INV_PW M RV674 1 VGA@ 2 100K_0201_5%
DGPU_INV_PW M NVVDD_PSI <103> DGPU_ENVDD
GPIO7 BL1 RV675 1 VGA@ 2 10K_0201_5%
GPIO8 BK6 VRAM_VDD_CTL DGPU_PW M_SW RV676 1 VGA@ 2 10K_0201_5%
VGA_ALERT# VRAM_VDD_CTL <108> DGPU_ENBKL
GPIO9 BK5 RV678 1 VGA@ 2 100K_0201_5%
GPIO10 BK4 VRAM_VREF_CTL
JTAG_TCK DGPU_ENVDD DV6
@ T67 PAD~D 1 BP25 JTAG_TCK GPIO11 BK3
@ T66 PAD~D 1JTAG_TMS BN25 JTAG_TMS GPIO12 BK2 ACIN_BUF 2 1
JTAG_TDI IGPU_BL_EN DGPU_AC_DETECT <58,85>
@ T64 PAD~D 1 BT25 JTAG_TDI GPIO13 BK1 VGA@ 10/06
@ T65 PAD~D 1JTAG_TDO BR25 JTAG_TDO GPIO14 BJ6 Level shift for BL(iGPU to dGPU) 10/06
1 2JTAG_TRST# BM25 BJ5 RB751S40T1G_SOD523-2 Level shift for BL(dGPU to iGPU) +3VS
JTAG_TRST GPIO15
RV10 10K_0201_5% GPIO16 BJ4 DGPU_PW M_SW +1.8VSDGPU_AON
VGA@ GPIO17 BJ3 eDP_HPD_GPU# +3VS
+1.8VSDGPU_AON GPIO18 BJ2

2
BL25 NVJTAG_SEL GPIO19 BJ1 VGA@

2
BH1 VGA@ +3VS RV577
GPIO20
1

2
GPIO21 BG7 DGPU_ENBKL RV571 VGA@ 100K_0201_5%
RV19 GPIO22 BG6 GPIO22_ADC_MUX_SEL 100K_0201_5% RV572
GPIO22_ADC_MUX_SEL <36>
10K_0201_5% GPIO23 BG5 OVRM 100K_0201_5% 3.3V

1
2
@ GPIO24 BG4 1.8V VGA@

1
GPIO25 BG3 FBVDDQ_PSI IGPU_BL_EN RV578 DGPU_ENBKL_Q
FBVDDQ_PSI <108> DGPU_ENBKL_Q <39>
2

1
GPIO26 BG2 ROM_W P# 0_0402_5% 1 @ 2 RV120 ROM_W P#_R 100K_0201_5%
ROM_W P#_R <28>

6
GPIO27 BG1 HDMI_HPD_GPU# VBIOS WP
1

6
BF1 2
D
GPIO28
G
3.3V

1
D
RV18 JTAG_SEL GPIO29 BF2 S 3.3V 2 G

3
10K_0201_5% PD : NO JTAG DONGLE GPIO30 BF3 PJT138KA 2N SOT363-6 1.8V S

3
VGA@ PU : JTAG DONGLE BF4
D
5 3.3V IGPU_ENBKL_R PJT138KA 2N SOT363-6
GPIO31 QV31B G
IGPU_ENBKL_R <39>

1
GPIO32 BF5 VGA@ S DGPU_ENBKL 5 G
D
QV34B
2

GPIO33 BF6 PJT138KA 2N SOT363-6 S VGA@

4
GPIO34 BF7 QV31A PJT138KA 2N SOT363-6

4
GPIO35 BF8 VGA@ QV34A
VGA@
C C
@

10/06 10/06
Level shift for EDP SW Level shift for PWM SW

+3VS +3VS
+3VS
UV51
VGA@

2
0.1U_0201_10V6K 2 1 CV541 1 20 VGA@ VGA@
VDD 1V8_MAIN_EN +3VS RV574 +3VS RV575
100K_0201_5% 100K_0201_5%
GPIO4_EN 2 19 PLTRST_VGA#_1V8
1V8_MAIN_EN_GPU PEGX_RST# PLTRST_VGA#_1V8 <25>
3.3V 3.3V

1
2

2
(PE_GPIO1) 3 18 PEX_VDD_EN <37,110> VGA@ VGA@
<12> SOC_DGPU_PW R_EN DGPU_PWR_EN PEX_VDD_EN DGPU_EDP_SW _Q DGPU_PW M_SW _Q
RV573 RV576
GC6_FB_EN1V8 GC6_FB_EN1V8_R DGPU_EDP_SW _Q <39> DGPU_PW M_SW _Q <39>
RV415 1 @ 2 0_0402_5% 4 100K_0201_5% 100K_0201_5%
RV414 2 @ 1 10K_0201_5% GC6_FB_EN_GPU 17
FB_VDD_EN FBVDDQ_EN <37,108>

6
5
<110> PEX_VDD_PG

1
GN20E support GC6 PEX_VDD_PG 3.3V 2 G
D
3.3V 2 G
D

6 16 1.8V 1.8V
<12> GC6_FB_EN3V3 3VSDGPU_EN <78>
S S
GC6_FB_EN 3V3_SYS_EN

3
PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6

1
DGPU_EDP_SW DGPU_PW M_SW
D D
<108> FBVDDQ_PG 7 5 G
QV32B 5 G
QV33B
FB_VDD_PG 15 ALL_GPW RGD S VGA@ S VGA@
Rev0.2 add RV692(10K_0201) DGPU_HOLD_RST# PD VGA_OVERT# 8 ALL_GPU_PWR_OK PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6

4
OVERT#_GPU
<12> SOC_DGPU_HOLD_RST# QV32A QV33A
14 VGA@ VGA@
OVERT# GPU_OVERT# <59>
RV692 2 VGA@1 10K_0201_5%
10/19 9 13
rename from PLT_RST# to PLT_RST#_R DGPU_HOLD_RST# 1V8_AON_EN 1V8_AON_EN <37>
12
NVVDD_EN NVVDD1_EN <37,103>
10
<11,42,44,45,51,53,66,68,69,70> PLT_RST_R# PLT_RST#
+1.8VSDGPU_AON
11
GND
RV417 1 VGA@2 10K_0201_5% PLTRST_VGA#_1V8
B SLG4U43858VTR_STQFN20_3X2 B
VGA@
0.1U_0201_10V6K 2 1 CV611
@ SLG4U43589VTR_STQFN20_3X2
0.1U_0201_10V6K 2 1 CV542 VGA_OVERT# SA0000DZ000
@ Update Gen2 PN
0.1U_0201_10V6K 2 1 CV543 GPIO4_EN
2020/08/17
@
Update PN & Value(latest FW)

+1.8VSDGPU_AON +1.8VSDGPU_AON
1

VGA@ VGA@
CV625 RV457
2 1 10K_0201_5%

0.1U_0201_10V6K
2
5

Intel naming HDMI_HPD_GPU#

VCC

1
<6,40> SOC_HDMI_HPD IN B 4 2
D
G
QV5B 10/06
+1.8VSDGPU_AON PLTRST_VGA#_1V8 2 OUT Y PJT138KA 2N SOT363-6 Level shift for PWM
GND

IN A 1 S

PU at PCH side Intel naming @ VGA@ +3VS +3VS

1

CLKREQ_GPU# <11> CV610

VGA@ SA0000BJI00 0.1U_0201_10V6K
3
2

UV31 2

2
RV83 VGA@ NL17SZ08DFT2G_SC70-5 VGA@ VGA@
10K_0201_5% +3VS RV653 +3VS RV579
100K_0201_5% 100K_0201_5%
3
1

ALL_GPW RGD 5 G
D
QV5A 3.3V 3.3V

1
2

2
S
PJT138KA 2N SOT363-6 10/06 VGA@ VGA@
VGA@ Remove DP HPD change to eDP HPD RV654 DGPU_ENVDD_Q RV580 DGPU_INV_PW M_Q
1
4

DGPU_ENVDD_Q <39> DGPU_INV_PW M_Q <39>

@ 100K_0201_5% 100K_0201_5%
CV609

6
0.1U_0201_10V6K +1.8VSDGPU_AON
1

1
5

2 CLKREQ_PCIE#0_R 3.3V 2 G
D
3.3V 2 G
D

CLKREQ_PCIE#0_R <25> +1.8VSDGPU_AON 1.8V 1.8V

G

S S
1

3
4 3 VGA@ PJT138KA 2N SOT363-6 1 PJT138KA 2N SOT363-6

1
DGPU_ENVDD DGPU_INV_PW M
D D
5 5
S

A RV458 G QV39A QV39B G QV30A QV30B A

10/20 VGA@ 10K_0402_5% S VGA@
PJT138KA 2N SOT363-6 S VGA@
PJT138KA 2N SOT363-6
change net name from VGA_CLKREQ#_R to CLKREQ_PCIE#0_R CV626 QV29A VGA@ VGA@
4

4
change net name from VGA_CLKREQ# to CLKREQ_PCIE#0 2 1 PJT138KA 2N SOT363-6
2

VGA@ eDP_HPD_GPU#
0.1U_0201_10V6K
5

3.3V
VCC

GPU_EDP_HPD 1
<39> GPU_EDP_HPD IN B D
4 1.8V 2 G QV29B
PLTRST_VGA#_1V8 2 OUT Y PJT138KA 2N SOT363-6
GND

1 S

1.8V IN A @ VGA@
1

CV4120
0.1U_0201_10V6K Security Classification Compal Secret Data Compal Electronics, Inc.
3

VGA@ UV30 2 2020/08/16 2021/08/06 Title

NL17SZ08DFT2G_SC70-5
Issued Date Deciphered Date
SA0000BJI00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E GPIO / GPK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 26 of 122
5 4 3 2 1
 5 4 3 2 1

MEMORY: GPU Partition A/B

UV1B
GN20-E7 UV1C
BGA2714
GN20-E7
COMMON
BGA2714
COMMON
<32> FBA_D[63..0] 2/24 FBA FBA_CMD[24..0] <32>
<33> FBB_D[63..0] 3/24 FBB FBB_CMD[24..0] <33>
FBA_D0 AC51 Y53 FBA_CMD0
FBA_D0 FBA_CMD0
FBA_D1 AB48 AA56 FBA_CMD1 FBB_D0 D37 B37 FBB_CMD0
FBA_D1 FBA_CMD1 FBB_D0 FBB_CMD0
FBA_D2 AC52 AB55 FBA_CMD2 FBB_D1 J37 A37 FBB_CMD1
FBA_D2 FBA_CMD2 FBB_D1 FBB_CMD1
FBA_D3 AC49 AB56 FBA_CMD3 FBB_D2 G37 A38 FBB_CMD2
FBA_D3 FBA_CMD3 FBB_D2 FBB_CMD2
FBA_D4 AF52 AC56 FBA_CMD4 FBB_D3 F37 D38 FBB_CMD3
FBA_D4 FBA_CMD4 FBB_D3 FBB_CMD3
FBA_D5 AC54 AC53 FBA_CMD5 FBB_D4 H38 A39 FBB_CMD4
FBA_D5 FBA_CMD5 FBB_D4 FBB_CMD4
FBA_D6 AE51 AD56 FBA_CMD6 FBB_D5 E38 B40 FBB_CMD5
FBA_D6 FBA_CMD6 FBB_D5 FBB_CMD5
FBA_D7 AF51 AE55 FBA_CMD7 FBB_D6 F40 A40 FBB_CMD6
FBA_D7 FBA_CMD7 FBB_D6 FBB_CMD6
FBA_D8 W51 AE56 FBA_CMD8 FBB_D7 D40 A41 FBB_CMD7
FBA_D8 FBA_CMD8 FBB_D7 FBB_CMD7
FBA_D9 W50 AF56 FBA_CMD9 FBB_D8 F34 D41 FBB_CMD8
FBA_D9 FBA_CMD9 FBB_D8 FBB_CMD8
FBA_D10 W53 AF53 FBA_CMD10 FBB_D9 J34 A42 FBB_CMD9
FBA_D10 FBA_CMD10 FBB_D9 FBB_CMD9
FBA_D11 Y54 AG56 FBA_CMD11 FBB_D10 D34 B43 FBB_CMD10
FBA_D11 FBA_CMD11 FBB_D10 FBB_CMD10
FBA_D12 Y52 AH55 FBA_CMD12 FBB_D11 G34 A43 FBB_CMD11
FBA_D12 FBA_CMD12 FBB_D11 FBB_CMD11
FBA_D13 Y51 AH56 FBA_CMD13 FBB_D12 E35 A44 FBB_CMD12
FBA_D13 FBA_CMD13 FBB_D12 FBB_CMD12
FBA_D14 Y49 AJ56 FBA_CMD14 FBB_D13 K34 D44 FBB_CMD13
FBA_D14 FBA_CMD14 FBB_D13 FBB_CMD13
FBA_D15 AB51 AJ53 FBA_CMD15 FBB_D14 H35 A45 FBB_CMD14
FBA_D15 FBA_CMD15 FBB_D14 FBB_CMD14
D
FBA_D16 AM54 AK56 FBA_CMD16 FBB_D15 K35 B46 FBB_CMD15 D
FBA_D16 FBA_CMD16 FBB_D15 FBB_CMD15
FBA_D17 AL51 AL55 FBA_CMD17 FBB_D16 G47 A46 FBB_CMD16
FBA_D17 FBA_CMD17 FBB_D16 FBB_CMD16
FBA_D18 AM52 AL56 FBA_CMD18 FBB_D17 E44 A47 FBB_CMD17
FBA_D18 FBA_CMD18 FBB_D17 FBB_CMD17
FBA_D19 AJ54 AM56 FBA_CMD19 FBB_D18 F46 D47 FBB_CMD18
FBA_D19 FBA_CMD19 FBB_D18 FBB_CMD18
FBA_D20 AM47 AM53 FBA_CMD20 FBB_D19 F44 A48 FBB_CMD19
FBA_D20 FBA_CMD20 FBB_D19 FBB_CMD19
FBA_D21 AM51 AN56 FBA_CMD21 FBB_D20 E46 B49 FBB_CMD20
FBA_D21 FBA_CMD21 FBB_D20 FBB_CMD20
FBA_D22 AP50 AP55 FBA_CMD22 FBB_D21 C47 A49 FBB_CMD21
FBA_D22 FBA_CMD22 FBB_D21 FBB_CMD21
FBA_D23 AM49 AP56 FBA_CMD23 FBB_D22 E47 B50 FBB_CMD22
FBA_D23 FBA_CMD23 FBB_D22 FBB_CMD22
FBA_D24 AF54 AR56 FBA_CMD24 FBB_D23 C49 A50 FBB_CMD23
FBA_D24 FBA_CMD24 FBB_D23 FBB_CMD23
FBA_D25 AF49 AR53 FBB_D24 G40 C50 FBB_CMD24
FBA_D25 FBA_CMD25_NC FBB_D24 FBB_CMD24
FBA_D26 AH51 AT56 FBB_D25 C41 A51
FBA_D26 FBA_CMD26_NC FBB_D25 FBB_CMD25_NC
FBA_D27 AF47 AR55 FBB_D26 E41 B52
FBA_D27 FBA_CMD27 FBA_CMD[52..28] <32> FBB_D26 FBB_CMD26_NC
FBA_D28 AJ52 BM56 FBA_CMD28 FBB_D27 F41 C52
FBA_D28 FBA_CMD28 FBB_D27 FBB_CMD27 FBB_CMD[53..28] <33>
FBA_D29 AJ51 BM55 FBA_CMD29 FBB_D28 F43 Y56 FBB_CMD28
FBA_D29 FBA_CMD29 FBB_D28 FBB_CMD28
FBA_D30 AH48 BL56 FBA_CMD30 FBB_D29 C44 W56 FBB_CMD29
FBA_D30 FBA_CMD30 FBB_D29 FBB_CMD29
FBA_D31 AJ49 BK55 FBA_CMD31 FBB_D30 H41 W55 FBB_CMD30
FBA_D31 FBA_CMD31 FBB_D30 FBB_CMD30
FBA_D32 BA49 BK56 FBA_CMD32 FBB_D31 H44 V56 FBB_CMD31
FBA_D32 FBA_CMD32 FBB_D31 FBB_CMD31
FBA_D33 BD47 BJ56 FBA_CMD33 FBB_D32 L51 U53 FBB_CMD32
FBA_D33 FBA_CMD33 FBB_D32 FBB_CMD32
FBA_D34 BD54 BJ55 FBA_CMD34 FBB_D33 L52 U56 FBB_CMD33
FBA_D34 FBA_CMD34 FBB_D33 FBB_CMD33
FBA_D35 BD52 BH56 FBA_CMD35 FBB_D34 N51 T56 FBB_CMD34
FBA_D35 FBA_CMD35 FBB_D34 FBB_CMD34
FBA_D36 BC51 BG53 FBA_CMD36 FBB_D35 L49 T55 FBB_CMD35
FBA_D36 FBA_CMD36 FBB_D35 FBB_CMD35
FBA_D37 BD51 BG56 FBA_CMD37 FBB_D36 L54 R56 FBB_CMD36
FBA_D37 FBA_CMD37 FBB_D36 FBB_CMD36
FBA_D38 BF51 BF56 FBA_CMD38 FBB_D37 N47 P53 FBB_CMD37
FBA_D38 FBA_CMD38 FBB_D37 FBB_CMD37
FBA_D39 BD49 BF55 FBA_CMD39 FBB_D38 P51 P56 FBB_CMD38
FBA_D39 FBA_CMD39 FBB_D38 FBB_CMD38
FBA_D40 BG52 BE56 FBA_CMD40 FBB_D39 P49 N56 FBB_CMD39
FBA_D40 FBA_CMD40 FBB_D39 FBB_CMD39
FBA_D41 BG51 BD53 FBA_CMD41 FBB_D40 T51 N55 FBB_CMD40
FBA_D41 FBA_CMD41 FBB_D40 FBB_CMD40
FBA_D42 BG54 BD56 FBA_CMD42 FBB_D41 P52 M56 FBB_CMD41
FBA_D42 FBA_CMD42 FBB_D41 FBB_CMD41
FBA_D43 BF49 BC56 FBA_CMD43 FBB_D42 P54 L53 FBB_CMD42
FBA_D43 FBA_CMD43 FBB_D42 FBB_CMD42
FBA_D44 BJ54 BC55 FBA_CMD44 FBB_D43 U47 L56 FBB_CMD43
FBA_D44 FBA_CMD44 FBB_D43 FBB_CMD43
FBA_D45 BG50 BB56 FBA_CMD45 FBB_D44 U51 K56 FBB_CMD44
FBA_D45 FBA_CMD45 FBB_D44 FBB_CMD44
FBA_D46 BJ52 BA53 FBA_CMD46 FBB_D45 U52 K55 FBB_CMD45
FBA_D46 FBA_CMD46 FBB_D45 FBB_CMD45
FBA_D47 BK53 BA56 FBA_CMD47 FBB_D46 U54 J56 FBB_CMD46
FBA_D47 FBA_CMD47 FBB_D46 FBB_CMD46
FBA_D48 AP51 AY56 FBA_CMD48 FBB_D47 U49 H53 FBB_CMD47
FBA_D48 FBA_CMD48 FBB_D47 FBB_CMD47
FBA_D49 AP53 AY55 FBA_CMD49 FBB_D48 D52 H56 FBB_CMD48
FBA_D49 FBA_CMD49 FBB_D48 FBB_CMD48
FBA_D50 AR52 AW56 FBA_CMD50 FBB_D49 C53 G56 FBB_CMD49
FBA_D50 FBA_CMD50 FBB_D49 FBB_CMD49
FBA_D51 AR54 AV53 FBA_CMD51 FBB_D50 C54 G55 FBB_CMD50
FBA_D51 FBA_CMD51 FBB_D50 FBB_CMD50
FBA_D52 AU51 AV56 FBA_CMD52 FBB_D51 C55 E56 FBB_CMD51
FBA_D52 FBA_CMD52 FBB_D51 FBB_CMD51
FBA_D53 AR51 AU56 FBB_D52 D55 B54 FBB_CMD52 Follow NV CRB
FBA_D53 FBA_CMD53_NC FBB_D52 FBB_CMD52
FBA_D54 AV51 AU55 FBB_D53 D54 B53 FBB_CMD53
FBA_D54 FBA_CMD54_NC FBB_D53 FBB_CMD53_NC
FBA_D55 AR49 AV55 FBB_D54 F56 A52
FBA_D55 FBA_CMD55 FBB_D54 FBB_CMD54_NC
FBA_D56 AV49 FBB_D55 F49 E55
FBA_D56 FBB_D55 FBB_CMD55
FBA_D57 AV54 FBB_D56 G53
FBA_D57 FBB_D56
FBA_D58 AY51 FBB_D57 H49
FBA_D58 FBB_D57
FBA_D59 AV52 FBB_D58 H51
FBA_D59 FBB_D58
FBA_D60 AY48 FBB_D59 G51
FBA_D60 FBB_D59
FBA_D61 BA54 FBB_D60 H52
FBA_D61 FBB_D60
FBA_D62 BA52 AP48 FBB_D61 H54
FBA_D62 FBA_CLK0 FBA_CLK0 <32> FBB_D61
FBA_D63 BA51 AP47 FBB_D62 K48 K44
FBA_D63 FBA_CLK0 FBA_CLK0# <32> FBB_D62 FBB_CLK0 FBB_CLK0 <33>
AR48 FBB_D63 K51 J44
FBA_CLK1 FBA_CLK1 <32> FBB_D63 FBB_CLK0 FBB_CLK0# <33>
FBA_CLK1 AR47 FBB_CLK1 J46
<32> FBA_DBI[7..0] FBA_DBI0 AE50 FBA_CLK1# <32> K46 FBB_CLK1 <33>
FBA_DQM0 <33> FBB_DBI[7..0] FBB_CLK1 FBB_CLK1# <33>
FBA_DBI1 AB50 FBB_DBI0 F38
FBA_DQM1 FBB_DQM0
FBA_DBI2 AL50 AE48 FBB_DBI1 F35
FBA_DQM2 FBA_WCK01 FBA_WCK01 <32> FBB_DQM1
FBA_DBI3 AH50 AE47 FBB_DBI2 G46 J40
FBA_DQM3 FBA_WCK01 FBA_WCK01# <32> FBB_DQM2 FBB_WCK01 FBB_WCK01 <33>
FBA_DBI4 BC50 AC48 FBB_DBI3 G43 K40
FBA_DQM4 FBA_WCKB01 FBA_WCKB01 <32> FBB_DQM3 FBB_WCK01 FBB_WCK01# <33>
FBA_DBI5 BF50 AC47 FBB_DBI4 N50 K38
FBA_DQM5 FBA_WCKB01 FBA_WCKB01# <32> FBB_DQM4 FBB_WCKB01 FBB_WCKB01 <33>
FBA_DBI6 AU50 AL48 FBB_DBI5 T50 J38
FBA_DQM6 FBA_WCK23 FBA_WCK23 <32> FBB_DQM5 FBB_WCKB01 FBB_WCKB01# <33>
FBA_DBI7 AY50 AL47 FBB_DBI6 E49 J43
FBA_DQM7 FBA_WCK23 FBA_WCK23# <32> FBB_DQM6 FBB_WCK23 FBB_WCK23 <33>
AJ48 FBB_DBI7 K50 K43
FBA_WCKB23 FBA_WCKB23 <32> FBB_DQM7 FBB_WCK23 FBB_WCK23# <33>
FBA_WCKB23 AJ47 FBB_WCKB23 K41
<32> FBA_EDC[7..0] FBA_EDC0 AE53 BA47 FBA_WCKB23# <32> J41 FBB_WCKB23 <33>
FBA_DQS_WP0 FBA_WCK45 FBA_WCK45 <32> <33> FBB_EDC[7..0] FBB_WCKB23 FBB_WCKB23# <33>
FBA_EDC1 AB53 BA48 FBB_EDC0 C38 P47
FBA_DQS_WP1 FBA_WCK45 FBA_WCK45# <32> FBB_DQS_WP0 FBB_WCK45 FBB_WCK45 <33>
FBA_EDC2 AL53 BC48 FBB_EDC1 C35 P48
C
FBA_DQS_WP2 FBA_WCKB45 FBA_WCKB45 <32> FBB_DQS_WP1 FBB_WCK45 FBB_WCK45# <33> C
FBA_EDC3 AH53 BC47 FBB_EDC2 D46 T48
FBA_DQS_WP3 FBA_WCKB45 FBA_WCKB45# <32> FBB_DQS_WP2 FBB_WCKB45 FBB_WCKB45 <33>
FBA_EDC4 BC53 AU48 FBB_EDC3 D43 T47
FBA_DQS_WP4 FBA_WCK67 FBA_WCK67 <32> FBB_DQS_WP3 FBB_WCKB45 FBB_WCKB45# <33>
FBA_EDC5 BF53 AU47 +FBVDDQ FBB_EDC4 N53 K47
FBA_EDC6
FBA_DQS_WP5 FBA_WCK67 FBA_WCK67# <32> CKE_A FBB_EDC5
FBB_DQS_WP4 FBB_WCK67 FBB_WCK67 <33>
AU53 FBA_DQS_WP6 FBA_WCKB67 AV48 T53 FBB_DQS_WP5 FBB_WCK67 J47
FBA_EDC7 FBA_WCKB67 <32> FBB_EDC6 FBB_WCK67# <33> +FBVDDQ
AY53 FBA_DQS_WP7 FBA_WCKB67 AV47 E53 FBB_DQS_WP6 FBB_WCKB67 L47 CKE_A
FBA_WCKB67# <32> FBA_CMD14 FBB_EDC7 FBB_WCKB67 <33>
2 VGA@ 1 K53 FBB_DQS_WP7 FBB_WCKB67 L48
FBB_WCKB67# <33>
RV87 10K_0402_5%
BN37 FBA_CMD44 2 VGA@ 1 FBB_CMD14 2 VGA@ 1
GND
BN38 GND RV88 10K_0402_5% BN44 GND RV97 10K_0402_5%
BN39 BN45 FBB_CMD44 2 VGA@ 1
GND
+FB_PLLVDD +1.8VSDGPU_AON
CKE_B GND
BN4 GND BN46 GND RV95 10K_0402_5%
BN40 FBA_CMD17 2 VGA@ 1 BN47
GND GND
+FB_PLLVDD
CKE_B
BN41 GND RV92 10K_0402_5% BN48 GND
BN42 VGA@ FBA_CMD41 2 VGA@ 1 BN6 FBB_CMD17 2 VGA@ 1
GND GND
BN43 GND FB_PLLVDD AC46 LV2 1 2 RV91 10K_0402_5% BN9 GND RV94 10K_0402_5%
AE11 TAI-TECH HCB1608KF-330T30 BP1 L17 FBB_CMD41 2 VGA@ 1
CV164

CV165

CV166

FB_PLLVDD GND FB_PLLVDD

AP46 RESET RV93 10K_0402_5%

CV167
FB_PLLVDD 1 1 1 SM01000JX00
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1CV179

1U_0201_6.3V6M
SM01000JX00 FBA_CMD3 2 VGA@ 1 RESET
CV178

CV177

22U_0603_6.3V6M

RV89 10K_0402_5%
VGA@

VGA@

VGA@

1 1 3000ma 33ohm@100mhz DCR 0.04

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

2 2 2 FBA_CMD31 2 VGA@ 1 FBB_CMD3 2 VGA@ 1

VGA@
RV90 10K_0402_5% 2 RV96 10K_0402_5%
FBB_CMD31 2 VGA@ 1
VGA@

VGA@

2 2 RV98 10K_0402_5%
@

VGA@

@
MEMORY: GPU Partition C/D
UV1D
GN20-E7 UV1E
BGA2714 GN20-E7
COMMON
BGA2714
COMMON
<34> FBC_D[63..0] 4/24 FBC FBC_CMD[24..0] <34>
<35> FBD_D[63..0] 5/24 FBD FBD_CMD[24..0] <35>
FBC_D0 F7 B5 FBC_CMD0
FBC_D0 FBC_CMD0
FBC_D1 H5 A5 FBC_CMD1 FBD_D0 AR4 AU1 FBD_CMD0
FBC_D1 FBC_CMD1 FBD_D0 FBD_CMD0
FBC_D2 F8 C5 FBC_CMD2 FBD_D1 AP8 AU4 FBD_CMD1
FBC_D2 FBC_CMD2 FBD_D1 FBD_CMD1
FBC_D3 G5 A6 FBC_CMD3 FBD_D2 AP6 AT1 FBD_CMD2
FBC_D3 FBC_CMD3 FBD_D2 FBD_CMD2
FBC_D4 H8 B7 FBC_CMD4 FBD_D3 AR6 AR2 FBD_CMD3
FBC_D4 FBC_CMD4 FBD_D3 FBD_CMD3
FBC_D5 E8 A7 FBC_CMD5 FBD_D4 AM6 AR1 FBD_CMD4
FBC_D5 FBC_CMD5 FBD_D4 FBD_CMD4
FBC_D6 C8 A8 FBC_CMD6 FBD_D5 AP3 AP1 FBD_CMD5
FBC_D6 FBC_CMD6 FBD_D5 FBD_CMD5
FBC_D7 D10 D8 FBC_CMD7 FBD_D6 AP5 AP4 FBD_CMD6
FBC_D7 FBC_CMD7 FBD_D6 FBD_CMD6
FBC_D8 D2 A9 FBC_CMD8 FBD_D7 AM9 AN1 FBD_CMD7
FBC_D8 FBC_CMD8 FBD_D7 FBD_CMD7
FBC_D9 E1 B10 FBC_CMD9 FBD_D8 AU5 AM2 FBD_CMD8
FBC_D9 FBC_CMD9 FBD_D8 FBD_CMD8
FBC_D10 C2 A10 FBC_CMD10 FBD_D9 AV6 AM1 FBD_CMD9
FBC_D10 FBC_CMD10 FBD_D9 FBD_CMD9
FBC_D11 D3 A11 FBC_CMD11 FBD_D10 AV9 AL1 FBD_CMD10
FBC_D11 FBC_CMD11 FBD_D10 FBD_CMD10
FBC_D12 C3 D11 FBC_CMD12 FBD_D11 AU3 AL4 FBD_CMD11
FBC_D12 FBC_CMD12 FBD_D11 FBD_CMD11
FBC_D13 B4 A12 FBC_CMD13 FBD_D12 AU6 AK1 FBD_CMD12
FBC_D13 FBC_CMD13 FBD_D12 FBD_CMD12
FBC_D14 E4 B13 FBC_CMD14 FBD_D13 AU8 AJ2 FBD_CMD13
FBC_D14 FBC_CMD14 FBD_D13 FBD_CMD13
FBC_D15 D5 A13 FBC_CMD15 FBD_D14 AU10 AJ1 FBD_CMD14
FBC_D15 FBC_CMD15 FBD_D14 FBD_CMD14
FBC_D16 F17 A14 FBC_CMD16 FBD_D15 AR7 AH1 FBD_CMD15
FBC_D16 FBC_CMD16 FBD_D15 FBD_CMD15
FBC_D17 E14 D14 FBC_CMD17 FBD_D16 AF6 AH4 FBD_CMD16
FBC_D17 FBC_CMD17 FBD_D16 FBD_CMD16
FBC_D18 C14 A15 FBC_CMD18 FBD_D17 AH5 AG1 FBD_CMD17
FBC_D18 FBC_CMD18 FBD_D17 FBD_CMD17
FBC_D19 H14 B16 FBC_CMD19 FBD_D18 AH3 AF2 FBD_CMD18
FBC_D19 FBC_CMD19 FBD_D18 FBD_CMD18
FBC_D20 E17 A16 FBC_CMD20 FBD_D19 AF9 AF1 FBD_CMD19
FBC_D20 FBC_CMD20 FBD_D19 FBD_CMD19
FBC_D21 F16 A17 FBC_CMD21 FBD_D20 AE6 AE1 FBD_CMD20
FBC_D21 FBC_CMD21 FBD_D20 FBD_CMD20
FBC_D22 C17 D17 FBC_CMD22 FBD_D21 AE8 AE4 FBD_CMD21
FBC_D22 FBC_CMD22 FBD_D21 FBD_CMD21
B
FBC_D23 H17 A18 FBC_CMD23 FBD_D22 AE5 AD1 FBD_CMD22 B
FBC_D23 FBC_CMD23 FBD_D22 FBD_CMD22
FBC_D24 F10 B19 FBC_CMD24 FBD_D23 AE10 AC2 FBD_CMD23
FBC_D24 FBC_CMD24 FBD_D23 FBD_CMD23
FBC_D25 G10 A19 FBD_D24 AL6 AC1 FBD_CMD24
FBC_D25 FBC_CMD25_NC FBD_D24 FBD_CMD24
FBC_D26 C11 A20 FBD_D25 AL3 AB1
FBC_D26 FBC_CMD26_NC FBD_D25 FBD_CMD25_NC
FBC_D27 E11 B20 FBD_D26 AL5 AB4
FBC_D27 FBC_CMD27 FBC_CMD[52..28] <34> FBD_D26 FBD_CMD26_NC
FBC_D28 F11 A36 FBC_CMD28 FBD_D27 AL8 AB2
FBC_D28 FBC_CMD28 FBD_D27 FBD_CMD27 FBD_CMD[52..28] <35>
FBC_D29 F13 D35 FBC_CMD29 FBD_D28 AJ6 G2 FBD_CMD28
FBC_D29 FBC_CMD29 FBD_D28 FBD_CMD28
FBC_D30 F14 A35 FBC_CMD30 FBD_D29 AL10 G1 FBD_CMD29
FBC_D30 FBC_CMD30 FBD_D29 FBD_CMD29
FBC_D31 H11 A34 FBC_CMD31 FBD_D30 AH6 G3 FBD_CMD30
FBC_D31 FBC_CMD31 FBD_D30 FBD_CMD30
FBC_D32 F26 B34 FBC_CMD32 FBD_D31 AH8 H1 FBD_CMD31
FBC_D32 FBC_CMD32 FBD_D31 FBD_CMD31
FBC_D33 E26 A33 FBC_CMD33 FBD_D32 T5 H2 FBD_CMD32
FBC_D33 FBC_CMD33 FBD_D32 FBD_CMD32
FBC_D34 H26 D32 FBC_CMD34 FBD_D33 T6 J1 FBD_CMD33
FBC_D34 FBC_CMD34 FBD_D33 FBD_CMD33
FBC_D35 D28 A32 FBC_CMD35 FBD_D34 P6 K4 FBD_CMD34
FBC_D35 FBC_CMD35 FBD_D34 FBD_CMD34
FBC_D36 C26 A31 FBC_CMD36 FBD_D35 T8 K1 FBD_CMD35
FBC_D36 FBC_CMD36 FBD_D35 FBD_CMD35
FBC_D37 E29 B31 FBC_CMD37 FBD_D36 T3 K2 FBD_CMD36
FBC_D37 FBC_CMD37 FBD_D36 FBD_CMD36
FBC_D38 F28 A30 FBC_CMD38 FBD_D37 N5 L1 FBD_CMD37
FBC_D38 FBC_CMD38 FBD_D37 FBD_CMD37
FBC_D39 G28 D29 FBC_CMD39 FBD_D38 N3 L2 FBD_CMD38
FBC_D39 FBC_CMD39 FBD_D38 FBD_CMD38
FBC_D40 F31 A29 FBC_CMD40 FBD_D39 N6 M1 FBD_CMD39
FBC_D40 FBC_CMD40 FBD_D39 FBD_CMD39
FBC_D41 K29 A28 FBC_CMD41 FBD_D40 L6 N4 FBD_CMD40
FBC_D41 FBC_CMD41 FBD_D40 FBD_CMD40
FBC_D42 H29 B28 FBC_CMD42 FBD_D41 N8 N1 FBD_CMD41
FBC_D42 FBC_CMD42 FBD_D41 FBD_CMD41
FBC_D43 J28 A27 FBC_CMD43 FBD_D42 K6 P1 FBD_CMD42
FBC_D43 FBC_CMD43 FBD_D42 FBD_CMD42
FBC_D44 D31 D26 FBC_CMD44 FBD_D43 L9 P2 FBD_CMD43
FBC_D44 FBC_CMD44 FBD_D43 FBD_CMD43
FBC_D45 G31 A26 FBC_CMD45 FBD_D44 K3 R1 FBD_CMD44
FBC_D45 FBC_CMD45 FBD_D44 FBD_CMD44
FBC_D46 E32 A25 FBC_CMD46 FBD_D45 K5 T4 FBD_CMD45
FBC_D46 FBC_CMD46 FBD_D45 FBD_CMD45
FBC_D47 H31 B25 FBC_CMD47 FBD_D46 J2 T1 FBD_CMD46
FBC_D47 FBC_CMD47 FBD_D46 FBD_CMD46
FBC_D48 F19 A24 FBC_CMD48 FBD_D47 K8 U1 FBD_CMD47
FBC_D48 FBC_CMD48 FBD_D47 FBD_CMD47
FBC_D49 K17 D23 FBC_CMD49 FBD_D48 AC7 U2 FBD_CMD48
FBC_D49 FBC_CMD49 FBD_D48 FBD_CMD48
FBC_D50 C20 A23 FBC_CMD50 FBD_D49 AE3 V1 FBD_CMD49
FBC_D50 FBC_CMD50 FBD_D49 FBD_CMD49
FBC_D51 J19 A22 FBC_CMD51 FBD_D50 AC6 W4 FBD_CMD50
FBC_D51 FBC_CMD51 FBD_D50 FBD_CMD50
FBC_D52 E20 B22 FBC_CMD52 FBD_D51 AC4 W1 FBD_CMD51
FBC_D52 FBC_CMD52 FBD_D51 FBD_CMD51
FBC_D53 F20 A21 FBD_D52 AB3 Y1 FBD_CMD52
FBC_D53 FBC_CMD53_NC FBD_D52 FBD_CMD52
FBC_D54 K20 D20 FBD_D53 AB5 Y2
FBC_D54 FBC_CMD54_NC FBD_D53 FBD_CMD53_NC
FBC_D55 H20 B23 FBD_D54 AB6 AA1
FBC_D55 FBC_CMD55 FBD_D54 FBD_CMD54_NC
FBC_D56 G22 FBD_D55 AB8 W2
FBC_D56 FBD_D55 FBD_CMD55
FBC_D57 F22 FBD_D56 W6
FBC_D57 FBD_D56
FBC_D58 C23 FBD_D57 W8
FBC_D58 FBD_D57
FBC_D59 D22 FBD_D58 W5
FBC_D59 FBD_D58
FBC_D60 E23 FBD_D59 Y6
FBC_D60 FBD_D59
FBC_D61 F23 FBD_D60 W3
FBC_D61 FBD_D60
FBC_D62 F25 K22 FBD_D61 U9
FBC_D62 FBC_CLK0 FBC_CLK0 <34> FBD_D61
FBC_D63 H23 J22 FBD_D62 U6 AC10
FBC_D63 FBC_CLK0 FBC_CLK0# <34> FBD_D62 FBD_CLK0 FBD_CLK0 <35>
K23 FBD_D63 T10 AC9
FBC_CLK1 FBC_CLK1 <34> FBD_D63 FBD_CLK0 FBD_CLK0# <35>
FBC_CLK1 J23 FBD_CLK1 AB10
<34> FBC_DBI[7..0] FBC_DBI0 FBC_CLK1# <34> FBD_CLK1 <35>
G7 FBC_DQM0 FBD_CLK1 AB9
FBC_DBI1 <35> FBD_DBI[7..0] FBD_DBI0 FBD_CLK1# <35>
E3 FBC_DQM1 AM7 FBD_DQM0
FBC_DBI2 G16 K13 FBD_DBI1 AV7
FBC_DQM2 FBC_WCK01 FBC_WCK01 <34> FBD_DQM1
FBC_DBI3 G13 J13 FBD_DBI2 AF7 AP9
FBC_DQM3 FBC_WCK01 FBC_WCK01# <34> FBD_DQM2 FBD_WCK01 FBD_WCK01 <35>
FBC_DBI4 F29 K11 FBD_DBI3 AJ7 AP10
FBC_DQM4 FBC_WCKB01 FBC_WCKB01 <34> FBD_DQM3 FBD_WCK01 FBD_WCK01# <35>
FBC_DBI5 F32 J11 FBD_DBI4 P7 AR9
FBC_DQM5 FBC_WCKB01 FBC_WCKB01# <34> FBD_DQM4 FBD_WCKB01 FBD_WCKB01 <35>
FBC_DBI6 G19 J16 FBD_DBI5 L7 AR10
FBC_DQM6 FBC_WCK23 FBC_WCK23 <34> FBD_DQM5 FBD_WCKB01 FBD_WCKB01# <35>
FBC_DBI7 G25 K16 FBD_DBI6 Y7 AH10
FBC_DQM7 FBC_WCK23 FBC_WCK23# <34> FBD_DQM6 FBD_WCK23 FBD_WCK23 <35>
J14 FBD_DBI7 U7 AH9
FBC_WCKB23 FBC_WCKB23 <34> FBD_DQM7 FBD_WCK23 FBD_WCK23# <35>
FBC_WCKB23 K14 FBD_WCKB23 AJ10
<34> FBC_EDC[7..0] FBC_EDC0 FBC_WCKB23# <34> FBD_WCKB23 <35>
D7 FBC_DQS_WP0 FBC_WCK45 K31 FBD_WCKB23 AJ9
FBC_EDC1 FBC_WCK45 <34> <35> FBD_EDC[7..0] FBD_EDC0 FBD_WCKB23# <35>
B3 FBC_DQS_WP1 FBC_WCK45 J31 AM4 FBD_DQS_WP0 FBD_WCK45 P10
FBC_EDC2 D16 K32 FBC_WCK45# <34> FBD_EDC1 AV4 P9 FBD_WCK45 <35>
FBC_DQS_WP2 FBC_WCKB45 FBC_WCKB45 <34> FBD_DQS_WP1 FBD_WCK45 FBD_WCK45# <35>
FBC_EDC3 D13 J32 FBD_EDC2 AF4 N10
FBC_DQS_WP3 FBC_WCKB45 FBC_WCKB45# <34> FBD_DQS_WP2 FBD_WCKB45 FBD_WCKB45 <35>
FBC_EDC4 C29 K25 FBD_EDC3 AJ4 N9
FBC_DQS_WP4 FBC_WCK67 FBC_WCK67 <34> FBD_DQS_WP3 FBD_WCKB45 FBD_WCKB45# <35>
FBC_EDC5 C32 J25 FBD_EDC4 P4 Y10
FBC_DQS_WP5 FBC_WCK67 FBC_WCK67# <34> FBD_DQS_WP4 FBD_WCK67 FBD_WCK67 <35>
FBC_EDC6 D19 J26 FBD_EDC5 L4 Y9 +FBVDDQ
FBC_EDC7
FBC_DQS_WP6 FBC_WCKB67 FBC_WCKB67 <34> FBD_EDC6
FBD_DQS_WP5 FBD_WCK67 FBD_WCK67# <35> CKE_A
D25 FBC_DQS_WP7 FBC_WCKB67 K26 Y4 FBD_DQS_WP6 FBD_WCKB67 W9
FBC_WCKB67# <34> FBD_EDC7 FBD_WCKB67 <35>
U4 FBD_DQS_WP7 FBD_WCKB67 W10
FBD_WCKB67# <35> FBD_CMD14 2 VGA@ 1
A A
BP32 GND RV527 10K_0402_5%
BP34 +FBVDDQ BP48 FBD_CMD44 2 VGA@ 1
GND CKE_A GND
BP36 GND BR1 GND RV107 10K_0402_5%
BP38 GND BR12 GND CKE_B
BP40 +FB_PLLVDD FBC_CMD14 2 VGA@ 1 BR15 +FB_PLLVDD
GND GND
BP42 RV522 10K_0402_5% BR18 FBD_CMD17 2 VGA@ 1
GND GND
BP44 FBC_CMD44 2 VGA@ 1 BR2 RV525 10K_0402_5%
GND GND
BP46 L35 RV521 10K_0402_5% BR21 FBD_CMD41 2 VGA@ 1
GND FB_PLLVDD GND
CKE_B BR24 GND FB_PLLVDD T46 RV524 10K_0402_5%
CV168

FBC_CMD17 2 VGA@ 1 RESET

CV169

1
1U_0201_6.3V6M

RV100 10K_0402_5% 1
1U_0201_6.3V6M

FBC_CMD41 2 VGA@ 1 FBD_CMD3 2 VGA@ 1

RV99 10K_0402_5% RV526 10K_0402_5%
VGA@

2 FBD_CMD31 2 VGA@ 1
VGA@

2 RV528 10K_0402_5%
RESET
@

FBC_CMD3 2 VGA@ 1
@

RV102 10K_0402_5%
FBC_CMD31 2 VGA@ 1
RV523 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E MEM-A~D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 27 of 122
5 4 3 2 1
 5 4 3 2 1
10/10 10/30
SMB_ALT_DDR +1.8VSDGPU_AON change RV41 to VGA@ and RV42 to @
0:single VGA to support G-Sync Advanced Optimus
1:Duar VGA
DEVID_SEL +1.8VSDGPU_AON
0:original PCIe ID define
1:re-brand Device ID define UV1W

2
100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%
PCIE_CFG GN20-E7
0:normal (full) signal swing BGA2714
1:reduce signal swing COMMON
@ @ @ VGA@ @ GSYNC@

2
VGA_DEVICE RV31 RV33 RV35 RV37 RV39 RV41 14/24 MISC 2
0:3D device @ @ VGA@

1
1:VGA device
RV50 RV52 RV54
STRAP0 BM5 STRAP0 ROM_CS BP7 ROM_CS# 100K_0402_1% 10K_0402_5% 100K_0402_1%
STRAP1 BN5 STRAP1

1
STRAP2 BP4 STRAP2 ROM_SI BR7 ROM_SI
STRAP3 BP3 STRAP3 ROM_SO BT8 ROM_SO
D D
STRAP4 BR3 STRAP4 ROM_SCLK BT7 ROM_SCLK
STRAP5 BR4 STRAP5

2
100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%

100K_0402_1%

2
@ @ @ @ VGA@ NGSYNC@ VGA@ VGA@ @
RV32 RV34 RV36 RV38 RV40 RV42 RV51 RV53 RV55
100K_0402_1% 10K_0402_5% 100K_0402_1%

1
@

The Strap for ROM_SO should be 10K while all others are 100K.- check list
check NV only PD need change to 10K?? - DG
Memory Vendor Manufacture part Die Strap Strap2 Strap1 Strap0 GN20-E8 GN20-E6 GN20-E3 Memory speed +1.8VSDGPU_AON
Density Number Revision
+1.8VSDGPU_AON
8Gb Samsung K4Z80325BC-HC14 C-die 0x0 L L L V V (x6) 14 Gbps

1
8Gb Micron MT61K256M32JE-14:A A-die 0x1 L L H V 14 Gbps 1 VGA@
VGA@ VGA@ CV176
8Gb Hynix H56C8H24AIR-S2C A-die 0x2 L H L V V (x6) 14 Gbps RV62 RV520 0.1U_0201_10V6K
VGA@ 10K_0402_5% 10K_0402_5%
16Gb Samsung K4ZAF325BM-HC16 M-die 0x6 H H L V 16 Gbps RV60 2

2
33_0402_5% UV2 VGA@
C ROM_CS# 1 2 ROM_CS_R# 1 8 RV63 C
16Gb Hynix H56G42AS4DX014 A-die 0x8 L L M 16 Gbps ROM_SO 0_0402_5% 1 @ 2 RV61 ROM_SO_R 2 CS# VCC 7 33_0402_5%
ROM_WP#_R 3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
<26> ROM_WP#_R 4 W P#(IO2) CLK 5 ROM_SI_R 1 2 ROM_SI
GND DI(IO0)

1
20210316
Check if use WP RV61 change from 0 ohm to R-short @ W25Q16JWSSIQ_SO8 RV64
RV119 VGA@ P/N: SA0000DHJ00 33_0402_5%
10K_0402_5% VGA@

DGPU VBIOS ROM 16Mb

2
UV1X
GN20-E7
BGA2714
+1.8VSDGPU_AON +GPU_PLLVDD COMMON

Change to Reserve 13/24 XTAL/PLL

VGA@
LV1 1 2 BG22 SP_PLLVDD
TAI-TECH HCB1608KF-330T30

CV174

1CV175

CV171

CV170
BG25

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M
SM01000JX00 VID_PLLVDD

22U_0603_6.3V6M
1 1
SM01000JX00 1
3000ma 33ohm@100mhz DCR 0.04

@
VGA@
2 2

VGA@

VGA@ 2
2

BF9 GPCADC_AVDD

CV172

CV173
Samsung 8Gb Samsung 16Gb

1U_0201_6.3V6M

1U_0201_6.3V6M
X76VSAM@ X76VSAM@ X76VSAM@ X76VSAM@ X76VSAM@ X76VSAM@ X76VS16G@ X76VS16G@ X76VS16G@ X76VS16G@ X76VS16G@ X76VS16G@ 1 1
B UV3 UV4 UV5 UV6 UV7 UV8 UV3 UV4 UV5 UV6 UV7 UV8 BF25 CORE_PLL_AVDD
+1.8VSDGPU_AON B

VGA@

VGA@
SA0000C6280 SA0000C6280 SA0000C6280 SA0000C6280 SA0000C6280 SA0000C6280 SA0000DYL30 SA0000DYL30 SA0000DYL30 SA0000DYL30 SA0000DYL30 SA0000DYL30

2
2 2
X76VS8G@ X76VS8G@ Strap Pin X76VS16G@ X76VS16G@ Strap Pin @
UV9 UV10 UV9 UV10 RV66
X76VSAM@ X76VSAM@ X76VSAM@ X76VS16G@ X76VS16G@ X76VS16G@ 100K_0402_1%
SA0000C6280 SA0000C6280 RV32 RV34 RV36 SA0000DYL30 SA0000DYL30 RV35 RV32 RV33

1
X76VSAM@ - for 6GB SD034100380 SD034100380 SD034100380 SD034100380 SD034100380 SD034100380
X76VSAM@ + X76VS8G@ - for 6GB 100K +-1% 0402 100K +-1% 0402 100K +-1% 0402 X76VS16G@ - for 16GB 100K +-1% 0402 100K +-1% 0402 100K +-1% 0402

EXT_REFCLK_FL BK8 EXT_REFCLK_FL XTALOUTBUFF BP5 XTALOUTBUFF

10K_0402_5%
Hynix 8Gb Hynix 16Gb BT5 XTALIN XTALOUT BR5

1
10K_0402_5%
X76VHYN@ X76VHYN@ X76VHYN@ X76VHYN@ X76VHYN@ X76VHYN@ X76VH16G@ X76VH16G@ X76VH16G@ X76VH16G@ X76VH16G@ X76VH16G@ RV506 @
UV3 UV4 UV5 UV6 UV7 UV8 UV3 UV4 UV5 UV6 UV7 UV8 @ RV65 RV67
VGA@ 100K_0402_1%
SA0000ENP40 SA0000ENP40 SA0000ENP40 SA0000ENP40 SA0000ENP40 SA0000ENP40 SA0000EPM30 SA0000EPM30 SA0000EPM30 SA0000EPM30 SA0000EPM30 SA0000EPM30

@
2

2
18P_0402_50V8J
X76VH8G@ X76VH8G@ Strap Pin X76VH16G@ X76VH16G@ Strap Pin
UV9 UV10 UV9 UV10 XTALIN RV503 1 @ 2 XTALOUT_R

CV640
X76VHYN@ X76VHYN@ X76VHYN@ X76VH16G@ X76VH16G@ X76VH16G@ X76VH16G@ 10M_0402_5% NV suggest floating

1
SA0000ENP40 SA0000ENP40 RV31 RV34 RV35 SA0000EPM30 SA0000EPM30 RV31 RV32 RV34 RV36 @
VGA@ RV502 VGA@
X76VHYN@ - for 6GB YV1
SD034100380 SD034100380 SD034100380 SD034100380 SD034100380 SD034100380 SD034100380 330_0402_1%
X76VH6G@ + X76VH8G@ - for 8GB 100K +-1% 0402 100K +-1% 0402 100K +-1% 0402 X76VH16G@- for 16GB 100K +-1% 0402 100K +-1% 0402 100K +-1% 0402 100K +-1% 0402 27MHZ_10PF_XRCGB27M000F2P18R0

2
1 3 XTALOUT
1 3
1 NC NC 2
Micron 8Gb
A X76VMIC@ X76VMIC@ X76VMIC@ X76VMIC@ X76VMIC@ X76VMIC@ NV suggest PD 10k CV638 CV639 A
UV3 UV4 UV5 UV6 UV7 UV8 15P_0201_50V8J 2 4 15P_0201_50V8J
2 VGA@ 1
VGA@
SA0000BND80 SA0000BND80 SA0000BND80 SA0000BND80 SA0000BND80 SA0000BND80
X76VM8G@ X76VM8G@ Strap Pin
UV9 UV10
X76VMIC@ X76VMIC@ X76VMIC@
SA0000BND80 SA0000BND80 RV31 RV34 RV36 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title
X76VMIC@ - for 6GB
X76VM8GB@ + X76VMIC@ - for 8GB
SD034100380 SD034100380 SD034100380
100K +-1% 0402 100K +-1% 0402 100K +-1% 0402
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E RON/XTAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 28 of 122
5 4 3 2 1
 5 4 3 2 1

DP to CPU DPIP port(DP in)

UV1R
GN20-E7
BGA2714
COMMON

7/24 IFPAB

DL-DVI DVI/HDMI DP

IFPA_AUX BT10
SDA SDA
SCL SCL IFPA_AUX BT11

IFPA_L3 BR20
D IFPAB_RSET TXC TXC D
RV25 2 VGA@ 1 BH23 IFPAB_RSET IFPA_L3 BP20
TXC TXC
1K_0402_1%
+GPU_PLLVDD IFPA_L2 BP22
TXD0 TXD0
TXD0 TXD0 IFPA_L2 BR22
NV BH22 IFPAB_PLLVDD
suggest
CV116 IFPA_L1 BT22

1U_0201_6.3V6M
TXD1 TXD1
TXD1 TXD1 IFPA_L1 BT23
1

TXD2 TXD2 IFPA_L0 BR23

BP23
VGA@

TXD2 TXD2 IFPA_L0

2

IFPB_AUX BR11
SDA
SCL IFPB_AUX BP11
+PEX_VDD +IFP_IOVDD

IFPB_L3 BL22 UV1V

TXC
RV24 1 @ 2 BF14 IFP_IOVDD IFPB_L3 BM22 GN20-E7
TXC
0_0603_5% BF13 IFP_IOVDD BGA2714
COMMON

BF16 BK22
VGA@ CV104

VGA@ CV101

VGA@ CV102

VGA@ CV103

1 1 1 1 IFP_IOVDD IFPB_L2 6/24 IFPF

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M

TXD3 TXD0
BF17 IFP_IOVDD TXD3 TXD0 IFPB_L2 BJ22

DVI/HDMI DP
2 2 2 2 BK23
TXD4 TXD1 IFPB_L1
TXD4 TXD1 IFPB_L1 BL23
IFPF_AUX BK10
SDA
IFPF_AUX BJ10
SCL
TXD5 TXD2 IFPB_L0 BK25
TXD5 TXD2 IFPB_L0 BJ25
C Near GPU Close GPU IFPF_L3 BP13 C
TXC
IFPAB TXC IFPF_L3 BR13

IFPF_L2 BT13
TXD0
BT14
@

TXD0 IFPF_L2
IFPF BR14
TXD1 IFPF_L1
IFPF_L1 BP14
TXD1

IFPF_L0 BP16
UV1U TXD2
IFPF_L0 BR16
GN20-E7 TXD2
BGA2714 BG19 IFP_IOVDD
COMMON BG20 IFP_IOVDD
10/24 IFPE BG16 IFP_IOVDD
BG17 IFP_IOVDD
DVI/HDMI DP

RV27 2 VGA@ 1 IFPEF_RSET BH17 BJ11

@
IFPEF_RSET SDA IFPE_AUX
1K_0402_1% SCL IFPE_AUX BK11
+IFP_IOVDD
+GPU_PLLVDD
IFPE_L3 BL13
TXC
BH16 IFPEF_PLLVDD IFPE_L3 BM13
TXC
BK13
CV118

IFPE_L2
1U_0201_6.3V6M

TXD0
1 TXD0 IFPE_L2 BJ13
NV

VGA@ CV115

VGA@ CV112

VGA@ CV113

VGA@ CV114
1 1 1 1

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M
suggest TXD1 IFPE_L1 BK14
BL14
VGA@

TXD1 IFPE_L1
2 IFPE
BL16 2 2 2 2
TXD2 IFPE_L0
TXD2 IFPE_L0 BM16

+IFP_IOVDD 10/09
Add eDP Main link and Aux
BG13 IFP_IOVDD
BG14 IFP_IOVDD Near GPU Close GPU
BG23
VGA@ CV111

1 IFP_IOVDD
1U_0201_6.3V6M

B B
@

2 UV1T
GPU_EDP_AUXN RV28 1 2 100K_0402_5%
GN20-E7
BGA2714
COMMON GPU_EDP_AUXP RV29 1 2 100K_0402_5%
9/24 IFPD

Under GPU eDP to Mux DVI/HDMI DP

Close GPU

IFPD_AUX BL11 GPU_EDP_AUXN

SDA
BM11 GPU_EDP_AUXP GPU_EDP_AUXN <39>

HDMI 2.1 UV1S

GN20-E7
SCL IFPD_AUX GPU_EDP_AUXP <39>

BGA2714 IFPD_L3 BT16 GPU_EDP_TXN3

TXC GPU_EDP_TXN3 <39>
COMMON
TXC IFPD_L3 BT17 GPU_EDP_TXP3
GPU_EDP_TXP3 <39>
8/24 IFPC
IFPD_L2 BR17 GPU_EDP_TXN2
TXD0 GPU_EDP_TXN2 <39>
RV26 2 VGA@ 1 IFPCD_RSET BH20 IFPCD_RSET IFPD_L2 BP17 GPU_EDP_TXP2
TXD0 GPU_EDP_TXP2 <39>
1K_0402_1%
+GPU_PLLVDD DVI/HDMI DP IFPD BP19 GPU_EDP_TXN1
TXD1 IFPD_L1 GPU_EDP_TXN1 <39>
TXD1 IFPD_L1 BR19 GPU_EDP_TXP1
GPU_HDMI_CTRL_DAT GPU_EDP_TXP1 <39>
BH19 IFPCD_PLLVDD IFPC_AUX BM10
SDA GPU_HDMI_CTRL_CLK GPU_HDMI_CTRL_DAT <40> GPU_EDP_TXN0
IFPC_AUX BL10 TXD2 IFPD_L0 BT19
GPU_HDMI_CTRL_CLK <40> GPU_EDP_TXN0 <39>
SCL
BT20 GPU_EDP_TXP0
eDP
CV117

IFPD_L0
1U_0201_6.3V6M

TXD2 GPU_EDP_TXP0 <39>

NV +IFP_IOVDD
suggest BK17 GPU_HDMI_CLKN
1 TXC IFPC_L3 GPU_HDMI_CLKN <40>
IFPC_L3 BL17 GPU_HDMI_CLKP BF22 IFP_IOVDD
TXC GPU_HDMI_CLKP <40>
BF23 IFP_IOVDD
BL19 GPU_HDMI_N0
VGA@

VGA@ CV109

VGA@ CV110

IFPC_L2 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

2 TXD0 GPU_HDMI_P0 GPU_HDMI_N0 <40>

TXD0 IFPC_L2 BM19
GPU_HDMI_P0 <40>
@

IFPC BK19 GPU_HDMI_N1

TXD1 IFPC_L1 GPU_HDMI_N1 <40>
BJ19 GPU_HDMI_P1 2 2
TXD1 IFPC_L1 GPU_HDMI_P1 <40>
A IFPC_L0 BK20 GPU_HDMI_N2 A
+IFP_IOVDD TXD2
BL20 GPU_HDMI_P2 GPU_HDMI_N2 <40>
TXD2 IFPC_L0 GPU_HDMI_P2 <40>

BF19 IFP_IOVDD Near GPU Under GPU

BF20 IFP_IOVDD
Rename for HDMI
2020/08/18
VGA@ CV108

VGA@ CV105

VGA@ CV106

VGA@ CV107

1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
4.7U_0402_6.3V6M

2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E DISP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
Near GPU Close GPU MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 29 of 122
5 4 3 2 1
 5 4 3 2 1

UV1F UV1G UV1H UV1I UV1J

GN20-E7 GN20-E7 GN20-E7 GN20-E7 GN20-E7 UV1K
BGA2714 BGA2714 BGA2714 BGA2714 BGA2714
COMMON COMMON COMMON COMMON COMMON GN20-E7
BGA2714
COMMON
15/24 GND_1/5 16/24 GND_2/5 21/24 GND_3/5 24/24 GND_5/5 23/24 GND_4/5
11/24 XVDD
A2 GND GND AE35 AK8 GND GND AR42 B39 GND GND BE6 H7 GND GND R41 BR6 GND GND F30
A3 GND GND AE36 AL13 GND GND AR43 B41 GND GND BE8 H9 GND GND R42 BR9 GND GND F33 CONFIGURABLE
A54 GND GND AE37 AL14 GND GND AR44 B42 GND GND BF52 J10 GND GND R43 BT2 GND GND F36 +NVVDD1 POWER CHANNELS
A55 GND GND AE38 AL15 GND GND AR5 B44 GND GND BF54 J17 GND GND R44 BT3 GND GND F39 (NC on substrate) +NVVDD1
AA10 GND GND AE39 AL16 GND GND AR50 B45 GND GND BG12 J20 GND GND R47 C1 GND GND F4
AA13 GND GND AE40 AL17 GND GND AR8 B47 GND GND BG15 J29 GND GND R49 C10 GND GND F42
AA14 GND GND AE41 AL18 GND GND AT10 B48 GND GND BG18 J35 GND GND R51 C13 GND GND F45
AA15 GND GND AE42 AL19 GND GND AT2 B51 GND GND BG21 J4 GND GND R53 C16 GND GND F47 AY1 XVDD_1 XVDD_88 BT52
AA16 GND GND AE43 AL2 GND GND AT4 B55 GND GND BG24 J49 GND GND R55 C19 GND GND F48 AY2 XVDD_2 XVDD_89 BR52
AA17 GND GND AE44 AL20 GND GND AT47 B56 GND GND BG30 J51 GND GND R6 C22 GND GND F51 AY3 XVDD_3 XVDD_90 BN50
AA18 GND GND AE49 AL21 GND GND AT49 B6 GND GND BG33 J53 GND GND R8 C25 GND GND F53 AY4 XVDD_4 XVDD_91 BM49
AA19 GND GND AE52 AL22 GND GND AT51 B8 GND GND BG36 J55 GND GND T2 C28 GND GND F55 AY5 XVDD_5 XVDD_92 BL48
D D
AA2 GND GND AE54 AL23 GND GND AT53 B9 GND GND BG39 J6 GND GND T49 C31 GND GND F6 AY6 XVDD_6 XVDD_93 BK47
AA20 GND GND AE7 AL24 GND GND AT55 BA14 GND GND BG42 J8 GND GND T52 C34 GND GND F9 AY7 XVDD_7 XVDD_94 BJ46
AA21 GND GND AE9 AL25 GND GND AT6 BA15 GND GND BG49 K12 GND GND T54 C37 GND GND G11 AY8 XVDD_8
AA22 GND GND AF10 AL26 GND GND AT8 BA16 GND GND BG55 K15 GND GND T7 C4 GND GND G14 AY9 XVDD_9
AA23 GND GND AF3 AL27 GND GND AU14 BA17 GND GND BH2 K18 GND GND T9 C40 GND GND G17 AY10 XVDD_10 XVDD_95
BT54
AA24 GND GND AF48 AL28 GND GND AU15 BA18 GND GND BH4 K19 GND GND U10 C43 GND GND G20 AY11 XVDD_11 XVDD_96 BR53
AA25 GND GND AF5 AL29 GND GND AU16 BA19 GND GND BH51 K21 GND GND U13 C46 GND GND G23 XVDD_97 BP52
AA26 GND GND AF50 AL30 GND GND AU17 BA20 GND GND BH53 K24 GND GND U14 C56 GND GND G26 XVDD_98 BN51
AA27 GND GND AF55 AL31 GND GND AU18 BA21 GND GND BH55 K27 GND GND U15 C7 GND GND G29 BA1 XVDD_12 XVDD_99 BM50
AA28 GND GND AF8 AL32 GND GND AU19 BA22 GND GND BH6 K28 GND GND U16 D12 GND GND G32 BA2 XVDD_13 XVDD_100 BL49
AA29 GND GND AG10 AL33 GND GND AU2 BA23 GND GND BH8 K30 GND GND U17 D15 GND GND G35 BA3 XVDD_14 XVDD_101 BJ47
AA30 GND GND AG13 AL34 GND GND AU20 BA24 GND GND BJ12 K33 GND GND U18 D18 GND GND G38 BA4 XVDD_15 XVDD_102 BH46
AA31 GND GND AG14 AL35 GND GND AU21 BA25 GND GND BJ14 K36 GND GND U19 D21 GND GND G4 BA5 XVDD_16 XVDD_103 BG45
AA32 GND GND AG15 AL36 GND GND AU22 BA26 GND GND BJ15 K37 GND GND U20 D24 GND GND G41 BA6 XVDD_17 XVDD_104 BF44
AA33 GND GND AG16 AL37 GND GND AU23 BA27 GND GND BJ17 K39 GND GND U21 D27 GND GND G44 BA7 XVDD_18
AA34 GND GND AG17 AL38 GND GND AU24 BA28 GND GND BJ18 K42 GND GND U22 D30 GND GND G49 BA8 XVDD_19
AA35 GND GND AG18 AL39 GND GND AU25 BA29 GND GND BJ20 K45 GND GND U23 D33 GND GND G52 BA9 XVDD_20 XVDD_105 BT55
AA36 GND GND AG19 AL40 GND GND AU26 BA30 GND GND BJ21 K49 GND GND U24 D36 GND GND G54 BA10 XVDD_21 XVDD_106 BR54
AA37 GND GND AG2 AL41 GND GND AU27 BA31 GND GND BJ23 K52 GND GND U25 D39 GND GND G8 BA11 XVDD_22 XVDD_107 BP53
AA38 GND GND AG20 AL42 GND GND AU28 BA32 GND GND BJ24 K54 GND GND U26 D4 GND GND H10 XVDD_108 BN52
AA39 GND GND AG21 AL43 GND GND AU29 BA33 GND GND BJ31 K7 GND GND U27 D42 GND GND H12 XVDD_109 BL50
AA4 GND GND AG22 AL44 GND GND AU30 BA34 GND GND BJ33 K9 GND GND U28 D45 GND GND H13 BB2 XVDD_23 XVDD_110 BK49
AA40 GND GND AG23 AL49 GND GND AU31 BA35 GND GND BJ35 L10 GND GND U29 D48 GND GND H15 BB4 XVDD_24 XVDD_111 BJ48
AA41 GND GND AG24 AL52 GND GND AU32 BA36 GND GND BJ37 L3 GND GND U3 D49 GND GND H16 BB6 XVDD_25 XVDD_112 BH47
AA42 GND GND AG25 AL54 GND GND AU33 BA37 GND GND BJ39 L5 GND GND U30 D51 GND GND H18 BB8 XVDD_26 XVDD_113 BG46
AA43 GND GND AG26 AL7 GND GND AU34 BA38 GND GND BJ41 L50 GND GND U31 D53 GND GND H19 BB10 XVDD_27
AA44 GND GND AG27 AL9 GND GND AU35 BA39 GND GND BJ43 L55 GND GND U32 D6 GND GND H21
AA47 GND GND AG28 AM10 GND GND AU36 BA40 GND GND BJ45 L8 GND GND U33 D9 GND GND H22 XVDD_114 BR55
AA49 GND GND AG29 AM3 GND GND AU37 BA41 GND GND BJ53 M10 GND GND U34 E10 GND GND H24 BC1 XVDD_28 XVDD_115 BP54
AA51 GND GND AG30 AM48 GND GND AU38 BA42 GND GND BJ9 M2 GND GND U35 E13 GND GND H25 BC2 XVDD_29 XVDD_116 BN53
AA53 GND GND AG31 AM5 GND GND AU39 BA43 GND GND BK31 M4 GND GND U36 E16 GND GND H27 BC3 XVDD_30 XVDD_117 BM52
AA55 GND GND AG32 AM50 GND GND AU40 BA50 GND GND BK33 M47 GND GND U37 E19 GND GND H28 BC4 XVDD_31 XVDD_118 BL51
AA6 GND GND AG33 AM55 GND GND AU41 BA55 GND GND BK35 M49 GND GND U38 E2 GND GND H3 BC5 XVDD_32 XVDD_119 BK50
AA8 GND GND AG34 AM8 GND GND AU42 BB47 GND GND BK37 M51 GND GND U39 E22 GND GND H30 BC6 XVDD_33 XVDD_120 BJ49
AB47 GND GND AG35 AN10 GND GND AU43 BB49 GND GND BK39 M53 GND GND U40 E25 GND GND H32 BC7 XVDD_34 XVDD_121 BG47
AB49 GND GND AG36 AN13 GND GND AU49 BB51 GND GND BK41 M55 GND GND U41 E28 GND GND H33 BC8 XVDD_35 XVDD_122 BF46
AB52 GND GND AG37 AN14 GND GND AU52 BB53 GND GND BK43 M6 GND GND U42 E31 GND GND H34 BC9 XVDD_36
C AB54 GND GND AG38 AN15 GND GND AU54 BB55 GND GND BK45 M8 GND GND U43 E34 GND GND H36 BC10 XVDD_37 C
AB7 GND GND AG39 AN16 GND GND AU7 BC14 GND GND BK54 N14 GND GND U44 E37 GND GND H37 BC11 XVDD_38 XVDD_123 BR56
AC13 GND GND AG4 AN17 GND GND AU9 BC15 GND GND BL12 N16 GND GND U48 E40 GND GND H39 XVDD_124 BP55
AC14 GND GND AG40 AN18 GND GND AV10 BC16 GND GND BL15 N18 GND GND U5 E43 GND GND H4 XVDD_125 BN54
AC15 GND GND AG41 AN19 GND GND AV3 BC17 GND GND BL18 N2 GND GND U50 E5 GND GND H40 BD1 XVDD_39 XVDD_126 BM53
AC16 GND GND AG42 AN2 GND GND AV5 BC18 GND GND BL2 N20 GND GND U55 E52 GND GND H42 BD2 XVDD_40 XVDD_127 BK51
AC17 GND GND AG43 AN20 GND GND AV50 BC19 GND GND BL21 N22 GND GND U8 E7 GND GND H43 BD3 XVDD_41 XVDD_128 BJ50
AC18 GND GND AG44 AN21 GND GND AV8 BC20 GND GND BL24 N24 GND GND V10 F1 GND GND H45 BD4 XVDD_42 XVDD_129 BH49
AC19 GND GND AG47 AN22 GND GND AW10 BC21 GND GND BL30 N26 GND GND V2 F12 GND GND H46 BD5 XVDD_43 XVDD_130 BG48
AC20 GND GND AG49 AN23 GND GND AW14 BC22 GND GND BL32 N28 GND GND V4 F15 GND GND H47 BD6 XVDD_44 XVDD_131 BF47
AC21 GND GND AG51 AN24 GND GND AW15 BC23 GND GND BL34 N29 GND GND V47 F18 GND GND H48 BD7 XVDD_45
AC22 GND GND AG53 AN25 GND GND AW16 BC24 GND GND BL36 N31 GND GND V49 F2 GND GND H50 BD8 XVDD_46
AC23 GND GND AG55 AN26 GND GND AW17 BC25 GND GND BL38 N33 GND GND V51 F21 GND GND H55 BD9 XVDD_47 XVDD_132 BP56
AC24 GND GND AG6 AN27 GND GND AW18 BC26 GND GND BL4 N35 GND GND V53 F24 GND GND H6 BD10 XVDD_48 XVDD_133 BN55
AC25 GND GND AG8 AN28 GND GND AW19 BC27 GND GND BL40 N37 GND GND V55 F27 GND BD11 XVDD_49 XVDD_134 BM54
AC26 GND GND AH2 AN29 GND GND AW2 BC28 GND GND BL42 N39 GND GND V6 XVDD_135 BL53
AC27 GND GND AH47 AN30 GND GND AW20 BC29 GND GND BL44 N41 GND GND V8 +PEX_VDD XVDD_136 BK52
AC28 GND GND AH49 AN31 GND GND AW21 BC30 GND GND BL46 N43 GND GND W13 @ XVDD_137 BJ51
AC29 GND GND AH52 AN32 GND GND AW22 BC31 GND GND BL55 N48 GND GND W14 XVDD_138 BF48
AC3 GND GND AH54 AN33 GND GND AW23 BC32 GND GND BL6 N52 GND GND W15 BT26 XVDD_50 XVDD_139 BE47
AC30 GND GND AH7 AN34 GND GND AW24 BC33 GND GND BL9 N54 GND GND W16 BR26 XVDD_51 XVDD_140 BD46
AC31 GND GND AJ13 AN35 GND GND AW25 BC34 GND GND BM14 N7 GND GND W17 BP26 XVDD_52
AC32 GND GND AJ14 AN36 GND GND AW26 BC35 GND GND BM17 P3 GND GND W18 BN26 XVDD_53
AC33 GND GND AJ15 AN37 GND GND AW27 BC36 GND GND BM20 P5 GND GND W19 BM26 XVDD_54
AC34 GND GND AJ16 AN38 GND GND AW28 BC37 GND GND BM23 P50 GND GND W20 BL26 XVDD_55
AC35 GND GND AJ17 AN39 GND GND AW29 BC38 GND GND BM30 P55 GND GND W21 BK26 XVDD_56
AC36 GND GND AJ18 AN4 GND GND AW30 BC39 GND GND BM32 P8 GND GND W22 BJ26 XVDD_57
AC37 GND GND AJ19 AN40 GND GND AW31 BC40 GND GND BM34 R10 GND GND W23 BH26 XVDD_58
AC38 GND GND AJ20 AN41 GND GND AW32 BC41 GND GND BM36 R13 GND GND W24 BG26 XVDD_59
AC39 GND GND AJ21 AN42 GND GND AW33 BC42 GND GND BM38 R14 GND GND W25 BF26 XVDD_60
AC40 GND GND AJ22 AN43 GND GND AW34 BC43 GND GND BM40 R15 GND GND W26
AC41 GND GND AJ23 AN44 GND GND AW35 BC49 GND GND BM42 R16 GND GND W27
AC42 GND GND AJ24 AN47 GND GND AW36 BC52 GND GND BM44 R17 GND GND W28 BR27 XVDD_61
AC43 GND GND AJ25 AN49 GND GND AW37 BC54 GND GND BM46 R18 GND GND W29 BN27 XVDD_62
AC44 GND GND AJ26 AN51 GND GND AW38 BD15 GND GND BM48 R19 GND GND W30 BL27 XVDD_63
AC5 GND GND AJ27 AN53 GND GND AW39 BD16 GND GND BN10 R2 GND GND W31 BJ27 XVDD_64
AC50 GND GND AJ28 AN55 GND GND AW4 BD19 GND GND BN11 R20 GND GND W32 BG27 XVDD_65
AC55 GND GND AJ29 AN6 GND GND AW40 BD20 GND GND BN12 R21 GND GND W33
B B
AC8 GND GND AJ3 AN8 GND GND AW41 BD23 GND GND BN13 R22 GND GND W34
AD10 GND GND AJ30 AP2 GND GND AW42 BD24 GND GND BN14 R23 GND GND W35 BT28 XVDD_66
AD2 GND GND AJ31 AP49 GND GND AW43 BD27 GND GND BN15 R24 GND GND W36 BR28 XVDD_67
AD4 GND GND AJ32 AP52 GND GND AW47 BD30 GND GND BN16 R25 GND GND W37 BP28 XVDD_68
AD47 GND GND AJ33 AP54 GND GND AW49 BD33 GND GND BN17 R26 GND GND W38 BN28 XVDD_69
AD49 GND GND AJ34 AP7 GND GND AW51 BD34 GND GND BN18 R27 GND GND W39 BM28 XVDD_70
AD51 GND GND AJ35 AR13 GND GND AW53 BD37 GND GND BN19 R28 GND GND W40 BL28 XVDD_71
AD53 GND GND AJ36 AR14 GND GND AW55 BD38 GND GND BN20 R29 GND GND W41 BK28 XVDD_72
AD55 GND GND AJ37 AR15 GND GND AW6 BD41 GND GND BN21 R30 GND GND W42 BJ28 XVDD_73
AD6 GND GND AJ38 AR16 GND GND AW8 BD42 GND GND BN22 R31 GND GND W43 BH28 XVDD_74
AD8 GND GND AJ39 AR17 GND GND AY47 BD48 GND GND BN23 R32 GND GND W44 BG28 XVDD_75
AE13 GND GND AJ40 AR18 GND GND AY49 BD50 GND GND BN24 R33 GND GND W52 BF28 XVDD_76
AE14 GND GND AJ41 AR19 GND GND AY52 BD55 GND GND BN30 R34 GND GND W54
AE15 GND GND AJ42 AR20 GND GND AY54 BE10 GND GND BN31 R35 GND GND W7
AE16 GND GND AJ43 AR21 GND GND B1 BE2 GND GND BN32 R36 GND GND Y3 BT29 XVDD_77
AE17 GND GND AJ44 AR22 GND GND B11 BE4 GND GND BN33 R37 GND GND Y48 BR29 XVDD_78
AE18 GND GND AJ5 AR23 GND GND B12 BE49 GND GND BN34 R38 GND GND Y5 BP29 XVDD_79
AE19 GND GND AJ50 AR24 GND GND B14 BE51 GND GND BN35 R39 GND GND Y50 BN29 XVDD_80
AE2 GND GND AJ55 AR25 GND GND B15 BE53 GND GND BN36 R4 GND GND Y55 BM29 XVDD_81
AE20 GND GND AJ8 AR26 GND GND B17 BE55 GND GND BR30 R40 GND GND Y8 BL29 XVDD_82
AE21 GND GND AK10 AR27 GND GND B18 BK29 XVDD_83
AE22 GND GND AK2 AR28 GND GND B2 BJ29 XVDD_84
AE23 GND GND AK4 AR29 GND GND B21 @ @ BH29 XVDD_85
AE24 GND GND AK47 AR3 GND GND B24 BG29 XVDD_86
AE25 GND GND AK49 AR30 GND GND B26 BF29 XVDD_87
AE26 GND GND AK51 AR31 GND GND B27
AE27 GND GND AK53 AR32 GND GND B29
AE28 GND GND AK55 AR33 GND GND B30
AE29 GND GND AK6 AR34 GND GND B32 @
AE30 GND GND B38 AR35 GND GND B33
AE31 GND GND BH13 AR36 GND GND B35
AE32 GND AR37 GND GND B36
AE33 GND AR38 GND GND AR40
AE34 GND AR39 GND GND AR41

@ @
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 30 of 122
5 4 3 2 1
 5 4 3 2 1

UV1M UV1N UV1P

GN20-E7 GN20-E7
+FBVDDQ GN20-E7
+FBVDDQ
+NVVDD1 BGA2714 +NVVDD1 +NVVDD1 BGA2714 +NVVDD1 BGA2714
COMMON COMMON COMMON
UV1L
+NVVDD1 GN20-E7 17/24 VDD_1/2 18/24 VDD_2/2 19/24 FBVDDQ
BGA2714 +NVVDD1
COMMON AB14 AF29 AK38 AP39 AB11 L19
VDD VDD VDD VDD FBVDDQ FBVDDQ
22/24 VDDMS AB15 VDD VDD AF30 AK39 VDD VDD AP40 AB46 FBVDDQ FBVDDQ L20
AB16 VDD VDD AF31 AK40 VDD VDD AP41 AC11 FBVDDQ FBVDDQ L22
AY27 VDDMS VDDMS AB13 AB17 VDD VDD AF32 AK41 VDD VDD AP42 AE46 FBVDDQ FBVDDQ L23
AY28 VDDMS VDDMS AB44 AB18 VDD VDD AF33 AK42 VDD VDD AP43 AF11 FBVDDQ FBVDDQ L25
AY29 VDDMS VDDMS AD13 AB19 VDD VDD AF34 AK43 VDD VDD P14 AF46 FBVDDQ FBVDDQ L26
AY30 VDDMS VDDMS AD44 AB20 VDD VDD AF35 AM14 VDD VDD P15 AH11 FBVDDQ FBVDDQ L28
AY31 VDDMS VDDMS AF13 AB21 VDD VDD AF36 AM15 VDD VDD P16 AH46 FBVDDQ FBVDDQ L29
AY32 VDDMS VDDMS AF44 AB22 VDD VDD AF37 AM16 VDD VDD P17 AJ11 FBVDDQ FBVDDQ L31
AY33 VDDMS VDDMS AH13 AB23 VDD VDD AF38 AM17 VDD VDD P18 AJ46 FBVDDQ FBVDDQ L32
D AY34 VDDMS VDDMS AH44 AB24 VDD VDD AF39 AM18 VDD VDD P19 AL11 FBVDDQ FBVDDQ L34 D
AY35 VDDMS VDDMS AK13 AB25 VDD VDD AF40 AM19 VDD VDD P20 AL46 FBVDDQ FBVDDQ L37
AY36 VDDMS VDDMS AK44 AB26 VDD VDD AF41 AM20 VDD VDD P21 AM11 FBVDDQ FBVDDQ L38
AY37 VDDMS VDDMS AM13 AB27 VDD VDD AF42 AM21 VDD VDD P22 AM46 FBVDDQ FBVDDQ L40
AY38 VDDMS VDDMS AM44 AB28 VDD VDD AF43 AM22 VDD VDD P23 AP11 FBVDDQ FBVDDQ L41
AY39 VDDMS VDDMS AP13 AB29 VDD VDD AH14 AM23 VDD VDD P24 AR11 FBVDDQ FBVDDQ L43
AY40 VDDMS VDDMS AP44 AB30 VDD VDD AH15 AM24 VDD VDD P25 AR46 FBVDDQ FBVDDQ L44
AY41 VDDMS VDDMS AT13 AB31 VDD VDD AH16 AM25 VDD VDD P26 AU11 FBVDDQ FBVDDQ L46
AY42 VDDMS VDDMS AT14 AB32 VDD VDD AH17 AM26 VDD VDD P27 AU46 FBVDDQ FBVDDQ N11
AY43 VDDMS VDDMS AT15 AB33 VDD VDD AH18 AM27 VDD VDD P28 AV11 FBVDDQ FBVDDQ N46
AY44 VDDMS VDDMS AT16 AB34 VDD VDD AH19 AM28 VDD VDD P29 AV46 FBVDDQ FBVDDQ P11
BA13 VDDMS VDDMS AT17 AB35 VDD VDD AH20 AM29 VDD VDD P30 AY46 FBVDDQ FBVDDQ P46
BA44 VDDMS VDDMS AT18 AB36 VDD VDD AH21 AM30 VDD VDD P31 BA46 FBVDDQ FBVDDQ T11
BB13 VDDMS VDDMS AT19 AB37 VDD VDD AH22 AM31 VDD VDD P32 BC46 FBVDDQ FBVDDQ U11
BB14 VDDMS VDDMS AT20 AB38 VDD VDD AH23 AM32 VDD VDD P33 K10 FBVDDQ FBVDDQ U46
BB15 VDDMS VDDMS AT21 AB39 VDD VDD AH24 AM33 VDD VDD P34 L11 FBVDDQ FBVDDQ W11
BB16 VDDMS VDDMS AT22 AB40 VDD VDD AH25 AM34 VDD VDD P35 L13 FBVDDQ FBVDDQ W46
BB17 VDDMS VDDMS AT23 AB41 VDD VDD AH26 AM35 VDD VDD P36 L14 FBVDDQ FBVDDQ Y11
BB18 AT24 AB42 AH27 AM36 P37 L16 Y46 +FBVDDQ
VDDMS VDDMS VDD VDD VDD VDD FBVDDQ FBVDDQ
BB19 VDDMS VDDMS AT25 AB43 VDD VDD AH28 AM37 VDD VDD P38
BB20 VDDMS VDDMS AT26 AD14 VDD VDD AH29 AM38 VDD VDD P39
BB21 VDDMS VDDMS AT27 AD15 VDD VDD AH30 AM39 VDD VDD P40

1
BB22 VDDMS VDDMS AT28 AD16 VDD VDD AH31 AM40 VDD VDD P41
BB23 VDDMS VDDMS AT29 AD17 VDD VDD AH32 AM41 VDD VDD P42 0_0402_5% 0_0402_5% 1 @ 2 RV505
FBVDDQ_GND_SENSE <108>
BB24 VDDMS VDDMS AT30 AD18 VDD VDD AH33 AM42 VDD VDD P43 @ RV209
BB25 VDDMS VDDMS AT31 AD19 VDD VDD AH34 AM43 VDD VDD T14 Place Near GPU
BB26 VDDMS VDDMS AT32 AD20 VDD VDD AH35 AP14 VDD VDD T15

2
BB27 VDDMS VDDMS AT33 AD21 VDD VDD AH36 AP15 VDD VDD T16
BB28 VDDMS VDDMS AT34 AD22 VDD VDD AH37 AP16 VDD VDD T17 FBVDDQ_SENSE E54 FB_VDDQ_SENSE
FB_VDDQ_SENSE <108>
BB29 VDDMS VDDMS AT35 AD23 VDD VDD AH38 AP17 VDD VDD T18
BB30 VDDMS VDDMS AT36 AD24 VDD VDD AH39 AP18 VDD VDD T19
BB31 VDDMS VDDMS AT37 AD25 VDD VDD AH40 AP19 VDD VDD T20
BB32 VDDMS VDDMS AT38 AD26 VDD VDD AH41 AP20 VDD VDD T21 FB_VREF W49 FB_VREF
BB33 VDDMS VDDMS AT39 AD27 VDD VDD AH42 AP21 VDD VDD T22 1

2
BB34 VDDMS VDDMS AT40 AD28 VDD VDD AH43 AP22 VDD VDD T23

3.9P_0402_50V8C
+FBVDDQ

CV627
2.49K_0402_1%
VGA@
BB35 VDDMS VDDMS AT41 AD29 VDD VDD AK14 AP23 VDD VDD T24

CV628
BB36 VDDMS VDDMS AT42 AD30 VDD VDD AK15 AP24 VDD VDD T25 VGA@
BB37 VDDMS VDDMS AT43 AD31 VDD VDD AK16 AP25 VDD VDD T26 2
BB38 VDDMS VDDMS AT44 AD32 VDD VDD AK17 AP26 VDD VDD T27 FB_CAL_PD_VDDQ W47 FBCAL_VDDQ RV461 1 VGA@ 2 40.2_0402_1%

1
BB39 VDDMS VDDMS AU13 AD33 VDD VDD AK18 AP27 VDD VDD T28
BB40 VDDMS VDDMS AU44 AD34 VDD VDD AK19 AP28 VDD VDD Y34 FB_CAL_PU_GND Y47 FBCAL_GND RV459 1 VGA@ 2 40.2_0402_1%
BB41 VDDMS VDDMS AV13 AD35 VDD VDD AK20 AP29 VDD VDD Y35
BB42 VDDMS VDDMS AV14 AD36 VDD VDD AK21 AP30 VDD VDD Y36 FB_CALTERM_GND W48 FBCAL_TERM RV460 1 VGA@ 2 40.2_0402_1%
C BB43 AV15 AD37 AK22 AP31 Y37 C
VDDMS VDDMS VDD VDD VDD VDD
BB44 VDDMS VDDMS AV16 AD38 VDD VDD AK23 AP32 VDD VDD Y38
BC13 AV17 AD39 AK24 AP33 Y39

@
VDDMS VDDMS VDD VDD VDD VDD
BC44 VDDMS VDDMS AV18 AD40 VDD VDD AK25 AP34 VDD VDD Y40
BD13 VDDMS VDDMS AV19 AD41 VDD VDD AK26 AP35 VDD VDD Y41
BD14 VDDMS VDDMS AV20 AD42 VDD VDD AK27 AP36 VDD VDD Y42
BD17 VDDMS VDDMS AV21 AD43 VDD VDD AK28 AP37 VDD VDD Y43
BD18 VDDMS VDDMS AV22 AF14 VDD VDD AK29 AP38 VDD
BD21 VDDMS VDDMS AV23 AF15 VDD VDD AK30
BD22 VDDMS VDDMS AV24 AF16 VDD VDD AK31
BD25 VDDMS VDDMS AV25 AF17 VDD VDD AK32
BD26 AV26 AF18 AK33 BT48 VDD_SENSE RV533 1 VGA@ 2 0_0201_5%
BD28
VDDMS
VDDMS
VDDMS
VDDMS AV27 AF19
VDD
VDD
VDD
VDD AK34
VDD_SENSE
GND_SENSE BR48 GND_SENSE RV532 1 VGA@ 2 0_0201_5%
VCC_SENSE_NVVDD1_MSVDD <103> need check with PWR
VSS_SENSE_NVVDD1_MSVDD <103>
BD29 VDDMS VDDMS AV28 AF20 VDD VDD AK35
BD31 VDDMS VDDMS AV29 AF21 VDD VDD AK36
BD32 AV30 AF22 AK37

@
VDDMS VDDMS VDD VDD
BD35 VDDMS VDDMS AV31 AF23 VDD VDD V29
BD36 VDDMS VDDMS AV32 AF24 VDD VDD V30
BD39 VDDMS VDDMS AV33 AF25 VDD VDD V31
BD40 VDDMS VDDMS AV34 AF26 VDD VDD V32
BD43 VDDMS VDDMS AV35 AF27 VDD VDD V33
BD44 AV36 AF28 V34 +1.8VSDGPU_AON
VDDMS VDDMS VDD VDD UV1O
N13 VDDMS VDDMS AV37 T29 VDD VDD V35 GN20-E7
N15 VDDMS VDDMS AV38 T30 VDD VDD V36 BGA2714
COMMON
N17 VDDMS VDDMS AV39 T31 VDD VDD V37
N19 VDDMS VDDMS AV40 T32 VDD VDD V38 2020/08/12 20/24 NC/1V8
N21 AV41 T33 V39 Del SNN Part

CV605

VGA@ CV606

CV602

VGA@ CV603

VGA@ CV604

VGA@ CV607

VGA@ CV608
VDDMS VDDMS VDD VDD
N23 AV42 T34 V40 AV1 BF10

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
VDDMS VDDMS VDD VDD NC 1V8 1 1 1 1 1 1 1
N25 VDDMS VDDMS AV43 T35 VDD VDD V41 AV2 NC 1V8 BF11
N27 VDDMS VDDMS AV44 T36 VDD VDD V42 BG9 NC 1V8 BG10
N30 AW13 T37 V43 BH10 BG11

VGA@

VGA@
VDDMS VDDMS VDD VDD NC 1V8
N32 AW44 T38 Y14 BH11 2 2 2 2 2 2 2
VDDMS VDDMS VDD VDD NC
N34 VDDMS VDDMS AY13 T39 VDD VDD Y15 BH14 NC
N36 VDDMS VDDMS AY14 T40 VDD VDD Y16 BJ16 NC
N38 VDDMS VDDMS AY15 T41 VDD VDD Y17 BJ7 NC
N40 VDDMS VDDMS AY16 T42 VDD VDD Y18 BJ8 NC RSVD_1 A4
N42 VDDMS VDDMS AY17 T43 VDD VDD Y19 BK16 NC RSVD_2 A53
N44 AY18 V14 Y20 BN49 BN1
P13
VDDMS
VDDMS
VDDMS
VDDMS AY19 V15
VDD
VDD
VDD
VDD Y21 BP50
NC
NC
RSVD_3
RSVD_4 BN56 Under GPU Near GPU
P44 VDDMS VDDMS AY20 V16 VDD VDD Y22 BR50 NC RSVD_5 BT4
T13 VDDMS VDDMS AY21 V17 VDD VDD Y23 BR51 NC RSVD_6 BT53
T44 VDDMS VDDMS AY22 V18 VDD VDD Y24 BT51 NC RSVD_7 D1
B V13 VDDMS VDDMS AY23 V19 VDD VDD Y25 D50 NC RSVD_8 D56 B
V44 VDDMS VDDMS AY24 V20 VDD VDD Y26 E50 NC
Y13 VDDMS VDDMS AY25 V21 VDD VDD Y27 F50 NC
Y44 AY26 V22 Y28 G50 +1.8VSDGPU_AON
VDDMS VDDMS VDD VDD NC
V23 VDD VDD Y29 G6 NC
V24 VDD VDD Y30 N49 NC FUSE_SRC BH25
V25 VDD VDD Y31
V26 VDD VDD Y32
VDDMS_SENSE BP49 V27 VDD VDD Y33 Connect to 1.8VSDGPU_AON
BR49 V28
@

GNDMS_SENSE VDD
@

VDDMS_SENSE 0_0402_5% 1 @ 2 RV508 VCC_SENSE_NVVDD1_MSVDD +FBVDDQ +FBVDDQ

GNDMS_SENSE 0_0402_5% 1 @ 2 RV509 VSS_SENSE_NVVDD1_MSVDD
CV119

VGA@ CV120

VGA@ CV121

VGA@ CV122

VGA@ CV123

VGA@ CV124

VGA@ CV125

VGA@ CV126

VGA@ CV127

VGA@ CV128

VGA@ CV129

VGA@ CV130

CV151

VGA@ CV152

VGA@ CV153

VGA@ CV154

VGA@ CV155
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

need check with PWR

VGA@

VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1CV156

1CV157

1CV158

1CV159

1CV160

1CV161

1CV162

1CV163

1CV641
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
CV131

VGA@ CV132

VGA@ CV133

VGA@ CV134

VGA@ CV135

VGA@ CV136

VGA@ CV137

VGA@ CV138

VGA@ CV139

VGA@ CV140

VGA@ CV141

VGA@ CV142
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1
VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2
VGA@

2 2 2 2 2 2 2 2 2 2 2 2

A A
CV143

VGA@ CV144

VGA@ CV145

VGA@ CV146

VGA@ CV147

VGA@ CV148

VGA@ CV149

VGA@ CV150
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 1
Place Near GPU
22U_0603*9(X6S)
VGA@

2 2 2 2 2 2 2 2 10U_0603*5(X6S)

1U_0402*24(X6S) Security Classification Compal Secret Data Compal Electronics, Inc.

Place Under GPU 10U_0603*8(X6S) 2020/08/16 2021/08/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 31 of 122
5 4 3 2 1
 5 4 3 2 1

Follow NV CRB UV3 MF=1 MF=2

Follow NV CRB UV4 Follow NV CRB
Follow NV CRB
C2 B4
<27> FBA_EDC1 EDC0_A DQ0_A FBA_D9 <27>
C13 A3 C2 B4
<27> FBA_EDC3 EDC1_A DQ1_A FBA_D8 <27> <27> FBA_EDC5 EDC0_A DQ0_A FBA_D41 <27>
T2 B3 C13 A3
<27> FBA_EDC0 EDC0_B DQ2_A FBA_D13 <27> <27> FBA_EDC7 EDC1_A DQ1_A FBA_D40 <27>
T13 B2 T2 B3
<27> FBA_EDC2 EDC1_B DQ3_A FBA_D10 <27> <27> FBA_EDC4 EDC0_B DQ2_A FBA_D42 <27>
E3 T13 B2
DQ4_A FBA_D14 <27> <27> FBA_EDC6 EDC1_B DQ3_A FBA_D44 <27>
E2 E3
DQ5_A FBA_D11 <27> DQ4_A FBA_D47 <27>
D2 F2 E2
<27> FBA_DBI1 DBI0#_A DQ6_A FBA_D15 <27> DQ5_A FBA_D46 <27>
D13 G2 D2 F2
<27> FBA_DBI3 DBI1#_A DQ7_A FBA_D12 <27> <27> FBA_DBI5 DBI0#_A DQ6_A FBA_D43 <27>
R2 B11 D13 G2
<27> FBA_DBI0 DBI0#_B DQ8_A FBA_D24 <27> <27> FBA_DBI7 DBI1#_A DQ7_A FBA_D45 <27>
R13 A12 R2 B11
<27> FBA_DBI2 DBI1#_B DQ9_A FBA_D27 <27> <27> FBA_DBI4 DBI0#_B DQ8_A FBA_D60 <27>
B12 R13 A12
DQ10_A FBA_D25 <27> <27> FBA_DBI6 DBI1#_B DQ9_A FBA_D61 <27>
B13 B12
DQ11_A FBA_D30 <27> DQ10_A FBA_D62 <27>
J10 E12 B13
<27> FBA_CLK0 CK DQ12_A FBA_D26 <27> DQ11_A FBA_D58 <27>
D K10 E13 J10 E12 D
<27> FBA_CLK0# CK# DQ13_A FBA_D31 <27> <27> FBA_CLK1 CK DQ12_A FBA_D63 <27>
G10 F13 K10 E13
<27> FBA_CMD14 CKE#_A DQ14_A FBA_D28 <27> <27> FBA_CLK1# CK# DQ13_A FBA_D59 <27>
M10 G13 G10 F13
<27> FBA_CMD17 CKE#_B DQ15_A FBA_D29 <27> <27> FBA_CMD44 CKE#_A DQ14_A FBA_D57 <27>
M10 G13
<27> FBA_CMD41 CKE#_B DQ15_A FBA_D56 <27>
U4
DQ0_B FBA_D4 <27>
V3 U4
DQ1_B FBA_D2 <27> DQ0_B FBA_D32 <27>
U3 V3
DQ2_B FBA_D6 <27> DQ1_B FBA_D33 <27>
J5 U2 U3
<27> FBA_CMD10 CABI#_A DQ3_B FBA_D5 <27> DQ2_B FBA_D36 <27>
K5 P3 J5 U2
<27> FBA_CMD9 CABI#_B DQ4_B FBA_D7 <27> <27> FBA_CMD37 CABI#_A DQ3_B FBA_D39 <27>
P2 K5 P3
DQ5_B FBA_D0 <27> <27> FBA_CMD38 CABI#_B DQ4_B FBA_D34 <27>
N2 P2
DQ6_B FBA_D3 <27> DQ5_B FBA_D38 <27>
M2 N2
DQ7_B FBA_D1 <27> DQ6_B FBA_D35 <27>
U11 M2
DQ8_B FBA_D17 <27> DQ7_B FBA_D37 <27>
V12 U11
DQ9_B FBA_D21 <27> DQ8_B FBA_D55 <27>
RV463 2 VGA@ 1 121_0402_1% J14 U12 V12
ZQ_A DQ10_B FBA_D16 <27> DQ9_B FBA_D48 <27>
RV462 2 VGA@ 1 121_0402_1% K14 U13 RV465 2 VGA@ 1 121_0402_1% J14 U12
ZQ_B DQ11_B FBA_D18 <27> ZQ_A DQ10_B FBA_D53 <27>
P12 RV464 2 VGA@ 1 121_0402_1% K14 U13
DQ12_B FBA_D19 <27> ZQ_B DQ11_B FBA_D49 <27>
P13 P12
DQ13_B FBA_D20 <27> DQ12_B FBA_D54 <27>
N13 P13
DQ14_B FBA_D22 <27> DQ13_B FBA_D51 <27>
M13 N13
DQ15_B FBA_D23 <27> DQ14_B FBA_D52 <27>
M13
DQ15_B FBA_D50 <27>
2020/08/12 N5 H3 2020/08/12
Del SNN Part TCK CA0_A FBA_CMD1 <27> Del SNN Part
F10 G11 N5 H3
TDI CA1_A FBA_CMD13 <27> TCK CA0_A FBA_CMD33 <27>
N10 G4 F10 G11
TDO CA2_A FBA_CMD12 <27> TDI CA1_A FBA_CMD45 <27>
F5 H12 N10 G4
TMS CA3_A FBA_CMD24 <27> TDO CA2_A FBA_CMD35 <27>
H5 F5 H12
CA4_A FBA_CMD11 <27> TMS CA3_A FBA_CMD46 <27>
H10 H5
CA5_A FBA_CMD15 <27> CA4_A FBA_CMD36 <27>
J12 H10
CA6_A FBA_CMD22 <27> CA5_A FBA_CMD43 <27>
J11 J12
CA7_A FBA_CMD23 <27> CA6_A FBA_CMD48 <27>
J4 J11
CA8_A FBA_CMD0 <27> CA7_A FBA_CMD47 <27>
Follow NV CRB J3 Follow NV CRB J4
CA9_A FBA_CMD2 <27> CA8_A FBA_CMD34 <27>
J3
CA9_A FBA_CMD32 <27>
L3
FBA_WCKB01 CA0_B FBA_CMD5 <27>
D4 M11 L3
<27> FBA_WCKB01 FBA_WCKB01# WCK_A CA1_B FBA_CMD18 <27> FBA_WCKB45 CA0_B FBA_CMD29 <27>
D5 M4 D4 M11
<27> FBA_WCKB01# FBA_WCK23 WCK#_A CA2_B FBA_CMD7 <27> <27> FBA_WCKB45 FBA_WCKB45# WCK_A CA1_B FBA_CMD52 <27>
R11 L12 D5 M4
<27> FBA_WCK23 FBA_WCK23# WCK_B CA3_B FBA_CMD20 <27> <27> FBA_WCKB45# FBA_WCK67 WCK#_A CA2_B FBA_CMD40 <27>
R10 L5 R11 L12
<27> FBA_WCK23# WCK#_B CA4_B FBA_CMD8 <27> <27> FBA_WCK67 FBA_WCK67# WCK_B CA3_B FBA_CMD50 <27>
L10 R10 L5
CA5_B FBA_CMD16 <27> <27> FBA_WCK67# WCK#_B CA4_B FBA_CMD39 <27>
K12 L10
CA6_B FBA_CMD21 <27> CA5_B FBA_CMD42 <27>
K11 K12
CA7_B FBA_CMD19 <27> CA6_B FBA_CMD49 <27>
K4 K11
W=16mils CA8_B K3 FBA_CMD6 <27> CA7_B K4 FBA_CMD51 <27>
+FBAA_VREFC K1
VREFC
CA9_B
+FBVDDQ
FBA_CMD4 <27>
W=16mils
+FBAB_VREFC
CA8_B
CA9_B
K3
FBA_CMD28
FBA_CMD30
<27>
<27>
K1
C1 VREFC +FBVDDQ
J1 VDDQ1 E1 C1
<27> FBA_CMD3 RESET# VDDQ2 VDDQ1
H1 J1 E1
VDDQ3 <27> FBA_CMD31 RESET# VDDQ2
L1 H1
B1 VDDQ4 P1 VDDQ3 L1
C +FBAA_VREFC D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 C
F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1
VSS3 VDDQ7 VSS2 VDDQ6
2

G1 K2 F1 J2
1K_0402_5%

M1 VSS4 VDDQ8 C4 +FBAB_VREFC G1 VSS3 VDDQ7 K2

RV478

VGA@ N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4

VSS6 VDDQ10 VSS5 VDDQ9

2
R1 N4 N1 F4

1K_0402_5%
U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4

RV479
1

A2 VSS8 VDDQ12 B5 VGA@ U1 VSS7 VDDQ11 T4

V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5
C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5

1
D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10
F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10
G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11
M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11
N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11
R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11
T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13
A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13
E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14
H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14
L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14
P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14
V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14
C5 VSS24 VDDQ28 V4 VSS23 VDDQ27 T14
T5 VSS25 C5 VSS24 VDDQ28
C10 VSS26 A1 T5 VSS25
T10 VSS27 VDD1 V1 C10 VSS26 A1
A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1
E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2
H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2
L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5
P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5
V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10
C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10
D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13
F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13
VSS37 VDD11
Follow NV CRB VSS36 VDD10
G12 V14 F12 A14
M12 VSS38 VDD12 +1.8VSDGPU_AON G12 VSS37 VDD11 V14
VSS39 VSS38 VDD12
Follow NV CRB
N12 M12 +1.8VSDGPU_AON
R12 VSS40 A5 N12 VSS39
T12 VSS41 VPP1 V5 R12 VSS40 A5
A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5
V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10
B14 VSS44 VPP4 V13 VSS43 VPP3 V10
D14 VSS45 R4 FBA_WCK01 B14 VSS44 VPP4
VSS46 WCK0_t_B,NC FBA_WCK01# FBA_WCK01 <27> VSS45 FBA_WCK45
F14 R5 D14 R4
VSS47 WCK0_c_B,NC FBA_WCK01# <27> VSS46 WCK0_t_B,NC FBA_WCK45# FBA_WCK45 <27>
G14 F14 R5
VSS48 VSS47 WCK0_c_B,NC FBA_WCK45# <27>
M14 G5 G14
N14 VSS49 RFU_A,NC M5 M14 VSS48 G5
R14 VSS50 RFU_B,NC N14 VSS49 RFU_A,NC M5
B U14 VSS51 180-BALL D10 FBA_WCKB23# R14 VSS50 RFU_B,NC B
VSS52 WCK1_c_A,NC FBA_WCKB23# <27> VSS51
SGRAM GDDR6 D11 FBA_WCKB23 U14 180-BALL D10 FBA_WCKB67#
WCK1_t_A,NC FBA_WCKB23 <27> VSS52 WCK1_c_A,NC FBA_WCKB67# <27>
SGRAM GDDR6 D11 FBA_WCKB67
WCK1_t_A,NC FBA_WCKB67 <27>
K4Z80325BC-HC14_FBGA180~D
SA0000C6280 K4Z80325BC-HC14_FBGA180~D
@ 2020/08/12 SA0000C6280
Del SNN Part @ 2020/08/12
Del SNN Part

+1.8VSDGPU_AON +1.8VSDGPU_AON

+FBVDDQ +FBVDDQ
CV210

CV211

CV212

CV213

CV222

CV223

CV224

CV225
CV180

VGA@ CV181

VGA@ CV182

VGA@ CV183

VGA@ CV184

VGA@ CV185

VGA@ CV186

VGA@ CV187

VGA@ CV188

VGA@ CV189

VGA@ CV190

VGA@ CV191

VGA@ CV192

VGA@ CV193

VGA@ CV194

VGA@ CV195

VGA@ CV196

VGA@ CV197

CV226

VGA@ CV227

VGA@ CV228

VGA@ CV229

VGA@ CV230

VGA@ CV231

VGA@ CV232

VGA@ CV233

VGA@ CV234

VGA@ CV235

VGA@ CV236

VGA@ CV237

VGA@ CV238

VGA@ CV239

VGA@ CV240

VGA@ CV241

VGA@ CV242

VGA@ CV243
1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
2 2 2 2 2 2 2 2
VGA@

VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV198

VGA@ CV199

VGA@ CV200

VGA@ CV201

CV244

VGA@ CV245

VGA@ CV246

VGA@ CV247
1 1 1 1 1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
CLOSE OR UNDER DRAM CLOSE OR UNDER DRAM
VGA@

VGA@
2 2 2 2 2 2 2 2
1U_0402*18 (X6S) 1U_0402*18 (X6S)
10U_0603*4 (X6S) 10U_0603*4 (X6S)

+FBVDDQ +FBVDDQ
+FBVDDQ +FBVDDQ

A A
1CV204

1CV205

1CV206

1CV207

1CV208

1CV209

1CV216

1CV217

1CV218

1CV219

1CV220

1CV221
CV202

VGA@ CV203

CV214

VGA@ CV215

1 1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

+ +
CV612

CV613
VGA@

VGA@
VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2
2 2 2 2 2 2

@
VGA@

BULK DECAPS CLOSE OR UNDER DRAM BULK DECAPS CLOSE OR UNDER DRAM
AROUND DRAM AROUND DRAM

Security Classification Compal Secret Data Compal Electronics, Inc.

2020/08/16 2021/08/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E-GDDR6_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 32 of 122
5 4 3 2 1
 5 4 3 2 1

Follow NV CRB
MF=1 Follow NV CRB UV6 MF=2
UV5 Follow NV CRB
Follow NV CRB
C2 B4
<27> FBB_EDC5 EDC0_A DQ0_A FBB_D42 <27>
C2 B4 C13 A3
<27> FBB_EDC1 EDC0_A DQ0_A FBB_D15 <27> <27> FBB_EDC7 EDC1_A DQ1_A FBB_D41 <27>
C13 A3 T2 B3
<27> FBB_EDC3 EDC1_A DQ1_A FBB_D9 <27> <27> FBB_EDC4 EDC0_B DQ2_A FBB_D40 <27>
T2 B3 T13 B2
<27> FBB_EDC0 EDC0_B DQ2_A FBB_D10 <27> <27> FBB_EDC6 EDC1_B DQ3_A FBB_D45 <27>
T13 B2 E3
<27> FBB_EDC2 EDC1_B DQ3_A FBB_D11 <27> DQ4_A FBB_D46 <27>
E3 E2
DQ4_A FBB_D13 <27> DQ5_A FBB_D44 <27>
E2 D2 F2
DQ5_A FBB_D8 <27> <27> FBB_DBI5 DBI0#_A DQ6_A FBB_D43 <27>
D2 F2 D13 G2
<27> FBB_DBI1 DBI0#_A DQ6_A FBB_D14 <27> <27> FBB_DBI7 DBI1#_A DQ7_A FBB_D47 <27>
D13 G2 R2 B11
<27> FBB_DBI3 DBI1#_A DQ7_A FBB_D12 <27> <27> FBB_DBI4 DBI0#_B DQ8_A FBB_D63 <27>
R2 B11 R13 A12
<27> FBB_DBI0 DBI0#_B DQ8_A FBB_D25 <27> <27> FBB_DBI6 DBI1#_B DQ9_A FBB_D61 <27>
R13 A12 B12
<27> FBB_DBI2 DBI1#_B DQ9_A FBB_D26 <27> DQ10_A FBB_D58 <27>
B12 B13
DQ10_A FBB_D27 <27> DQ11_A FBB_D60 <27>
B13 J10 E12
DQ11_A FBB_D24 <27> <27> FBB_CLK1 CK DQ12_A FBB_D62 <27>
D J10 E12 K10 E13 D
<27> FBB_CLK0 CK DQ12_A FBB_D29 <27> <27> FBB_CLK1# CK# DQ13_A FBB_D56 <27>
K10 E13 G10 F13
<27> FBB_CLK0# CK# DQ13_A FBB_D31 <27> <27> FBB_CMD44 CKE#_A DQ14_A FBB_D57 <27>
G10 F13 M10 G13
<27> FBB_CMD14 CKE#_A DQ14_A FBB_D28 <27> <27> FBB_CMD41 CKE#_B DQ15_A FBB_D59 <27>
M10 G13
<27> FBB_CMD17 CKE#_B DQ15_A FBB_D30 <27>
U4
DQ0_B FBB_D32 <27>
U4 V3
DQ0_B FBB_D1 <27> DQ1_B FBB_D35 <27>
V3 U3
DQ1_B FBB_D7 <27> DQ2_B FBB_D33 <27>
U3 J5 U2
DQ2_B FBB_D6 <27> <27> FBB_CMD37 CABI#_A DQ3_B FBB_D39 <27>
J5 U2 K5 P3
<27> FBB_CMD10 CABI#_A DQ3_B FBB_D5 <27> <27> FBB_CMD38 CABI#_B DQ4_B FBB_D36 <27>
K5 P3 P2
<27> FBB_CMD9 CABI#_B DQ4_B FBB_D4 <27> DQ5_B FBB_D38 <27>
P2 N2
DQ5_B FBB_D0 <27> DQ6_B FBB_D34 <27>
N2 M2
DQ6_B FBB_D3 <27> DQ7_B FBB_D37 <27>
M2 U11
DQ7_B FBB_D2 <27> DQ8_B FBB_D55 <27>
U11 V12
DQ8_B FBB_D18 <27> DQ9_B FBB_D49 <27>
V12 RV468 2 VGA@ 1 121_0402_1% J14 U12
DQ9_B FBB_D21 <27> ZQ_A DQ10_B FBB_D54 <27>
RV466 2 VGA@ 1 121_0402_1% J14 U12 RV469 2 VGA@ 1 121_0402_1% K14 U13
ZQ_A DQ10_B FBB_D20 <27> ZQ_B DQ11_B FBB_D48 <27>
RV467 2 VGA@ 1 121_0402_1% K14 U13 P12
ZQ_B DQ11_B FBB_D22 <27> DQ12_B FBB_D52 <27>
P12 P13
DQ12_B FBB_D19 <27> DQ13_B FBB_D51 <27>
P13 N13
DQ13_B FBB_D23 <27> DQ14_B FBB_D53 <27>
N13 M13
DQ14_B FBB_D17 <27> DQ15_B FBB_D50 <27>
M13
DQ15_B FBB_D16 <27>
N5 H3
TCK CA0_A FBB_CMD33 <27>
N5 H3 2020/08/12 F10 G11
TCK CA0_A FBB_CMD1 <27> Del SNN Part TDI CA1_A FBB_CMD45 <27>
2020/08/12 F10 G11 N10 G4
Del SNN Part TDI CA1_A FBB_CMD13 <27> TDO CA2_A FBB_CMD35 <27>
N10 G4 F5 H12
TDO CA2_A FBB_CMD12 <27> TMS CA3_A FBB_CMD46 <27>
F5 H12 H5
TMS CA3_A FBB_CMD24 <27> CA4_A FBB_CMD36 <27>
H5 H10
CA4_A FBB_CMD11 <27> CA5_A FBB_CMD43 <27>
H10 J12
CA5_A FBB_CMD15 <27> CA6_A FBB_CMD48 <27>
J12 J11
CA6_A FBB_CMD22 <27> CA7_A FBB_CMD47 <27>
J11 J4
CA7_A FBB_CMD23 <27> CA8_A FBB_CMD34 <27>
Follow NV CRB J4 Follow NV CRB J3
CA8_A FBB_CMD0 <27> CA9_A FBB_CMD32 <27>
J3
CA9_A FBB_CMD2 <27>
L3
FBB_WCKB45 CA0_B FBB_CMD29 <27>
L3 D4 M11
FBB_WCKB01 CA0_B FBB_CMD5 <27> <27> FBB_WCKB45 FBB_WCKB45# WCK_A CA1_B FBB_CMD52 <27>
D4 M11 D5 M4
<27> FBB_WCKB01 FBB_WCKB01# WCK_A CA1_B FBB_CMD18 <27> <27> FBB_WCKB45# FBB_WCK67 WCK#_A CA2_B FBB_CMD40 <27>
D5 M4 R11 L12
<27> FBB_WCKB01# FBB_WCK23 WCK#_A CA2_B FBB_CMD7 <27> <27> FBB_WCK67 FBB_WCK67# WCK_B CA3_B FBB_CMD50 <27>
R11 L12 R10 L5
<27> FBB_WCK23 FBB_WCK23# WCK_B CA3_B FBB_CMD20 <27> <27> FBB_WCK67# WCK#_B CA4_B FBB_CMD39 <27>
R10 L5 L10
<27> FBB_WCK23# WCK#_B CA4_B FBB_CMD8 <27> CA5_B FBB_CMD42 <27>
L10 K12
CA5_B FBB_CMD16 <27> CA6_B FBB_CMD49 <27>
K12 K11
CA6_B FBB_CMD21 <27> CA7_B FBB_CMD51 <27>
K11 K4
CA7_B K4 FBB_CMD19 <27>
W=16mils CA8_B K3 FBB_CMD28 <27>
W=16mils
+FBBA_VREFC
CA8_B
CA9_B
K3
FBB_CMD6 <27>
FBB_CMD4 <27>
+FBBB_VREFC K1
VREFC
CA9_B FBB_CMD30
+FBVDDQ
<27>
K1
VREFC +FBVDDQ C1
C1 J1 VDDQ1 E1
VDDQ1 <27> FBB_CMD31 RESET# VDDQ2
J1 E1 H1
<27> FBB_CMD3 RESET# VDDQ2 VDDQ3
H1 L1
VDDQ3 L1 B1 VDDQ4 P1
C B1 VDDQ4 P1 +FBBB_VREFC D1 VSS1 VDDQ5 T1 C
+FBBA_VREFC D1 VSS1 VDDQ5 T1 F1 VSS2 VDDQ6 J2
F1 VSS2 VDDQ6 J2 G1 VSS3 VDDQ7 K2
VSS3 VDDQ7 VSS4 VDDQ8

2
G1 K2 M1 C4

1K_0402_5%
VSS4 VDDQ8 VSS5 VDDQ9
2

M1 C4 N1 F4

RV481
1K_0402_5%

N1 VSS5 VDDQ9 F4 VGA@ R1 VSS6 VDDQ10 N4

RV480

VGA@ R1 VSS6 VDDQ10 N4 U1 VSS7 VDDQ11 T4

U1 VSS7 VDDQ11 T4 A2 VSS8 VDDQ12 B5

1
A2 VSS8 VDDQ12 B5 V2 VSS9 VDDQ13 U5
1

V2 VSS9 VDDQ13 U5 C3 VSS10 VDDQ14 B10

C3 VSS10 VDDQ14 B10 D3 VSS11 VDDQ15 U10
D3 VSS11 VDDQ15 U10 F3 VSS12 VDDQ16 C11
F3 VSS12 VDDQ16 C11 G3 VSS13 VDDQ17 F11
G3 VSS13 VDDQ17 F11 M3 VSS14 VDDQ18 N11
M3 VSS14 VDDQ18 N11 N3 VSS15 VDDQ19 T11
N3 VSS15 VDDQ19 T11 R3 VSS16 VDDQ20 J13
R3 VSS16 VDDQ20 J13 T3 VSS17 VDDQ21 K13
T3 VSS17 VDDQ21 K13 A4 VSS18 VDDQ22 C14
A4 VSS18 VDDQ22 C14 E4 VSS19 VDDQ23 E14
E4 VSS19 VDDQ23 E14 H4 VSS20 VDDQ24 H14
H4 VSS20 VDDQ24 H14 L4 VSS21 VDDQ25 L14
L4 VSS21 VDDQ25 L14 P4 VSS22 VDDQ26 P14
P4 VSS22 VDDQ26 P14 V4 VSS23 VDDQ27 T14
V4 VSS23 VDDQ27 T14 C5 VSS24 VDDQ28
C5 VSS24 VDDQ28 T5 VSS25
T5 VSS25 C10 VSS26 A1
C10 VSS26 A1 T10 VSS27 VDD1 V1
T10 VSS27 VDD1 V1 A11 VSS28 VDD2 H2
A11 VSS28 VDD2 H2 E11 VSS29 VDD3 L2
E11 VSS29 VDD3 L2 H11 VSS30 VDD4 E5
H11 VSS30 VDD4 E5 L11 VSS31 VDD5 P5
L11 VSS31 VDD5 P5 P11 VSS32 VDD6 E10
P11 VSS32 VDD6 E10 V11 VSS33 VDD7 P10
V11 VSS33 VDD7 P10 C12 VSS34 VDD8 H13
C12 VSS34 VDD8 H13 D12 VSS35 VDD9 L13
VSS35 VDD9 VSS36 VDD10
Follow NV CRB
D12 L13 Follow NV CRB F12 A14
F12 VSS36 VDD10 A14 G12 VSS37 VDD11 V14
G12 VSS37 VDD11 V14 M12 VSS38 VDD12 +1.8VSDGPU_AON
M12 VSS38 VDD12 +1.8VSDGPU_AON N12 VSS39
N12 VSS39 R12 VSS40 A5
R12 VSS40 A5 T12 VSS41 VPP1 V5
T12 VSS41 VPP1 V5 A13 VSS42 VPP2 A10
A13 VSS42 VPP2 A10 V13 VSS43 VPP3 V10
V13 VSS43 VPP3 V10 B14 VSS44 VPP4
B14 VSS44 VPP4 D14 VSS45 R4 FBB_WCK45
VSS45 FBB_WCK01 VSS46 WCK0_t_B,NC FBB_WCK45# FBB_WCK45 <27>
D14 R4 F14 R5
VSS46 WCK0_t_B,NC FBB_WCK01# FBB_WCK01 <27> VSS47 WCK0_c_B,NC FBB_WCK45# <27>
F14 R5 G14
G14 VSS47 WCK0_c_B,NC FBB_WCK01# <27> M14 VSS48 G5
M14 VSS48 G5 N14 VSS49 RFU_A,NC M5
N14 VSS49 RFU_A,NC M5 R14 VSS50 RFU_B,NC
B R14 VSS50 RFU_B,NC U14 VSS51 180-BALL D10 FBB_WCKB67# B
VSS51 VSS52 WCK1_c_A,NC FBB_WCKB67# <27>
U14 180-BALL D10 FBB_WCKB23# SGRAM GDDR6 D11 FBB_WCKB67
VSS52 WCK1_c_A,NC WCK1_t_A,NC FBB_WCKB67 <27>
SGRAM GDDR6 D11 FBB_WCKB23 FBB_WCKB23# <27>
WCK1_t_A,NC FBB_WCKB23 <27>
K4Z80325BC-HC14_FBGA180~D
K4Z80325BC-HC14_FBGA180~D SA0000C6280
SA0000C6280 @ 2020/08/12
@ 2020/08/12 Del SNN Part
Del SNN Part

+1.8VSDGPU_AON +1.8VSDGPU_AON
+FBVDDQ
+FBVDDQ
CV256

CV257

CV258

CV259

CV290

CV291

CV292

CV293
CV294

VGA@ CV295

VGA@ CV296

VGA@ CV299

VGA@ CV300

VGA@ CV301

VGA@ CV302

VGA@ CV303

VGA@ CV304

VGA@ CV305

VGA@ CV307
VGA@ CV2821

VGA@ CV2819

VGA@ CV2822

VGA@ CV2823

VGA@ CV2820

VGA@ CV3100

VGA@ CV3111
1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV260

VGA@ CV261

VGA@ CV262

VGA@ CV263

VGA@ CV264

VGA@ CV265

VGA@ CV266

VGA@ CV267

VGA@ CV268

VGA@ CV269

VGA@ CV270

VGA@ CV2804

VGA@ CV2817

VGA@ CV2798

VGA@ CV2799

VGA@ CV2801

VGA@ CV2803

VGA@ CV2806

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
2 2 2 2 2 2 2 2

VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VGA@ CV314

VGA@ CV315
VGA@ CV3122

VGA@ CV3133

VGA@ CV4218

VGA@ CV4219

VGA@ CV4220
VGA@ CV2818

VGA@ CV2800

VGA@ CV2802

VGA@ CV2805

1 1 1 1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CLOSE OR UNDER DRAM

CLOSE OR UNDER DRAM 2 2 2 2 2 2 2
2 2 2 2 1U_0402*18 (X6S)
1U_0402*18 (X6S) 10U_0603*4 (X6S)
10U_0603*4 (X6S)
20210316
reserve 3*0402 CAP

+FBVDDQ
+FBVDDQ +FBVDDQ

+FBVDDQ
1CV288

1CV289
CV2810

CV2811

CV2807

CV2808

A A
1CV250

1CV251

1CV252

1CV253

1CV254

1CV255

CV282

VGA@ CV2809

1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

330U_D2_2V_Y
CV248

VGA@ CV249

1 1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1

CV615
1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

330U_D2_2V_Y

+
VGA@
CV614

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

2 2 2

@
VGA@

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

VGA@ 2

2 2
2
@

BULK DECAPS CLOSE OR UNDER DRAM

AROUND DRAM
AROUND DRAM BULK DECAPS CLOSE OR UNDER DRAM

Security Classification Compal Secret Data Compal Electronics, Inc.

2020/08/16 2021/08/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E-GDDR6_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 33 of 122
5 4 3 2 1
 5 4 3 2 1

Follow NV CRB Follow NV CRB

UV7 MF=1 UV8 MF=2
Follow NV CRB Follow NV CRB
C2 B4 C2 B4
<27> FBC_EDC1 EDC0_A DQ0_A FBC_D9 <27> <27> FBC_EDC5 EDC0_A DQ0_A FBC_D45 <27>
C13 A3 C13 A3
<27> FBC_EDC3 EDC1_A DQ1_A FBC_D8 <27> <27> FBC_EDC7 EDC1_A DQ1_A FBC_D44 <27>
T2 B3 T2 B3
<27> FBC_EDC0 EDC0_B DQ2_A FBC_D15 <27> <27> FBC_EDC4 EDC0_B DQ2_A FBC_D40 <27>
T13 B2 T13 B2
<27> FBC_EDC2 EDC1_B DQ3_A FBC_D10 <27> <27> FBC_EDC6 EDC1_B DQ3_A FBC_D46 <27>
E3 E3
DQ4_A FBC_D13 <27> DQ4_A FBC_D42 <27>
E2 E2
DQ5_A FBC_D12 <27> DQ5_A FBC_D41 <27>
D2 F2 D2 F2
<27> FBC_DBI1 DBI0#_A DQ6_A FBC_D14 <27> <27> FBC_DBI5 DBI0#_A DQ6_A FBC_D43 <27>
D13 G2 D13 G2
<27> FBC_DBI3 DBI1#_A DQ7_A FBC_D11 <27> <27> FBC_DBI7 DBI1#_A DQ7_A FBC_D47 <27>
R2 B11 R2 B11
<27> FBC_DBI0 DBI0#_B DQ8_A FBC_D25 <27> <27> FBC_DBI4 DBI0#_B DQ8_A FBC_D62 <27>
R13 A12 R13 A12
<27> FBC_DBI2 DBI1#_B DQ9_A FBC_D31 <27> <27> FBC_DBI6 DBI1#_B DQ9_A FBC_D60 <27>
B12 B12
DQ10_A FBC_D24 <27> DQ10_A FBC_D61 <27>
B13 B13
DQ11_A FBC_D30 <27> DQ11_A FBC_D58 <27>
J10 E12 J10 E12
<27> FBC_CLK0 CK DQ12_A FBC_D27 <27> <27> FBC_CLK1 CK DQ12_A FBC_D63 <27>
D K10 E13 K10 E13 D
<27> FBC_CLK0# CK# DQ13_A FBC_D29 <27> <27> FBC_CLK1# CK# DQ13_A FBC_D57 <27>
G10 F13 G10 F13
<27> FBC_CMD14 CKE#_A DQ14_A FBC_D26 <27> <27> FBC_CMD44 CKE#_A DQ14_A FBC_D59 <27>
M10 G13 M10 G13
<27> FBC_CMD17 CKE#_B DQ15_A FBC_D28 <27> <27> FBC_CMD41 CKE#_B DQ15_A FBC_D56 <27>
U4 U4
DQ0_B FBC_D5 <27> DQ0_B FBC_D33 <27>
V3 V3
DQ1_B FBC_D6 <27> DQ1_B FBC_D32 <27>
U3 U3
DQ2_B FBC_D2 <27> DQ2_B FBC_D36 <27>
J5 U2 J5 U2
<27> FBC_CMD10 CABI#_A DQ3_B FBC_D0 <27> <27> FBC_CMD37 CABI#_A DQ3_B FBC_D34 <27>
K5 P3 K5 P3
<27> FBC_CMD9 CABI#_B DQ4_B FBC_D4 <27> <27> FBC_CMD38 CABI#_B DQ4_B FBC_D39 <27>
P2 P2
DQ5_B FBC_D7 <27> DQ5_B FBC_D37 <27>
N2 N2
DQ6_B FBC_D3 <27> DQ6_B FBC_D35 <27>
M2 M2
DQ7_B FBC_D1 <27> DQ7_B FBC_D38 <27>
U11 U11
DQ8_B FBC_D19 <27> DQ8_B FBC_D49 <27>
V12 V12
DQ9_B FBC_D18 <27> DQ9_B FBC_D51 <27>
RV470 2 CHC@ 1 121_0402_1% J14 U12 RV472 2 CHC@ 1 121_0402_1% J14 U12
ZQ_A DQ10_B FBC_D17 <27> ZQ_A DQ10_B FBC_D48 <27>
RV471 2 CHC@ 1 121_0402_1% K14 U13 RV473 2 CHC@ 1 121_0402_1% K14 U13
ZQ_B DQ11_B FBC_D21 <27> ZQ_B DQ11_B FBC_D54 <27>
P12 P12
DQ12_B FBC_D22 <27> DQ12_B FBC_D55 <27>
P13 P13
DQ13_B FBC_D20 <27> DQ13_B FBC_D52 <27>
N13 N13
DQ14_B FBC_D16 <27> DQ14_B FBC_D53 <27>
M13 M13
DQ15_B FBC_D23 <27> DQ15_B FBC_D50 <27>

2020/08/12 N5 H3 N5 H3
Del SNN Part TCK CA0_A FBC_CMD1 <27> TCK CA0_A FBC_CMD33 <27>
F10 G11 2020/08/12 F10 G11
TDI CA1_A FBC_CMD13 <27> Del SNN Part TDI CA1_A FBC_CMD45 <27>
N10 G4 N10 G4
TDO CA2_A FBC_CMD12 <27> TDO CA2_A FBC_CMD35 <27>
F5 H12 F5 H12
TMS CA3_A FBC_CMD24 <27> TMS CA3_A FBC_CMD46 <27>
H5 H5
CA4_A FBC_CMD11 <27> CA4_A FBC_CMD36 <27>
H10 H10
CA5_A FBC_CMD15 <27> CA5_A FBC_CMD43 <27>
J12 J12
CA6_A FBC_CMD22 <27> CA6_A FBC_CMD48 <27>
J11 J11
CA7_A FBC_CMD23 <27> CA7_A FBC_CMD47 <27>
Follow NV CRB J4 Follow NV CRB J4
CA8_A FBC_CMD0 <27> CA8_A FBC_CMD34 <27>
J3 J3
CA9_A FBC_CMD2 <27> CA9_A FBC_CMD32 <27>
L3 L3
FBC_WCKB01 CA0_B FBC_CMD5 <27> FBC_WCKB45 CA0_B FBC_CMD29 <27>
D4 M11 D4 M11
<27> FBC_WCKB01 FBC_WCKB01# WCK_A CA1_B FBC_CMD18 <27> <27> FBC_WCKB45 FBC_WCKB45# WCK_A CA1_B FBC_CMD52 <27>
D5 M4 D5 M4
<27> FBC_WCKB01# FBC_WCK23 WCK#_A CA2_B FBC_CMD7 <27> <27> FBC_WCKB45# FBC_WCK67 WCK#_A CA2_B FBC_CMD40 <27>
R11 L12 R11 L12
<27> FBC_WCK23 FBC_WCK23# WCK_B CA3_B FBC_CMD20 <27> <27> FBC_WCK67 FBC_WCK67# WCK_B CA3_B FBC_CMD50 <27>
R10 L5 R10 L5
<27> FBC_WCK23# WCK#_B CA4_B FBC_CMD8 <27> <27> FBC_WCK67# WCK#_B CA4_B FBC_CMD39 <27>
L10 L10
CA5_B FBC_CMD16 <27> CA5_B FBC_CMD42 <27>
K12 K12
CA6_B FBC_CMD21 <27> CA6_B FBC_CMD49 <27>
K11 K11
CA7_B FBC_CMD19 <27> CA7_B FBC_CMD51 <27>
K4 K4
+FBCA_VREFC
W=16mils CA8_B
CA9_B
K3 FBC_CMD6
FBC_CMD4
<27>
<27> +FBCB_VREFC
W=16mils CA8_B
CA9_B
K3 FBC_CMD28
FBC_CMD30
<27>
<27>
K1 K1
VREFC +FBVDDQ VREFC +FBVDDQ
C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
<27> FBC_CMD3 RESET# VDDQ2 <27> FBC_CMD31 RESET# VDDQ2
H1 H1
VDDQ3 L1 VDDQ3 L1
B1 VDDQ4 P1 +FBCB_VREFC B1 VDDQ4 P1
C +FBCA_VREFC D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1 C
F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
VSS3 VDDQ7 VSS3 VDDQ7

2
G1 K2 G1 K2

1K_0402_5%
VSS4 VDDQ8 VSS4 VDDQ8
2

M1 C4 M1 C4

RV483
1K_0402_5%

N1 VSS5 VDDQ9 F4 CHC@ N1 VSS5 VDDQ9 F4

RV482

CHC@ R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4

U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4

1
A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
1

V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5

C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
C5 VSS24 VDDQ28 C5 VSS24 VDDQ28
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
VSS36 VDD10
Follow NV CRB VSS36 VDD10
F12 A14 F12 A14
G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
M12 VSS38 VDD12 +1.8VSDGPU_AON M12 VSS38 VDD12 +1.8VSDGPU_AON
N12 VSS39 N12 VSS39
VSS40 VSS40
Follow NV CRB
R12 A5 R12 A5
T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
B14 VSS44 VPP4 B14 VSS44 VPP4
D14 VSS45 R4 FBC_WCK01 D14 VSS45 R4 FBC_WCK45
VSS46 WCK0_t_B,NC FBC_WCK01# FBC_WCK01 <27> VSS46 WCK0_t_B,NC FBC_WCK45# FBC_WCK45 <27>
F14 R5 F14 R5
VSS47 WCK0_c_B,NC FBC_WCK01# <27> VSS47 WCK0_c_B,NC FBC_WCK45# <27>
G14 G14
M14 VSS48 G5 M14 VSS48 G5
N14 VSS49 RFU_A,NC M5 N14 VSS49 RFU_A,NC M5
R14 VSS50 RFU_B,NC R14 VSS50 RFU_B,NC
B U14 VSS51 180-BALL D10 FBC_WCKB23# U14 VSS51 180-BALL D10 FBC_WCKB67# B
VSS52 WCK1_c_A,NC FBC_WCKB23# <27> VSS52 WCK1_c_A,NC FBC_WCKB67# <27>
SGRAM GDDR6 D11 FBC_WCKB23 SGRAM GDDR6 D11 FBC_WCKB67
WCK1_t_A,NC FBC_WCKB23 <27> WCK1_t_A,NC FBC_WCKB67 <27>

K4Z80325BC-HC14_FBGA180~D K4Z80325BC-HC14_FBGA180~D
SA0000C6280 SA0000C6280
@ @
2020/08/12 2020/08/12
Del SNN Part Del SNN Part

+1.8VSDGPU_AON
+1.8VSDGPU_AON
+FBVDDQ
+FBVDDQ
CV324

CV325

CV326

CV327

CV358

CV359

CV360

CV361
1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV328

CV329

CV330

CV331

CV332

CV333

CV334

CV335

CV336

CV340

CV341

CV342

CV343

CV344

CV345
CHC@ CV3377

CHC@ CV3388

CHC@ CV3399

1 1 1 1

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV362

CV363

CV364

CV365

CV366

CV367

CV368

CV369

CV370

CV371

CV372

CV373

CV374

CV375

CV376

CV377

CV378

CV379
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

CHC@

CHC@

CHC@

CHC@

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
2 2 2 2

CHC@

CHC@

CHC@

CHC@
2 2 2 2
CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@

CHC@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV346

CV347

CV348

CV349

CV380

CV381

CV382

1 1 1 1 CV383
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CLOSE OR UNDER DRAM 10U_0402_6.3V6M

CLOSE OR UNDER DRAM
CHC@

CHC@

CHC@

CHC@

2 2 2 2
CHC@

CHC@

CHC@

CHC@

1U_0402*18 (X6S) 2 2 2 2

10U_0603*4 (X6S) 1U_0402*18 (X6S)

10U_0603*4 (X6S)

+FBVDDQ
+FBVDDQ
+FBVDDQ
A +FBVDDQ A
1

330U_D2_2V_Y
1CV318

1CV319

1CV320

1CV321

1CV322

1CV323

+
CV316

CV317

1CV352

1CV353

1CV354

1CV355

1CV356

1CV357

CV617
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

CV350

CV351

1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
330U_D2_2V_Y

1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

+ 2

@
CV616
CHC@

CHC@

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

2 2
CHC@

CHC@

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

CHC@ 2

2 2 2
@

BULK DECAPS CLOSE OR UNDER DRAM

AROUND DRAM BULK DECAPS CLOSE OR UNDER DRAM

AROUND DRAM
Security Classification Compal Secret Data Compal Electronics, Inc.
2020/08/16 2021/08/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E-GDDR6_C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 34 of 122
5 4 3 2 1
 5 4 3 2 1

Follow NV CRB
UV9 MF=1 Follow NV CRB
MF=2
Follow NV CRB UV10
Follow NV CRB
C2 B4
<27> FBD_EDC1 EDC0_A DQ0_A FBD_D14 <27>
C13 A3 C2 B4
<27> FBD_EDC3 EDC1_A DQ1_A FBD_D10 <27> <27> FBD_EDC5 EDC0_A DQ0_A FBD_D42 <27>
T2 B3 C13 A3
<27> FBD_EDC0 EDC0_B DQ2_A FBD_D15 <27> <27> FBD_EDC7 EDC1_A DQ1_A FBD_D45 <27>
T13 B2 T2 B3
<27> FBD_EDC2 EDC1_B DQ3_A FBD_D9 <27> <27> FBD_EDC4 EDC0_B DQ2_A FBD_D40 <27>
E3 T13 B2
DQ4_A FBD_D13 <27> <27> FBD_EDC6 EDC1_B DQ3_A FBD_D44 <27>
E2 E3
DQ5_A FBD_D8 <27> DQ4_A FBD_D43 <27>
D2 F2 E2
<27> FBD_DBI1 DBI0#_A DQ6_A FBD_D12 <27> DQ5_A FBD_D46 <27>
D13 G2 D2 F2
<27> FBD_DBI3 DBI1#_A DQ7_A FBD_D11 <27> <27> FBD_DBI5 DBI0#_A DQ6_A FBD_D41 <27>
R2 B11 D13 G2
<27> FBD_DBI0 DBI0#_B DQ8_A FBD_D26 <27> <27> FBD_DBI7 DBI1#_A DQ7_A FBD_D47 <27>
R13 A12 R2 B11
<27> FBD_DBI2 DBI1#_B DQ9_A FBD_D25 <27> <27> FBD_DBI4 DBI0#_B DQ8_A FBD_D61 <27>
B12 R13 A12
DQ10_A FBD_D24 <27> <27> FBD_DBI6 DBI1#_B DQ9_A FBD_D56 <27>
B13 B12
DQ11_A FBD_D27 <27> DQ10_A FBD_D62 <27>
J10 E12 B13
<27> FBD_CLK0 CK DQ12_A FBD_D28 <27> DQ11_A FBD_D58 <27>
D K10 E13 J10 E12 D
<27> FBD_CLK0# CK# DQ13_A FBD_D31 <27> <27> FBD_CLK1 CK DQ12_A FBD_D63 <27>
G10 F13 K10 E13
<27> FBD_CMD14 CKE#_A DQ14_A FBD_D30 <27> <27> FBD_CLK1# CK# DQ13_A FBD_D60 <27>
M10 G13 G10 F13
<27> FBD_CMD17 CKE#_B DQ15_A FBD_D29 <27> <27> FBD_CMD44 CKE#_A DQ14_A FBD_D59 <27>
M10 G13
<27> FBD_CMD41 CKE#_B DQ15_A FBD_D57 <27>
U4
DQ0_B FBD_D7 <27>
V3 U4
DQ1_B FBD_D6 <27> DQ0_B FBD_D36 <27>
U3 V3
DQ2_B FBD_D4 <27> DQ1_B FBD_D33 <27>
J5 U2 U3
<27> FBD_CMD10 CABI#_A DQ3_B FBD_D5 <27> DQ2_B FBD_D35 <27>
K5 P3 J5 U2
<27> FBD_CMD9 CABI#_B DQ4_B FBD_D3 <27> <27> FBD_CMD37 CABI#_A DQ3_B FBD_D32 <27>
P2 K5 P3
DQ5_B FBD_D0 <27> <27> FBD_CMD38 CABI#_B DQ4_B FBD_D34 <27>
N2 P2
DQ6_B FBD_D2 <27> DQ5_B FBD_D39 <27>
M2 N2
DQ7_B FBD_D1 <27> DQ6_B FBD_D38 <27>
U11 M2
DQ8_B FBD_D16 <27> DQ7_B FBD_D37 <27>
V12 U11
DQ9_B FBD_D22 <27> DQ8_B FBD_D49 <27>
RV474 2 CHD@ 1 121_0402_1% J14 U12 V12
ZQ_A DQ10_B FBD_D20 <27> DQ9_B FBD_D48 <27>
RV475 2 CHD@ 1 121_0402_1% K14 U13 RV476 2 CHD@ 1 121_0402_1% J14 U12
ZQ_B DQ11_B FBD_D21 <27> ZQ_A DQ10_B FBD_D50 <27>
P12 RV477 2 CHD@ 1 121_0402_1% K14 U13
DQ12_B FBD_D18 <27> ZQ_B DQ11_B FBD_D51 <27>
P13 P12
DQ13_B FBD_D23 <27> DQ12_B FBD_D55 <27>
N13 P13
DQ14_B FBD_D17 <27> DQ13_B FBD_D52 <27>
M13 N13
DQ15_B FBD_D19 <27> DQ14_B FBD_D54 <27>
M13
2020/08/12 DQ15_B FBD_D53 <27>
Del SNN Part N5 H3 2020/08/12
TCK CA0_A FBD_CMD1 <27> Del SNN Part
F10 G11 N5 H3
TDI CA1_A FBD_CMD13 <27> TCK CA0_A FBD_CMD33 <27>
N10 G4 F10 G11
TDO CA2_A FBD_CMD12 <27> TDI CA1_A FBD_CMD45 <27>
F5 H12 N10 G4
TMS CA3_A FBD_CMD24 <27> TDO CA2_A FBD_CMD35 <27>
H5 F5 H12
CA4_A FBD_CMD11 <27> TMS CA3_A FBD_CMD46 <27>
H10 H5
CA5_A FBD_CMD15 <27> CA4_A FBD_CMD36 <27>
J12 H10
CA6_A FBD_CMD22 <27> CA5_A FBD_CMD43 <27>
J11 J12
CA7_A FBD_CMD23 <27> CA6_A FBD_CMD48 <27>
Follow NV CRB J4 J11
CA8_A FBD_CMD0 <27> CA7_A FBD_CMD47 <27>
J3 Follow NV CRB J4
CA9_A FBD_CMD2 <27> CA8_A FBD_CMD34 <27>
J3
CA9_A FBD_CMD32 <27>
L3
FBD_WCKB01 CA0_B FBD_CMD5 <27>
D4 M11 L3
<27> FBD_WCKB01 FBD_WCKB01# WCK_A CA1_B FBD_CMD18 <27> FBD_WCKB45 CA0_B FBD_CMD29 <27>
D5 M4 D4 M11
<27> FBD_WCKB01# FBD_WCK23 WCK#_A CA2_B FBD_CMD7 <27> <27> FBD_WCKB45 FBD_WCKB45# WCK_A CA1_B FBD_CMD52 <27>
R11 L12 D5 M4
<27> FBD_WCK23 FBD_WCK23# WCK_B CA3_B FBD_CMD20 <27> <27> FBD_WCKB45# FBD_WCK67 WCK#_A CA2_B FBD_CMD40 <27>
R10 L5 R11 L12
<27> FBD_WCK23# WCK#_B CA4_B FBD_CMD8 <27> <27> FBD_WCK67 FBD_WCK67# WCK_B CA3_B FBD_CMD50 <27>
L10 R10 L5
CA5_B FBD_CMD16 <27> <27> FBD_WCK67# WCK#_B CA4_B FBD_CMD39 <27>
K12 L10
CA6_B FBD_CMD21 <27> CA5_B FBD_CMD42 <27>
K11 K12
W=16mils CA7_B K4
FBD_CMD19 <27> CA6_B K11
FBD_CMD49 <27>

+FBDA_VREFC
CA8_B
CA9_B
K3 FBD_CMD6
FBD_CMD4
<27>
<27>
W=16mils CA7_B
CA8_B
K4 FBD_CMD51
FBD_CMD28
<27>
<27>
K1 K3
VREFC +FBVDDQ +FBDB_VREFC CA9_B FBD_CMD30 <27>
K1
C1 VREFC +FBVDDQ
J1 VDDQ1 E1 C1
<27> FBD_CMD3 RESET# VDDQ2 VDDQ1
H1 J1 E1
VDDQ3 <27> FBD_CMD31 RESET# VDDQ2
L1 H1
B1 VDDQ4 P1 VDDQ3 L1
C D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 C
F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1
G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2
+FBDA_VREFC M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2
N1 VSS5 VDDQ9 F4 +FBDB_VREFC M1 VSS4 VDDQ8 C4
R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4
VSS7 VDDQ11 VSS6 VDDQ10
2

U1 T4 R1 N4
1K_0402_5%

VSS8 VDDQ12 VSS7 VDDQ11

2
A2 B5 U1 T4
RV484

1K_0402_5%
CHD@ V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5

RV485
C3 VSS10 VDDQ14 B10 CHD@ V2 VSS9 VDDQ13 U5
D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10
1

F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10

1
G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11
M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11
N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11
R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11
T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13
A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13
E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14
H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14
L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14
P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14
V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14
C5 VSS24 VDDQ28 V4 VSS23 VDDQ27 T14
T5 VSS25 C5 VSS24 VDDQ28
C10 VSS26 A1 T5 VSS25
T10 VSS27 VDD1 V1 C10 VSS26 A1
A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1
E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2
H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2
L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5
P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5
V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10
C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10
D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13
F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13
G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14
M12 VSS38 VDD12 +1.8VSDGPU_AON G12 VSS37 VDD11 V14
N12 VSS39 M12 VSS38 VDD12 +1.8VSDGPU_AON
R12 VSS40 A5 N12 VSS39
VSS41 VPP1 VSS40
Follow NV CRB
T12 V5 Follow NV CRB R12 A5
A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5
V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10
B14 VSS44 VPP4 V13 VSS43 VPP3 V10
D14 VSS45 R4 FBD_WCK01 B14 VSS44 VPP4
VSS46 WCK0_t_B,NC FBD_WCK01# FBD_WCK01 <27> VSS45 FBD_WCK45
F14 R5 D14 R4
VSS47 WCK0_c_B,NC FBD_WCK01# <27> VSS46 WCK0_t_B,NC FBD_WCK45# FBD_WCK45 <27>
G14 F14 R5
VSS48 VSS47 WCK0_c_B,NC FBD_WCK45# <27>
M14 G5 G14
N14 VSS49 RFU_A,NC M5 M14 VSS48 G5
R14 VSS50 RFU_B,NC N14 VSS49 RFU_A,NC M5
B U14 VSS51 180-BALL D10 FBD_WCKB23# R14 VSS50 RFU_B,NC B
VSS52 WCK1_c_A,NC FBD_WCKB23# <27> VSS51
SGRAM GDDR6 D11 FBD_WCKB23 U14 180-BALL D10 FBD_WCKB67#
WCK1_t_A,NC FBD_WCKB23 <27> VSS52 WCK1_c_A,NC FBD_WCKB67# <27>
SGRAM GDDR6 D11 FBD_WCKB67
WCK1_t_A,NC FBD_WCKB67 <27>
K4Z80325BC-HC14_FBGA180~D
SA0000C6280 K4Z80325BC-HC14_FBGA180~D
@ SA0000C6280
2020/08/12 @
Del SNN Part 2020/08/12
Del SNN Part

+1.8VSDGPU_AON +1.8VSDGPU_AON

+FBVDDQ +FBVDDQ
CV392

CV393

CV394

CV395

CV426

CV427

CV428

CV429
1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV396

CV397

CV398

CV399

CV400

CV411

CV412

CV413

CV430

CV431

CV432

CV433

CV434

CV435

CV436

CV437

CV438

CV439

CV440

CV441

CV442

CV443

CV444

CV445

CV446

CV447
CHD@ CV4011

CHD@ CV4022

CHD@ CV4033

CHD@ CV4044

CHD@ CV4055

CHD@ CV4066

CHD@ CV4077

CHD@ CV4088

CHD@ CV4099

CHD@ CV4100

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@
2 2 2 2 2 2 2 2
CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV414

CV415

CV416

CV417

CV448

CV449

CV450

CV451

1 1 1 1 1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

CLOSE OR UNDER DRAM CLOSE OR UNDER DRAM

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

CHD@

2 2 2 2 2 2 2 2
1U_0402*18 (X6S) 1U_0402*18 (X6S)
10U_0603*4 (X6S) 10U_0603*4 (X6S)

+FBVDDQ

+FBVDDQ +FBVDDQ
A A
1

330U_D2_2V_Y
+FBVDDQ
+
1CV386

1CV387

1CV388

1CV389

1CV390

1CV391

1CV420

1CV421

1CV422

1CV423

1CV424

1CV425

CV619
CV384

CV385

CV418

CV419
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
330U_D2_2V_Y

@
+
CV618
CHD@

CHD@

CHD@

CHD@
CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

CHD@ 2

2 2 2 2
2
@

BULK DECAPS CLOSE OR UNDER DRAM

AROUND DRAM BULK DECAPS CLOSE OR UNDER DRAM AROUND DRAM

Security Classification Compal Secret Data Compal Electronics, Inc.
2020/08/16 2021/08/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E-GDDR6_D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 35 of 122
5 4 3 2 1
 A B C D E

GEN2 gain control by VBIOS 20201130C For OVRM Keep ON

uPI_GEN2@ uPI_GEN2@ GEN2 NV suggest BS_IN3,4 need also connect with BS_IN2(CSSP_FBVDD)
uPI_GEN2@ uPI_GEN2@ ON_GEN2@ ON_GEN2@ CV271 CV274 UPI GEN2 need check on 2021/01 GEN2 gain control by VBIOS No use SH_P/N need PU the same voltage as no use BS_IN
RV101 RV106 RV101 RV106 0.1U 25V K X7R 0402 0.1U 25V K X7R 0402 20210914
change +3V_OVRM +3VS GEN1@ uPI_GEN2@ uPI_GEN2@ uPI_GEN2@ uPI_GEN2@
SE00000W210 SE00000W210 RV3088 RV105 RV116 RV103 RV109 +3V_OVRM
from 1000P to 0.1U 51 +-5% 0402 51 +-5% 0402 51 +-5% 0402 51 +-5% 0402 51 +-5% 0402
51 +-5% 0402 51 +-5% 0402 0_0402_5% 0_0402_5% SD028510A80 SD028510A80 SD028510A80 SD028510A80 SD028510A80
GEN2 ON-Semi no need BS_IN 1000pF Pull down

1
0_0402_5%2 @ 1 RV178
SD028510A80 SD028510A80 SD028000080 SD028000080 ON_GEN2@ ON_GEN2@ ON_GEN2@ ON_GEN2@ RV1933
GEN2 UPI need 1000pF Pull down-->need check on 2021/01 RV105 RV116 RV103 RV109 0_0402_5%
20210914 UPI-Semi RV101/RV106 change to 51 ohm 1 0 +-5% 0402 0 +-5% 0402 0 +-5% 0402 0 +-5% 0402 GEN1@
UPI-Semi suggest pop CV274/CV271 when GEN2 NV Suggest CV272 SD028000080 SD028000080 SD028000080 SD028000080

2
Rev0.2 Keep NV suggest to unpop when GEN2. 0.1U_0201_10V6K 20201130C
add UPI_gen1 and on_gen1 bom structure OVRM@ RV192 2 GEN2@ 1 0_0402_5% CSSP_FBVDD
2
add 80W and 100W bom structure
2 @ 1
OVR-M GEN1 BOM options CSSP_B+ 75K_0402_1%1 GEN1@ 2 RV101 PFM_CH1_BS_IN1 NV Suggest 0_0402_5% 2 @ 1 RV3077 100_0402_1%1 GEN1@ 2 RV103 CSSP_B+ RV3099 0_0402_5%
CSSP_B+ <104>
1
based on GPU TGP RV104 CV273 CV273 1

1
RV104 uPI_GEN1@ 1000P_0402_50V7K 1 2 CV271 1 2 CV273 0.1U 25V K X7R 0402 680P_0402_50V7K

1
ON_GEN1@ 680P_0402_50V7K uPI_GEN2@ GEN1@

2K_0402_5%
RV110
ON_GEN1@

2K_0402_5%
RV111
ON_GEN1@

2K_0402_5%
RV112
ON_GEN1@

2K_0402_5%
RV113
ON_GEN1@
GEN1@ 665_0402_1% ON_GEN2@ SE00000W210 SE074681K80

2
499_0402_1%
SD034499080 0_0402_5%2 GEN1@ 1 RV105 CSSN_B+
CSSP_FBVDD 75K_0402_1%1 GEN1@ 2 RV106 PFM_CH1_BS_IN2 CSSN_B+ <104>

2
RV108 uPI_GEN1@ PFM_CH1_SH_IN_P3
RV108 PFM_CH1_SH_IN_N3
1000P_0402_50V7K 1 2 CV274 1 2 SNN_PFM_CH1_SH_IN_P4
499_0402_1% ON_GEN1@ SNN_PFM_CH1_SH_IN_N4
Need change to R-short

1
SD034499080 GEN1@ 665_0402_1%
RV114 RV115 0_0402_5%2 GEN2@ 1 RV3088 51 +-5% 0402 1 GEN1@ 2 RV109 CSSP_FBVDD RV110 GEN2@ RV111 GEN2@ RV112 GEN2@ RV113 GEN2@
RV122 RV122 0_0402_5% 0_0402_5% CSSP_FBVDD <104>
uPI_80W_GEN1@ uPI_100W_GEN1@ @ @ CV275 CV275

1
RV122 CV275 0.1U 25V K X7R 0402 0.1U 25V K X7R 0402 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

2
ON_100W_GEN1@ 680P_0402_50V7K uPI_GEN2@ GEN1@
255_0402_1% 196_0402_1% UV20 ON_GEN2@ SE00000W210 SE00000W210 SD028000080 SD028000080 SD028000080 SD028000080

2
SD034255080 SD00000XE80 CSSN_FBVDD
261_0402_1% 3 27 0_0402_5%2 GEN1@ 1 RV116 RV110 uPI_GEN1@ RV111 uPI_GEN1@ RV112 uPI_GEN1@ RV113 uPI_GEN1@
uPI_GEN2@ 6 BS_IN1 VCC CSSN_FBVDD <104>
SD034261080 PFM_CH1_BS_IN3 11 BS_IN2 PFM_CH1_SH_IN_P1
RV123 uPI_GEN1@ RV123 2
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 1 PFM_CH1_SH_IN_N1
BS_IN4 SH_IN_N1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
5 PFM_CH1_SH_IN_P2
SH_IN_P2 4 PFM_CH1_SH_IN_N2
475_0402_1% 0_0402_5%
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 ADC_IN_N <26> SD028000080 SD028000080 SD028000080 SD028000080
SD034475080 SD028000080 0_0402_5%1 GEN2@ 2 RV118 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4 ADC_IN_P <26> Need change to R-short
RV122 1 2 340_0402_1% ON_80W_GEN1@ SH_O1 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4 ON_GEN2@
RV123 1 2 634_0402_1% ON_GEN1@ IMON1 7 SH_O1 SH_IN_N4 ADC_IN_P RV125 1 2 0_0201_5% CV276 1 2 47P_0402_50V8J
SH_O2 2
RV124 1 2 169_0402_1% @ SH_O3 10 20 ON_GEN2@
RV126 1 2 169_0402_1% @ BG_REF_OUT 17 SH_O3 DIFF_OUT_P 19 @ CV3088
SH_O4 DIFF_OUT_N ADC_IN_N 47P_0402_50V8J RV127 1 2 0_0201_5% CV277 1 2 47P_0402_50V8J
30 PFM_PF_BSOK_R 1
NV Suggest no use IMON PIN 0_0402_5% ON_GEN2@
0.015U_0402_16V7K

0.015U_0402_16V7K

0.015U_0402_16V7K

0.015U_0402_16V7K

RV128 BS_OK ON_GEN2@

uPI PD GND 1 @ 2 PFM_ADC_MUX_SEL_R 29 8 IMON2
1 1 1 1
ON NC Floating MUX_SEL NC 18 BV_REF
GEN1@

GEN1@

NC 21 ADSR0
CV278

CV279

CV280

CV281

@ @ RV130 0_0201_5%
PFM_ADC_FILTER_EN 28 NC 31 SYNC 1 TH1 1 GEN2@ 2
2 2 2 2 2 ENABLE NC 2

2
23 PFM_BG_REF_OUT
PAD~D RV131 1 GEN1@ 2 0_0201_5% ON_GEN1@
PFM_SKIP_R 25 BG_REF_OUT 24 PFM_BS_REF RV134 1 GEN1@ 2 RV132 1 2 237K_0402_1% 1 OVRM@ 2 RV196
SKIP BS_REF 22 0_0201_5% 10K_0402_1% RV133 0_0201_5%
CM_REF_IN RV132 GEN2@ RV132 uPI_GEN1@ uPI_GEN2@
PFM_ADC_FILTER_MODE 26 33

1
MODE_SEL GND
31.6K_0402_1% 316K_0402_1%
<26> GPIO22_ADC_MUX_SEL NCP45492XMNTWG_QFN32_4X4 SD034316280 SD034316380
ON_GEN1@ NV Suggest no use IMON PIN
SA0000CQX00 PFM_BS_REF_R
uPI PD GND
1

NV Suggest no use IMON PIN RV193 ON NC Floating

uPI PD GND 0_0402_5% OVR-M GEN1/GEN2 IC Part number PFM_CM_REF_IN 1 2 PFM_CM_REF_IN_R
1
uPI_GEN2@ RV194 GEN1@ 0_0402_5% CV285
ON NC Floating UV20 uPI_GEN1@ OVRM@ 1000P_0402_50V7K
Can Remove
2

1000P_0402_50V7K
CV4101
1 1 1
2

1000P_0402_50V7K
CV283
GEN1@

1000P_0402_50V7K
CV3099
OVRM@
1 2 2 GEN1@ 1
S IC US5650QQKI WQFN 32P POWER MONITOR @ RV135 GEN1@ 365K_0402_1% RV136 681K_0402_1%
SA0000CMA00 2 2 2
UV20 ON_GEN2@
PFM_BG_REF_OUT_R 2 1 BG_REF_OUT
RV139 GEN2@ 0_0201_5%
S IC NCP45495XMNTWG QFN 32P MONITOR
SA0000DUX00
- RV139 NV Suggest POP when GEN2
UV20 uPI_GEN2@

S IC US5651AQKI WQFN 32P POWER MONITOR +3V_OVRM +3V_OVRM

SA0000DY100

1
RV148 RV147
10K_0201_5% 10K_0201_5%
GEN2@ @
3 3

2
ADSR0 PFM_CM_REF_IN
1

1
RV149 RV150
10K_0201_5% 10K_0201_5%
@ GEN2@
2

2
Pin23 : I2C_CLK(PFM_BG_REF_OUT)
Pin24 : I2C_DATA(PFM_BS_REF)
ADSRO(Pin21) ADSR1(Pin22,PFM_CM_REF_IN)
+3V_OVRM
1

RV159 RV200 1 GEN2@ 2 0_0201_5% VGA_I2CC_SCL_OVRM RV129 2 GEN2@ 10_0402_5% PFM_BG_REF_OUT

<26> VGA_I2CC_SCL
10K_0402_1%
OVRM@ RV201 1 GEN2@ 2 0_0201_5% VGA_I2CC_SDA_OVRM RV144 2 GEN2@ 10_0402_5% PFM_BS_REF
<26> VGA_I2CC_SDA
2

PFM_PF_BSOK_R RV203 1 @ 2 0_0201_5%

<26,103> VGA_I2CC_SCL_PWR
RV202 1 @ 2 0_0201_5%
<26,103> VGA_I2CC_SDA_PWR
1

NV Suggest RV198
24.9K_0402_1%
+3V_OVRM +3V_OVRM +3V_OVRM ON_GEN2@
2

RV152 GEN2@
1

4 4
RV141 1 Follow NV CRB, OVRM/PWR IC use same I2C power rail.
1

10K_0402_1% 10K_0201_5% CV306

RV151 RV152 SD034100280 @ 1U_0201_6.3V6M
10K_0201_5% 10K_0402_1% ON_GEN2@
2

@ GEN1@ 2
2

PFM_ADC_FILTER_MODE PFM_SKIP_R PFM_ADC_FILTER_EN

1

ON-SEMI Suggest need add RC filter.

RV156 RV199 RV145
10K_0201_5% 30.1K_0402_1% 10K_0201_5% Security Classification Compal Secret Data Compal Electronics, Inc.
@ @ OVRM@ 2019/09/20 2020/09/20 Title
Issued Date Deciphered Date
GN20E-OVR-M
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HH67A MB LA-M241P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 24, 2021 Sheet 36 of 112
A B C D E
 A B C D E F G H

10/23 10/13
remove UV104 Intel naming change +1.8VALW_PRIM
+3VSDGPU merge to U14 with +3VS

+1.8VALW_PRIM
+1.8VSDGPU_AON

VGA@

VGA@
1 1

22U_0603_6.3V6M

1U_0201_6.3V6M
1

1
UV12

CV632

CV2795
2
2 1
2 VIN1
VIN2
+5VALW 7 6
VIN thermal VOUT

10U_0402_6.3V6M

0.1U_0201_10V6K
CV2792
VGA@ 2 1 3 1 1
VBIAS

CV2789 VGA@
CG340 0.1U_0201_10V6K
RV507 2 @ 1 1V8_AON_EN_R 4 5
<26> 1V8_AON_EN ON GND
0_0402_5% 1

1
2 2

VGA@
RV413 @ CV2794 AOZ1334DI-01_DFN8-7_3X3
@ 1M_0402_5% 0.01U_0402_16V7K VGA@
2
SA000070V00

2
2 2

3 3

For Power down sequence

+PEX_VDD +FBVDDQ +NVVDD1

+3VS
2

1
RV498 VGA@ +3VS RV493 +3VS
20_0402_5% VGA@ 20_0402_5% RV491 VGA@
2

1_0603_5%
RV494 VGA@
1

1
2

2
100K_0402_5%

2
RV496 VGA@ VGA@ RV495
100K_0402_5% VGA@ 100K_0402_5%
1

QV22A VGA@ QV23B

PEX_VDD_EN#
D
2 G QV21B VGA@ PJT138KA_SOT363-6 PJT138KA_SOT363-6
1

1
3

6
S PJT138KA_SOT363-6
FBVDDQ_EN# NVVDD1_EN#
D D
5 G 2 G
1

S S

VGA@ QV21A VGA@ QV23A

4

1
PJT138KA_SOT363-6 PJT138KA_SOT363-6
3

3
PEX_VDD_EN NVVDD1_EN
D D
5 G 5 G
<26,110> PEX_VDD_EN <26,103> NVVDD1_EN
6

S VGA@ S
FBVDDQ_EN 2
D

+1.8V/+3.3V level
G
QV22B +1.8V/+3.3V level
<26,108> FBVDDQ_EN
4

S
PJT138KA_SOT363-6
+3.3V level
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/08/16 Deciphered Date 2021/08/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GN20E-GPU Power control
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 37 of 122
A B C D E F G H
 A B C D E

LCD POWER CIRCUIT

I (Max) : 0.372 A(+3VS_EDP)
RDS(Typ) : 70 mohm
+3VS
V drop : 0.026 V
UV117
+LCDVDD U2 redriver for camera
5 1 W=60mils 30mA
IN OUT +3VALW

0.1U_0201_10V6K
2 1 1

4.7U_0402_6.3V6M
GND CS86 2 1 1U_0201_6.3V6M

CV4173

CV4174
1
CV4172 LCD_ENVDD 4 3 U2RD@ US5
1 <39> LCD_ENVDD EN OC +3VALW 1
1U_0201_6.3V6M CS87 2 1 .1U_0402_16V7K 12
2 2 VCC 2 USB20_P7
High active SY6288C20AAC_SOT23-5 U2RD@
D1P

1
2 EN_VL:1.1V @ USB20_P7 7 1 USB20_N7
<13> USB20_P7 D2P D1M

1
@ USB20_N7 8
<13> USB20_N7 D2M
RV627 RS88 RS89 1 U2RD@ 2 0_0402_5% REQ = RS36
100K_0402_5% 47K_0402_5% U2RD@ 6
U2RD@ CS88 2 1 .1U_0402_16V7K 5 EQ 11 1 2

2
@ T330 4 RSTN VREG CS89 .1U_0402_16V7K

2
@ T331 3 SCL/CD U2RD@
9 SDA 10
ENA_HS GND
PD 100K For Gitch by Intel

1
TUSB212RWBR_X2QFN12_1P6X1P6
RS90 RDC1 = RS37 , RCD2 = RS38 U2RD@
DMIC_DATA 2 1 DMIC_DATA_R
TO eDP cable 47K_0402_5% SA0000C8Z00
<56> DMIC_DATA @ U2RD@
RA1 0_0402_5%

2
PCH_DMIC_DATA_L
Use SA0000C8Z00 symbol
2 1
<10> PCH_DMIC_DATA_L
RA3 33_0402_5%

PCH_DMIC_CLK_L 2 1
<10> PCH_DMIC_CLK_L
LA11 EMC@ BLM15PX221SN1D_2P
SM01000Q500
DMIC_CLK 2 1 DMIC_CLK_R
<56> DMIC_CLK
LA9 XEMC@ BLM15PX221SN1D_2P
SM01000Q500
change PN to SM01000Q500
100_0402_1%
1

+3VS
RA2
EMC@

20200728
- Remove 3S@ config
Place closed to JEDP1

2
+19VB Max: 222mA +INVPWR_B+_1
2

2
LCD enable signal RV688 Inrush: 1.5A +3VS +LCDVDD
2
330P_0402_50V7K
CA1
EMC@

10K_0201_5%
1
@ W=60mils LV12 W=60mils
HCB2012KF-221T30_0805 eDP Conn.

1
1 2 +INVPWR_B+_1
2 1 1
Follow Raptor RV623 LV14
1 @ 2 EDP_HPD_R HCB2012KF-221T30_0805 CV4177 CV4178 JEDP1
<39,59> EDP_HPD
1 2
W=60mils 1
0_0402_5% 0.1U_0201_10V6K .1U_0402_16V7K
2 2 2 1
SM01000EJ00 3000ma @ 2

CV4176 @
3
MiniLED power and GND connetctor 220ohm@100mhz

0.1U_0201_10V6K
3

1000P_0402_50V7K
4

100K_0402_5%
1 DCR 0.04 1 1 4

1
CV4175 5

EMC@ CV4235
+19VB +INVPWR_B+_2 68P_0402_50V8J 6 5

RV625
Max: 222mA 6
@ BKL_PWM_LCD 7
Inrush: 1.5A 2 2 2 BKOFF#_R 8 7
W=60mils LV13 W=60mils Note: Unmount LV5 when panel boost +LCDVDD EDP_HPD_R 9 8

2
HCB2012KF-221T30_0805 10 9
circuit was use. (2S battery cell) 10
1 2 10/30
W=60mils 11
LV15 RV679 RV680 NV check need to 12 11
HCB2012KF-221T30_0805 1.0 add 0.1u for ESD TD Used 680P change 0ohm(orignal is 0.1u) 13 12
1 2 CV4183 ~ CV4190 change from 0.1u to 0.22u PANEL_OD_EN 14 13
<12> PANEL_OD_EN 14
SM01000EJ00 3000ma 2021/4/27 RV679 and RV680 15
BKL_PWM_LCD EDP_AUXN_C 15
CV4231 @

RV621 1 @ 2 0_0201_5% RV679 1 2 .1U_0402_16V7K 16

220ohm@100mhz <39> INV_PWM +LCDVDD
change from 0ohm to 0.1u_0402 <39> EDP_AUXN EDP_AUXP_C 16 eDP
1000P_0402_50V7K

1 1 RV680 1 2 .1U_0402_16V7K 17
DCR 0.04 1 2 100K_0201_5%
<39> EDP_AUXP
18 17
CV4230 RV622 @ (4-Lane)
68P_0402_50V8J RV659 1 @ 2 1K_0402_5% VGA_I2CB_SCL_Q CV4183 1 2 0.22U_0402_16V7K EDP_TXP0_C 19 18
<39> EDP_TXP0 19
@ RB751S40T1G_SOD523-2 CV4184 1 2 0.22U_0402_16V7K EDP_TXN0_C 20
2 2 2 1 BKOFF#_R 1 2 1K_0402_5% VGA_I2CB_SDA_Q <39> EDP_TXN0 21 20
RV660 @
<39> BKOFF# 21
VGA@ DV8 CV4185 1 2 0.22U_0402_16V7K EDP_TXP1_C 22
<39> EDP_TXP1 22
RV626 1 2 10K_0201_5% CV4186 1 2 0.22U_0402_16V7K EDP_TXN1_C 23
<39> EDP_TXN1 23
1.0 change pin5 from power to NC, pin6 from NC to GND GLITCH@ 24
CV4187 1 2 0.22U_0402_16V7K EDP_TXP2_C 25 24
HEFEN_AWB01-S12CIA-HF <39> EDP_TXP2 25
PD 100K For Gitch by Intel CV4188 1 2 0.22U_0402_16V7K EDP_TXN2_C 26
<39> EDP_TXN2 26
12 14 10/30 27
11 12 GND 13 NV suggestion RV626 change to 10K PD CV4189 1 2 0.22U_0402_16V7K EDP_TXP3_C 28 27
<39> EDP_TXP3
10 11 GND RV624 change to DV8 CV4190 1 2 0.22U_0402_16V7K EDP_TXN3_C 29 28
3 9 10 <39> EDP_TXN3 30 29 3
9 20200721 - For DMIC (CCD 8pin module) 30
8 RV649 1 @ 2 0_0402_5% VGA_I2CB_SCL_Q 31
+3VS <26> VGA_I2CB_SCL_Q
7 8 1.0 DMIC_VCC change to +1.8VALW_PRIM For 32 31
6 7 sync with DMIC vlotage RV651 1 @ 2 0_0402_5% DDS <26> VGA_I2CB_SDA_Q
VGA_I2CB_SDA_Q 33 32
+1.8VALW_PRIM
5 6 +DMIC_VCC 34 33
+INVPWR_B+_2
4 5 +3V_CAM 35 34
3 4 For +3VALW RV690 1 @ 2 0_0603_5% USB20_N7_CAMERA 36 35
2 3 Camera USB20_P7_CAMERA 37 36
1 2 RV691 1 @ 2 0_0603_5% 38 37
1 +3VS 38
DMIC_CLK_R 39
JP6 DMIC_DATA_R 40 39
USB20_N7 RV628 1 @ 2 0_0402_5% 40

2
USB20_P7 RV629 1 @ 2 0_0402_5% 41
Touch creen 42 GND
I (Max) : 0.372 A(+3VS_EDP) OLED PMIC connetctor GND
RDS(Typ) : 70 mohm 43
+3VS +3VS 44 GND
V drop : 0.026 V GND
UV119 +TS_PWR XEMC@ ACES_50473-0400M-P01
100K_0402_5% 1 TS@ 2 TS_I2C_INT# 5 1 W=60mils DV7 CONN@
RV319 IN OUT +ELVSS YSLC05CH_SOT23-3
2 +ELVDD
SCA00004300
0.1U_0201_10V6K

1
SOC_TS_RST# 1 TS@ 2 100K_0402_5% GND JOLED1
1 1 1
4.7U_0402_6.3V6M

RV320 CV4234 4 3 1
CV4232

CV4233

1U_0201_6.3V6M EN OC 2 1
TS@ SY6288C20AAC_SOT23-5 3 2
2 TS@ 2 2 4 3
TS@ @ 5 4
6 5
PMIC_EN 7 6
<11,16,39,40,58,69,72,78,85,91> SUSP# <111> PMIC_EN 7
8
9 8 11
High active 9 G1
JTS1 EN_VL:1.1V 10 12
10 10 G2
9 GND2 ACES_50208-0100C-P03
GND1
8
20210719
4 4
SOC_TS_RST# 7 8 Check Pin define
to SOC <7> SOC_TS_RST# TS_I2C_INT# 6 7 Check symbol
to SOC <7> TS_I2C_INT# I2C_3_SCL 5 6
to SOC <12> I2C_3_SCL I2C_3_SDA 4 5
to SOC <12> I2C_3_SDA TS_EN 3 4
to EC <59> TS_EN
2 3
1 2 20210825
1 changeg pin define
+TS_PWR
20210719 CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
ACES_50208-00801-003 2020/09/25 2021/12/31 Title
Check Pin define Issued Date Deciphered Date
+TS_PWR source ? THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 38 of 112
A B C D E
 1 2 3 4 5

+1.2VS_DDS
+3VS

LV7 CV4121 +5VALW _L

1 2 VDD33_A 1U_0201_6.3V6M

1
BLM18KG331SN1D_2P 2 1

22P_0201_50V8J

10U_0402_6.3V6M

10U_0402_6.3V6M
1
VDD12_A 10/23 RV581
change from +3VS to +1.8VALW_PRIM

CV4122
UV108 4.99K_0402_1%
VDDA12_A +1.8VALW _PRIM 10 1
VDD VOUT 1 1
9 2 2

CV4133

CV4128
CV4132

2
VDDRX12_A VIN VOUT

4.7U_0402_6.3V6M
CV4123

0.1U_0201_10V6K
CV4129

0.1U_0201_10V6K
CV4124

0.01U_0201_16V7
CV4130

0.01U_0201_16V7
CV4125

0.1U_0201_10V6K
CV4131

1U_0201_6.3V6M
CV4126

10U_0402_6.3V6M
CV4127
1 1 1 1 1 1 1 20210316 10U_0402_6.3V6M 8 3 @
VIN VOUT

1
reserve RV3100 for DDS PWR enable 2 1 7 4
VDDTX12_A 2 RV3100 1 1.2VS_DDS_EN 6 VIN ADJ/NC 5 2 2
2021/04/27 EN PGOOD
0_0201_5%
EN pin control change to +1.8VALWS

1
2 2 2 2 2 2 2 11
PAD RV582
2 RV687 1 RT9059GQW _W DFN10_3X3 10K_0402_1%
<11,16,38,40,58,69,72,78,85,91> SUSP# 0_0201_5% SA000071S00
@ 1 S IC RT9059GQW W DFN 10P LDO

2
A CV4217 A

29

32
56

43

42
55

24
1

3
UV109 1U_0201_6.3V6M
@

VDD33
VDD33

VDD12
VDD12

VDDA12

VDDTX12
VDDTX12

VDDRX12
VDDRX12
VDD_DDC
2 *Vout = 0.8 * ((4.99K+10K)/10K) = 1.1992V
CPU_EDP_TXP0 CV4140 1 2 0.1U_0201_10V6K CPU_EDP_TXP0_C 4
<6> CPU_EDP_TXP0 CPU_EDP_TXN0 CPU_EDP_TXN0_C IN1_D0p +1.2VS_DDS
CV4141 1 2 0.1U_0201_10V6K 5
<6> CPU_EDP_TXN0 IN1_D0n +1.2VS_DDS LV8
CPU_EDP_TXP1 CV4142 1 2 0.1U_0201_10V6K CPU_EDP_TXP1_C 7 LV9 VDDRX12_A 1 2
<6> CPU_EDP_TXP1 CPU_EDP_TXN1 CPU_EDP_TXN1_C IN1_D1p VDD12_A
CV4143 1 2 0.1U_0201_10V6K 8 1 2 BLM18KG331SN1D_2P
<6> CPU_EDP_TXN1 IN1_D1n BLM18KG331SN1D_2P
CPU_EDP_TXP2 CPU_EDP_TXP2_C EDP_TXP0

4.7U_0402_6.3V6M
CS79

0.1U_0201_10V6K
CV4149

0.1U_0201_10V6K
CV4138

0.01U_0201_16V7
CS81

0.01U_0201_16V7
CS80
CV4134 1 2 0.1U_0201_10V6K 10 54
EDP_TXP0 <38> 1 1 1 1 1
<6> CPU_EDP_TXP2 IN1_D2p OUT_D0p

4.7U_0402_6.3V6M
CV4146

0.1U_0201_10V6K
CV4136

0.1U_0201_10V6K
CV4137

0.01U_0201_16V7
CV4147

0.01U_0201_16V7
CV4148
CPU_EDP_TXN2 CV4144 1 2 0.1U_0201_10V6K CPU_EDP_TXN2_C 11 53 EDP_TXN0
<6> CPU_EDP_TXN2 IN1_D2n OUT_D0n EDP_TXN0 <38> 1 1 1 1 1
CPU_EDP_TXP3 CV4135 1 2 0.1U_0201_10V6K CPU_EDP_TXP3_C 12 51 EDP_TXP1
<6> CPU_EDP_TXP3 CPU_EDP_TXN3 CPU_EDP_TXN3_C IN1_D3p OUT_D1p EDP_TXN1 EDP_TXP1 <38> 2 2 2 2 2
CV4145 1 2 0.1U_0201_10V6K 13 50 EDP_TXN1 <38>
<6> CPU_EDP_TXN3 IN1_D3n OUT_D1n 2 2 2 2 2
48 EDP_TXP2
GPU_EDP_TXP0 GPU_EDP_TXP0_C OUT_D2p EDP_TXN2 EDP_TXP2 <38>
CV4150 1 2 0.1U_0201_10V6K 14 47 EDP_TXN2 <38>
<29> GPU_EDP_TXP0 GPU_EDP_TXN0 GPU_EDP_TXN0_C IN2_D0p OUT_D2n
CV4139 1 2 0.1U_0201_10V6K 15
<29> GPU_EDP_TXN0 IN2_D0n EDP_TXP3
45 EDP_TXP3 <38>
GPU_EDP_TXP1 CV4151 1 2 0.1U_0201_10V6K GPU_EDP_TXP1_C 17 OUT_D3p 44 EDP_TXN3
<29> GPU_EDP_TXP1 GPU_EDP_TXN1 GPU_EDP_TXN1_C IN2_D1p OUT_D3n EDP_TXN3 <38>
CV4152 1 2 0.1U_0201_10V6K 18
<29> GPU_EDP_TXN1 IN2_D1n +1.2VS_DDS
GPU_EDP_TXP2 CV4153 1 2 0.1U_0201_10V6K GPU_EDP_TXP2_C 20 +1.2VS_DDS LV10
<29> GPU_EDP_TXP2 GPU_EDP_TXN2 GPU_EDP_TXN2_C IN2_D2p VDDTX12_A
CV4154 1 2 0.1U_0201_10V6K 21 LV11 1 2
<29> GPU_EDP_TXN2 IN2_D2n VDDA12_A 1 2 BLM18KG331SN1D_2P
GPU_EDP_TXP3 CV4155 1 2 0.1U_0201_10V6K GPU_EDP_TXP3_C 22 BLM18KG331SN1D_2P
<29> GPU_EDP_TXP3 IN2_D3p

4.7U_0402_6.3V6M
CS82

0.1U_0201_10V6K
CV4161

0.1U_0201_10V6K
CV4157

0.01U_0201_16V7
CV4162

0.01U_0201_16V7
CV4158
GPU_EDP_TXN3 CV4156 1 2 0.1U_0201_10V6K GPU_EDP_TXN3_C 23 1 1 1 1 1
<29> GPU_EDP_TXN3 IN2_D3n
MUX

4.7U_0402_6.3V6M
CS83

0.1U_0201_10V6K
CV4159

0.1U_0201_10V6K
CV4160

0.01U_0201_16V7
CS84

0.01U_0201_16V7
CS85
28 SW 1_CFG0
CFG0 1 1 1 1 1
27 SW 1_CFG1
RV583 1 2 4.99K_0402_1% DP1_SW 1_REXT 31 CFG1 26 SW 1_CFG2
REXT CFG2 25 SW 1_CFG3 2 2 2 2 2
CFG3 46 SW 1_CFG4 2 2 2 2 2
EC_SMB_CK2_DDS 34 CFG4
EC_SMB_DA2_DDS 33 CSCL 10/30
I2C_ADDR_SW 1 6 CSDA swap EDP_AUXP/EDP_AUXN to correct
I2C_ADDR 58 EDP_AUXP
DP_AUXp_SCL EDP_AUXN EDP_AUXP <38>
57
DP_AUXn_SDA EDP_AUXN <38>
66
65 IN1_SCL
IN1_SDA +3VS
B CPU_EDP_AUXP CPU_EDP_AUXP_C B
<6> CPU_EDP_AUXP CV4163 1 2 0.1U_0201_10V6K 62
CPU_EDP_AUXN CV4164 1 2 0.1U_0201_10V6K CPU_EDP_AUXN_C 61 IN1_AUXp
<6> CPU_EDP_AUXN IN1_AUXn MID1_CA_DET I2C_ADDR_SW 1
52 RV584 1 @ 2 4.7K_0402_5%
64 DP_CADET AUX_CFG RV3106 1 @ 2 4.7K_0402_5%
10/30 63 IN2_SCL EDP_AUXN RV587 1 @ 2 100K_0402_5%
swap GPU_EDP_AUXP/GPU_EDP_AUXN to correct IN2_SDA 1.0 unpop RV587、RV588 EDP_AUXP RV588 1 @ 2 100K_0402_5%
GPU_EDP_AUXP CV4166 1 2 0.1U_0201_10V6K GPU_EDP_AUXP_C 60 MID1_CA_DET RV589 2 1 1M_0402_5%
<29> GPU_EDP_AUXP GPU_EDP_AUXN GPU_EDP_AUXN_C IN2_AUXp EDP_HPD
<29> GPU_EDP_AUXN CV4165 1 2 0.1U_0201_10V6K 59 49
IN2_AUXn OUT_HPD EDP_HPD <38,59>
CPU_EDP_HPD 16 Rev0.2 change P/N to SA0000C8300
<6> CPU_EDP_HPD GPU_EDP_HPD IN1_HPD
19
<26> GPU_EDP_HPD IN2_HPD Vendor recommand for reserve PU and PD for Debug

+3VS 10/30
change to 100K
SW 1_IN1_EQ0
SW 1_IN1_EQ1
SW 1_IN2_EQ0
40
41
38
IN1_EQ0
IN1_EQ1 RSV0
37
36
DDS_RSV0
BackLight +3VS +3VS
RV590 1
RV591 1
@
@
2 100K_0201_5%
2 100K_0201_5%
GPU_EDP_AUXN_C
GPU_EDP_AUXP_C
SW 1_IN2_EQ1 39 IN2_EQ0
IN2_EQ1
RSV1
RSV2
35 AUX_CFG
switch

0.1U_0201_10V6K
1

CV4167
EDP_SW 2 RV592 1 0_0201_5% 9 EC_BKOFF# RV594 2 @ 1
SW <58> EC_BKOFF#
0_0402_5%
EDP_SW IGPU_ENBKL_R RV593 2 @ 1 UV111
<26> IGPU_ENBKL_R
2

L CPU 30 67 +3VS 0_0402_5% 2 SA0000BJI00

5
H VGA PD# EPAD(GND) NL17SZ08DFT2G_SC70-5
2

RV595

VCC
5
100K_0402_5% @ PS8461QFN66GTR-A4_QFN66_5X10 UV110 1
RV689 SOC_ENBKL 1 IN B 4 BKOFF#
1

P
SA0000DIY20 <6,58> SOC_ENBKL BKOFF# <38>
1

100K_0402_5% CV4169 INB 4 ENBKL 2 OUT Y

GND
20210914 0.1U_0201_10V6K DGPU_ENBKL_Q 2 O IN A 11/04
<26> DGPU_ENBKL_Q
1

INA

2
change from SA0000DIY10 to SA0000DIY20 NV suggestion
2 MC74VHC1G32DFT2G_SC70-5~D RV682

3
9/30 @ 10K_0201_5%
SA0000C8300

5
UV113 check CPU and GPU connection
+3VS +3VS +3VS EC_EDP_SW 1

1
INB 4 PW M_SW
DGPU_PW M_SW _Q 2 O
<26> DGPU_PW M_SW _Q INA

G
1

1
2.2K_0402_5%
RE263

2.2K_0402_5%
RE264

MC74VHC1G32DFT2G_SC70-5~D

3
1

+3VS RV596 0_0402_5% +3VS

SA0000C8300
LCDVDD enable
5

RV684 EC_LCD_EN 2 @ 1
G

<59> EC_LCD_EN
C 4.7K_0402_5% C
2

switch 1
2

2
EC_SMB_CK2 3 4 EC_SMB_CK2_DDS CV4170
S

58,62,63,66,72> EC_SMB_CK2 DDS_RSV0 0.1U_0201_10V6K RV681

D

QV42B @ +3VS 100K_0402_5% UV115

G

2N7002KDW _SOT363-6 2 SA0000BJI00

1

5
10/21 NL17SZ08DFT2G_SC70-5

1
check use EC or PCH

GND VCC
5
EC_SMB_DA2 6 1 EC_SMB_DA2_DDS RV685 NV recommand EC UV114 1
1
S

58,62,63,66,72> EC_SMB_DA2 SOC_ENVDD IN B LCD_ENVDD

4.7K_0402_5% CV4168 1 4
D

P
<6> SOC_ENVDD INB OUT Y LCD_ENVDD <38>
QV42A @ 0.1U_0201_10V6K 4 ENVDD 2
2

2N7002KDW _SOT363-6 DGPU_ENVDD_Q 2 O IN A

<26> DGPU_ENVDD_Q

G
Vendor recommand for reserve PU and PD for Debug 2 INA
MC74VHC1G32DFT2G_SC70-5~D

3
5

3.3V UV112 9/30

EC_EDP_SW 1 check CPU and GPU connection SA0000C8300
P

<59> EC_EDP_SW INB EDP_SW

2021/4/27 RV684 and RV685 3.3V 4 3.3V
DGPU_EDP_SW _Q 2 O
change from POP <26> DGPU_EDP_SW _Q INA
G

MC74VHC1G32DFT2G_SC70-5~D
3

@
CFG0/4->DP port1/2 config SA0000C8300 RV736 RV3109 2 1 0_0201_5%
+3V_5V_PW M
L:Auto jitter cleaning mode(default). 0_0201_5% 1.0 reserve RV3109 for UV116 缺缺 1.A add for co-lay Mux
IN1 and IN2 EQ M:Redriving mode. 2 1 +3V_5V_PW M @
H:Full cleaning mode. +3VS INV_PW M
EQ0 EQ1 compensate loss 2 1
INV_PW M <38> UV62
L L 8 dB(default) CFG1/3->Auto EQ option for port1/2 2 @ 1
+5VS EC_EDP_PW M PW M_MUX_EN
L M 11 dB L:Auto EQ enable, EQ auto adjust base on link traning(default). DT31 SCS00006300 RB751S-40_SOD523-2 1 6
L H 14 dB H:Auto EQ disable. RV3110 2 A1 Y1 5

0.1U_0201_10V6K
M L 16 dB 0_0201_5% RV598 2 1 0_0201_5% SOC_BKL_PW M 3 GND VCC 4 MUX_INV_PW M
CFG2->Output config <59> EC_EDP_PW M A2 Y2
M M 17 dB 2
L:Dynamic adjust base on link training(default)

CV4171
M H 18 dB
M:Fix on 400mV/0dB NC7W Z07P6X_SC70-6

1
H L 19 dB +3VS +3VS 1.A add for co-lay Mux
H M 20 dB
H:Fix on 800mv/3.5dB Add PSR2_mode for RV599 @
H H 21 dB
+3VS +3VS
Re-timer/Re-driver 1 0_0201_5%
6 Pin PWM SW:
mode switch by Main- SGMICRO SGM3157 (TBD)

2
UV116
1

2nd - PERICOM PI5A4157 (SA00009IO00)

PCH_GPIO 2021/05/25 8 1 MUX_INV_PW M 3rd - FAIRCHILD FSA4159(SA00006US00)
RV729 RV727 SOC_BKL_PW M 7 V+ COM 2 PW M_MUX_EN 2 RV600 1 0_0201_5% 2021/11/18
<6> SOC_BKL_PW M NC EN
1

@ 4.7K_0402_5% 4.7K_0402_5% DGPU_INV_PW M_Q 6 3 No have symbol now,

<26> DGPU_INV_PW M_Q NO GND Used NC7WZ07P6X_SC70-6 replace it
CFG0/4->DP port1/2 config CFG0/4->DP port1/2 config 5 4
2

D @ RV601 @ RV602 @ RV603 @ RV604 @ RV606 @ RV607 @ RV608 L:Auto jitter cleaning mode(default). L:Auto jitter cleaning mode(default). IN GND 20210819 D
M:Redriving mode. @ M:Redriving mode. PW M_SW remove EC_PWM_MUX
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 2 RV610 1 0_0201_5% TS5A3154DCUR_VSSOP8
6

H:Full cleaning mode. H:Full cleaning mode.

2

2
PSR2_MODE
D D
G 2 G 5
SW 1_IN1_EQ0 SW 1_CFG1 S PSR2_MODE <12> S RV611
SW 1_IN1_EQ1 SW 1_CFG2 QV45B QV45A
PWM 100K_0402_5%
1

SW 1_IN2_EQ0 SW 1_CFG3 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6 IN1 and IN2 EQ

SW 1_IN2_EQ1 PCH_PW M_MUX <6>
@ @ IN EN output INV_PWM

1
1

SW 1_CFG4 SW 1_CFG0 L L NC to COM SOC_BKL_PWM 10/28

switch
1

Internal PD 150K Internal PD 150K @ H L NO to COM DGPU_INV_PWM_Q check connect to EC control or PCH
RV731 X H X EC_EDP_PWM
1

@ RV612 @ RV613 @ RV614 @ RV615 @ RV617 @ RV618 @ RV619 100K_0402_5%

4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

RV730 @ RV728
2

4.7K_0402_5% 4.7K_0402_5% 2020/09/25 2021/12/31 Title

Issued Date Deciphered Date
eDP / DMIC / IR Camera / Touch
2

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 39 of 112
1 2 3 4 5
 5 4 3 2 1

HDMI CVH17 +5VALW +1.1V_HDMI

HDMI_RT_TX_N1 1
DVH3 XEMC@
9 HDMI_RT_TX_N1

1U_0201_6.3V6M HDMI_RT_TX_P1 2 8 HDMI_RT_TX_P1

2 1
+3VS +VDD33_HDMI HDMI_RT_TX_N2 4 7 HDMI_RT_TX_N2
+1.8VSDGPU_AON +VDDIO_HDMI LVH2

1
10/23 LVH1 1 2 HDMI_RT_TX_P2 5 6 HDMI_RT_TX_P2
1

22P_0201_50V8J

10U_0402_6.3V6M

10U_0402_6.3V6M
change from +3VS to +1.8VALW_PRIM RVH9 1 2 BLM18KG331SN1D_2P

0.1U_0201_10V6K

4.7U_0402_6.3V6M
0.01U_0402_16V7K

0.01U_0402_16V7K
UVH2 3.83K_0402_1% BLM18KG331SN1D_2P

CVH18
1 1 1 1 1

0.1U_0201_10V6K
4.7U_0402_6.3V6M
0.01U_0402_16V7K
+1.8VALW_PRIM 10 1

CVH22
1 1 1 1 1

0.1U_0201_10V6K
CVH24 9 VDD VOUT 2 2 Cap. place near pin 3

CVH25

CVH19

CVH27
2
10U_0402_6.3V6M 8 VIN VOUT 3 @ Cap. place near pin

CVH20

CVH29

CVH21

CVH23
2 1 7 VIN VOUT 4 2 2 2 2 2 TVWDF1004AD0_DFN9

CVH26

CVH28
1.1V_HDMI_EN 6 VIN ADJ/NC 5 2 2 2 2 2
D EN PGOOD SC300003Z00 D

1
11
PAD RVH10
RT9059GQW_WDFN10_3X3 10K_0402_1% DVH2 XEMC@
2 RV686 1 SA000071S00 HDMI_RT_CLKN 1 9 HDMI_RT_CLKN
,38,39,58,69,72,78,85,91> SUSP# 0_0201_5% S IC RT9059GQW WDFN 10P LDO +VDD33_HDMI

2
+VDD11_HDMI HDMI_RT_CLKP 2 8 HDMI_RT_CLKP
1
CV4216 UVH1
1U_0201_6.3V6M +VDDA11_HDMI 19 1 HDMI_RT_TX_N0 4 7 HDMI_RT_TX_N0
+VDDRX11_HDMI 41 VDD11 VDD33 13
2
*Vout = 0.8 * ((3.83K+10K)/10K) = 1.1064V VDD11 VDD33
25 HDMI_RT_TX_P0 5 6 HDMI_RT_TX_P0
@ +VDDTX11_HDMI 15 VDDA11
46 VDDRX11 37 HDMI_RT_R_TX_P2 CVH9 1 2 0.22U_0201_10V6M HDMI_RT_L_TX_P2
26 VDDRX11 OUT_D2p 36 HDMI_RT_R_TX_N2 CVH10 1 2 0.22U_0201_10V6M HDMI_RT_L_TX_N2
+VDDIO_HDMI 32 VDDTX11 OUT_D2n 3
+1.1V_HDMI +VDD11_HDMI 38 VDDTX11 34 HDMI_RT_R_TX_P1 CVH11 1 2 0.22U_0201_10V6M HDMI_RT_L_TX_P1
20200818 1.8V VDDTX11 OUT_D1p
43 33 HDMI_RT_R_TX_N1 CVH12 1 2 0.22U_0201_10V6M HDMI_RT_L_TX_N1 TVWDF1004AD0_DFN9
- Re-NAME to HDMI function VDDIO OUT_D1n
LVH3 TMDS DP
1 2 CVH1 1 2 0.22U_0201_10V6M HDMI_TX_P2 2 31 HDMI_RT_R_TX_P0 CVH13 1 2 0.22U_0201_10V6M HDMI_RT_L_TX_P0 SC300003Z00
<29> GPU_HDMI_P2 HDMI_TX_N2 IN_D2p OUT_D0p HDMI_RT_R_TX_N0 CVH14 HDMI_RT_L_TX_N0
BLM18KG331SN1D_2P CVH2 1 2 0.22U_0201_10V6M 3 30 1 2 0.22U_0201_10V6M
TX2 DP0 <29> GPU_HDMI_N2 IN_D2n OUT_D0n
0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

4.7U_0402_6.3V6M

1 1 1 1 1 CVH3 1 2 0.22U_0201_10V6M HDMI_TX_P1 5 28 HDMI_RT_R_CLKP CVH15 1 2 0.22U_0201_10V6M HDMI_RT_L_CLKP

<29> GPU_HDMI_P1 HDMI_TX_N1 IN_D1p OUT_CLKp HDMI_RT_R_CLKN HDMI_RT_L_CLKN
TX1 DP1 CVH4 1 2 0.22U_0201_10V6M 6 27 CVH16 1 2 0.22U_0201_10V6M DVH1
<29> GPU_HDMI_N1 IN_D1n OUT_CLKn HDMI_RT_HPD HDMI_CTRL_DAT
Cap. place near pin 6 3
CVH31

CVH5 1 2 0.22U_0201_10V6M HDMI_TX_P0 8 I/O4 I/O2

2 2 2 2 2 <29> GPU_HDMI_P0 HDMI_TX_N0 IN_D0p HDMI_CTRL_R_CLK
TX0 DP2 CVH6 1 2 0.22U_0201_10V6M 9 40 RVH32 1 @ 2 0_0402_5% HDMI_CTRL_CLK
CVH32

CVH33

CVH34

CVH35

<29> GPU_HDMI_N0 IN_D0n OUT_SCL HDMI_CTRL_R_DAT

39 RVH33 1 @ 2 0_0402_5% HDMI_CTRL_DAT
CVH7 1 2 0.22U_0201_10V6M HDMI_CLKP 11 OUT_SDA 5 2
TXC DP3 <29> GPU_HDMI_CLKP HDMI_CLKN IN_CLKp VDD GND
CVH8 1 2 0.22U_0201_10V6M 12
<29> GPU_HDMI_CLKN IN_CLKn
+VDDRX11_HDMI RVH11 1 @ 2 0_0402_5% GPU_HDMI_CTRL_CLK_R 45 42 HDMI_HPD_R RVH12 1 @ 2 1K_0402_5% HDMI_HPD
<29> GPU_HDMI_CTRL_CLK IN_SCL HPD_SRC
LVH4 RVH13 1 @ 2 0_0402_5% GPU_HDMI_CTRL_DAT_R 44 29 HDMI_RT_HPD_R RVH43 1 @ 2 0_0402_5% HDMI_RT_HPD HDMI_CTRL_CLK 4 1 +HDMI_5V_OUT
<29> GPU_HDMI_CTRL_DAT IN_SDA HPD_SNK I/O3 I/O1
1 2
BLM18KG331SN1D_2P *SCL/SDA can 3V3 or 1V8 AZC099-04S.R7G_SOT23-6
0.1U_0201_10V6K

0.1U_0201_10V6K

4.7U_0402_6.3V6M
0.01U_0402_16V7K

0.01U_0402_16V7K

HDMI_DCIN 7 20 HDMI_ISNK PD XEMC@ SC300001G00

C 1 1 1 1 1 DC_IN ISNK C
+VDD33_HDMI HDMI_EQ 16 35 HDMI_PD RVH14 1 2 4.7K_0402_5% L: Normal Operation
Cap. place near pin HDMI_I2C_ADDR 4 EQ PD 14 HDMI_REXT RVH15 1 2 4.99K_0402_1% H: Chip power-down
I2C_ADDR REXT
2 2 2 2 2 Placed close to REXT pin. For ESD
CVH36

CVH37

CVH38

CVH39

CVH40

HDMI_CFG0 21 18 RVH42 1 @ 2 0_0402_5%

RVH45 1 2 1K_0402_5% 22 CFG0 CSCL 17
1K_0402_5%

1K_0402_5%

1K_0402_5%

HDMI_CFG2 23 CFG1 CSDA

+VDDA11_HDMI RVH16 1 2HDMI_CFG3 24 CFG2
+VDD33_HDMI HDMI_CFG4 CFG3
LVH5 4.7K_0402_5% 10 47 10/22
CFG4 EPAD
1

1 2 add for vendor debug HDMI_RT_L_TX_N0 RVH1 1 2 649_0201_1%

BLM18KG331SN1D_2P HDMI_RT_L_TX_P0 RVH2 1 2 649_0201_1%
1 1 1
0.1U_0201_10V6K

0.01U_0402_16V7K

4.7U_0402_6.3V6M

PS8419GTR-A1_QFN46_4P5X6P5 HDMI_RT_L_TX_N1 RVH3 1 2 649_0201_1%

Cap. place near pin HDMI_RT_L_TX_P1 RVH4 1 2 649_0201_1%

HDMI_ISNK
RVH48

RVH47

RVH46

SA0000DUF10
HDMI_RT_L_TX_N2 RVH5 1 2 649_0201_1%
2

2 2 2 HDMI_RT_L_TX_P2 RVH6 1 2 649_0201_1%

CVH41

CVH42

CVH43

@ @ @ HDMI_RT_L_CLKN RVH7 1 2 649_0201_1%

HDMI_CFG0 HDMI_RT_L_CLKP RVH8 1 2 649_0201_1%
HDMI_CFG2 1.0 RVH34~RVH41 change from RS to 0 ohm, for HDMI impedance issue

0.1U_0201_10V6K
+VDDTX11_HDMI HDMI_CFG4

CVH51
1
LVH6 For EMI
1 2
BLM18KG331SN1D_2P
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

4.7U_0402_6.3V6M

HDMI_RT_L_TX_P2 RVH34 1 2 0_0201_5% HDMI_RT_TX_P2 HDMI_RT_L_TX_P1 RVH36 1 2 0_0201_5% HDMI_RT_TX_P1 2

1 1 1 1 1 1 1
Cap. place near pin
HDMI_RT_L_TX_N2 RVH35 1 2 0_0201_5% HDMI_RT_TX_N2 HDMI_RT_L_TX_N1 RVH37 1 2 0_0201_5% HDMI_RT_TX_N1
2 2 2 2 2 2 2
CVH44

CVH45

CVH46

CVH47

CVH48

CVH49

CVH50

HDMI_RT_L_TX_P0 RVH38 1 2 0_0201_5% HDMI_RT_TX_P0 HDMI_RT_L_CLKP RVH40 1 2 0_0201_5% HDMI_RT_CLKP

B +3VS +3VS B
HDP Deterct
2N7002KDW_SOT363-6

HDMI_RT_L_TX_N0 RVH39 1 2 0_0201_5% HDMI_RT_TX_N0 HDMI_RT_L_CLKN RVH41 1 2 0_0201_5% HDMI_RT_CLKN

2

20200724 RVH44
- Change to SOC_DP2_HPD RVH19 1 @ 2 HDMI_RT_HPD
2

1M_0402_5% 0_0402_5%
QVH1A
G

20200807
- HPD Re-Name to SOC_HDMI_HPD 20200806
1

- Change footprint to ACON_HMRF5-AK1L0C

1 6 HDMI_HPD
S

<6,26> SOC_HDMI_HPD JHDMI1

D

Intel/AMD naming 1 @ 2 HDMI_RT_TX_P2 1

RVH24 0_0402_5% RVH26 +5VS +HDMI_5V_OUT 2 D2+
UVH3 HDMI_RT_TX_N2 3 D2_Shield
100K_0402_5%
HDMI_RT_TX_P1 4 D2-
RY11 design guide rev2.0 W=40mils D1+
use 20K pull down. 3 20200807 5
1

OUT D1_Shield
3

D HDMI_RT_TX_N1 6
1 - Re-NAME to HDMI function
+3VS
5
G
QVH1B
2N7002KDW_SOT363-6
1
IN CVH30
DDC +1.8VSDGPU_AON +HDMI_5V_OUT
HDMI_RT_TX_P0 7
8
D1-
D0+
2 0.1U_0201_10V6K HDMI_RT_TX_N0 9 D0_Shield
S
W=40mils GND 2 +1.8VSDGPU_AON HDMI_RT_CLKP 10 D0-
4

11 CK+
2.2K_0402_5%

2.2K_0402_5%
CK_Shield
2

2
AP2330W-7_SC59-3 HDMI_RT_CLKN 12

2K_0402_5%

2K_0402_5%
13 CK- 20
RVH20

RVH21

RVH18

RVH17
+HDMI_5V_OUT 14 CEC GND 21
+3VS +3VS +3VS HDMI_CTRL_CLK 15 Reserved GND 22
EQ SCL GND
5

HDMI_CTRL_DAT 16 23
1

1
17 SDA GND
G

DDC/CEC GND
2 RVH22 1

GPU_HDMI_CTRL_CLK 4 3 HDMI_CTRL_CLK 18
20K_0402_1%

HDMI_RT_HPD +5V
S

@ @ QVH3A 19
RVH25 @ RVH30 PJT138KA_SOT363-6 HPD
EQ
L0: Pull down with 1k, 4.7K_0402_5% 4.7K_0402_5% @
2

EQ=8dB LOTES_AHDM0001-P001AC
2

HDMI_EQ HDMI_I2C_ADDR HDMI_DCIN

G

A A
L1: Pull down with 20k GPU_HDMI_CTRL_DAT 1 6 HDMI_CTRL_DAT
2 RVH27 1

EQ=7dB
S

QVH3B @
3ohm/10pF
1K_0402_5%

L2: Floating I2C ADDR DC IN

EQ=5dB @ L: 0x10 - 0x2F (Default) RVH29 L: TMDS input is AC Coupled RVH31 PJT138KA_SOT363-6
M: 0x30 - 0x4F 4.7K_0402_5% 4.7K_0402_5%
L3: Pull up with 20k H: 0x90 - 0x9f and 0xD0 - 0xDF H: TMDS input is DC Coupled
EQ=3dB rev1A
2

L4:Pull up with 1k change to correct name

EQ=1dB
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI/2eDP CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 40 of 112
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 41 of 112
5 4 3 2 1
 1 2 3 4 5
+3VS_TBT_0_RETIMER Tolerance (+ 5%/-7.5%):
Burnside Bridge power pins which connected to +3VS_TBT_0_RETIMER should

MB_USB3.1 TypeC Conn. (Port 0/ Re-Timer Master) +3VALW be 3.465v maximum and 3.07v minimum for normal operation.
+3VS_TBT_0_RETIMER ripple: 40mVp-p
+3VS_TBT_2_RETIMER
Delete FIP@ Part

1U_0201_6.3V6M
+3VALW UT4 1

CT626
UT34 1 TypeC@
5 1 CT627
@ IN OUT 4.7U_0402_6.3V6M
RT13161 @ 2 10K_0201_5% SOC_DG_BB_FORCE_PW R_R 2 2
RT13171 TypeC@ 2 10K_0201_5% GND 2
S IC JHL8040R SLMN7 A1 THUNDERBOLT ABO ! 4 3
RT1318 1 TypeC@ 2 100_0201_1% DG0_TEST_PW R_GOOD TypeC@ EN OC
SA0000CAH60 RT1319 1 @ 2 0_0201_5% TBT_2_RETIMER_LS_EN_R SY6288C20AAC_SOT23-5
DG0_POC_GPIO5 <43> TBT_2_RETIMER_LS_EN +3VS_TBT_2_RETIMER
RT1320 1 TypeC@ 2 10K_0201_5% SA000079400
RT1321 1 @ 2 0_0201_5% High active
UT4A BB1 <12> SOC_SLP_DS2#
EN_VL:1.1V TypeC@ RT13221 @ 2 10K_0201_5%

DG0_SPI_DI C6 C9 TBT_2_BBR0_I2C_SCL RT1323 2 @ 1 0_0201_5%

A +3VS_TBT_2_RETIMER DG0_SPI_DO EE_DI I2C_SCL TBT_2_BBR0_I2C_SDA RT1324 2 I2C3_PD1_R_CLK <43> A
B4 E7 @ 1 0_0201_5% I (Max) : 0.37 A(+3V_PRIM)

FLASH
Change DG0_FLSH_SHARE_EN to PD DG0_SPI_CS# B6 EE_DO I2C_SDA A10 TBT_2_BBR0_I2C_INT# RT1325 2 @ 1 0_0201_5%
I2C3_PD1_R_DAT
I2C3_PD1_R_INT#
<43>
<43>
I2C BB1 to PD1 RDS(Typ) : 70 mohm
DG0_SPI_CLK_R 1 @ 2 DG0_SPI_CLK C7 EE_CS# I2C_INT B10 SOC_DG_BB_FORCE_PW R_R
Delete DG0_FLSH_MSTR_SLV 1/7 RT1326 0_0201_5% EE_CLK FORCE_PWR A9 DG0_FLASH_BUSY# SOC_DG_BB_FORCE_PW
10/22
R_R <13,43,44,45,46> V drop : 0.026 V

POC GPIO
RT13271 @ 2 10K_0201_5% DG0_FLSH_SHARE_EN EMI Suggestion
DG0_JTAG_TDI
MISC & FLASH_BUSY#
POC_GPIO_5
POC_GPIO_6
B9
A8
DG0_POC_GPIO5
DG0_POC_GPIO6
TBT_RETIMER_RESET#_R2
check PCH_DG_BB_FORCE_PWR_R is connect to all BB and PD

RT13281 TypeC@ 2 10K_0201_5%

DG0_JTAG_TMS
DG0_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
RT0_SML0CLK
RT0_SML0DATA
RT1329 2 @ 1 0_0201_5%
RT1330 1 VPRO@ 2 0_0201_5%
RT1331 1 VPRO@ 2 0_0201_5%
PLT_RST_R# <11,26,44,45,51,53,66,68,69,70>
SOC_SML0CLK <9,44,45>
+3VS_TBT_2_RETIMER

PCH SML0 to BB2

JTAG
DG0_FLSH_MSTR_SLV DG0_JTAG_TDO TCK SMBUS_SDA DG0_FLSH_SHARE_EN SOC_SML0DATA <9,44,45> TBT_RETIMER_RESET#_R2
RT13321 @ 2 10K_0201_5% C5 A4 RT1333 2 1 10K_0201_5%
RT1334 1 2 TDO POC_GPIO_10 A5 DG0_FLSH_MSTR_SLV RT1335 2 1 10K_0201_5%
@ 10K_0201_5%
POC_GPIO_11
Reserved v-pro only @
RT13361 @ 2 10K_0201_5% DG0_POC_GPIO12 A6 DG0_POC_GPIO12
POC_GPIO_12 & PU at CPU side
RT1337 1 @ 2 10K_0201_5% L3
1AN0_THERMDA M11 NC_L3
DG0_SPI_CLK_R T345 TP@ THERMDA
CT628 2 1 10P_0201_50V8J DG0_RST# need to be output from PD
M12 controller to reset BBR main power NVPRO@
@ B2 TEST_EDM RT0_SML0CLK RT1338 2 1 100K_0201_5%
EMC Suggestion FUSE_VQPS_64 L11 PD1_DG0_RST# RT0_SML0DATA RT1339 2 1 100K_0201_5%
+3VALW RESET# PD1_DG0_RST# <43>
A11 NVPRO@
A12 MONDC L9 DG0_XTAL_25M_XI
Follow E team design PD 100K

DEBUG

Main
RT13401 TypeC@ 2 10K_0201_5% DG0_FLASH_BUSY# L12 NC_A12 XTAL_25_IN M9 DG0_XTAL_25M_XO
MONDC_SVR XTAL_25_OUT
Delete Port1 Share Rom Part 1/7 DG0_TEST_PW R_GOOD B3 L5 AN0_RSENSE
B11 TEST_PWR_GOOD
TEST_EN
RSENSE
RBIAS
L4 AN0_RBIAS 1 2 SMBUS:
A1
RT1341TypeC@
4.75K_0201_0.5%
No support Vpro
A2 ATEST_P
ATEST_N
Intel recommended PD 100K
DG1_RST#:
For PD based systems, DG1_RST# should be output from PD.
For TCPC based systems, DG1_RST# should be output from SOC/EC. BURNSIDE-BRIDGE_BGA105
DG1_BB_FORCE_PWR: @
Connect to EC/PCH for FW update NOTE:
'0' - by default Re-Timer with TBT , AC Caps should be use 0201/25V package.
'1' - for debug only Re-Timer without TBT , AC Caps can be use 0402/25V package.
DG1_FLASH_BUSY#: For non-PD support 25V rating is no must.
UT4D
If Flash sharing is being used, PU should be used.
If Flash sharing isn't being used, PD should be used.

DG1_FLSH_SHARE_EN: <6> TBT_2_TTX_DRX_P0

TypeC@
CT629 1 2 0.22U_0201_10V6M TBT_2_TTX_C_RD_DRX_P0 J1
TBT PORTS J12 TBT_2_TRX_RD_DTX_P0 RT1342 1 TypeC@ 2 2.2_0201_1% TBT_2_TRX_R_DTX_P0 CT630 1 2 0.33U_0201_25V6K TypeC@
TBT_2_TRX_C_DTX_P0 <43>
'0' - Flash isn't shared. 1 Flash per Re-timer CT631 1 2 0.22U_0201_10V6M TBT_2_TTX_C_RD_DRX_N0 J2 ASSRXp1 BSSRXp1 J11 TBT_2_TRX_RD_DTX_N0 RT1343 1 TypeC@ 2 2.2_0201_1% TBT_2_TRX_R_DTX_N0 CT632 1 2 0.33U_0201_25V6K TypeC@
<6> TBT_2_TTX_DRX_N0 ASSRXn1 BSSRXn1 TBT_2_TRX_C_DTX_N0 <43>
'1' - Flash is shared between 2 Re-timers TypeC@ TypeC@

Port B - TypeC Side

CT633 1 2 0.22U_0201_10V6M TBT_2_TRX_C_RD_DTX_P0 G1 G12 TBT_2_TTX_RD_DRX_P0 RT1344 1 TypeC@ 2 2.2_0201_1% TBT_2_TTX_R_DRX_P0 CT634 1 2 0.22U_0201_25V6K TypeC@

Port A - Host Side

B DG1_FLSH_MSTR_SLV: <6> TBT_2_TRX_DTX_P0 ASSTXp1 BSSTXp1 TBT_2_TTX_C_DRX_P0 <43> B
CT635 1 2 0.22U_0201_10V6M TBT_2_TRX_C_RD_DTX_N0 G2 G11 TBT_2_TTX_RD_DRX_N0 RT1345 1 TypeC@ 2 2.2_0201_1% TBT_2_TTX_R_DRX_N0 CT636 1 2 0.22U_0201_25V6K TypeC@
'0' - Set Re-timer to be Slave on shared flash SPI I/F. <6> TBT_2_TRX_DTX_N0 ASSTXn1 BSSTXn1 TBT_2_TTX_C_DRX_N0 <43>
'1' - Set Re-timer to be Master on shared flash SPI I/F TypeC@ TypeC@
CT637 1 2 0.22U_0201_10V6M TBT_2_TTX_C_RD_DRX_P1 C1 C12 TBT_2_TRX_RD_DTX_P1 RT1346 1 TypeC@ 2 2.2_0201_1% TBT_2_TRX_R_DTX_P1 CT638 1 2 0.33U_0201_25V6K TypeC@
<6> TBT_2_TTX_DRX_P1 ASSRXp2 BSSRXp2 TBT_2_TRX_C_DTX_P1 <43>
<6> TBT_2_TTX_DRX_N1 CT639 1 2 0.22U_0201_10V6M TBT_2_TTX_C_RD_DRX_N1 C2 C11 TBT_2_TRX_RD_DTX_N1 RT1347 1 TypeC@ 2 2.2_0201_1% TBT_2_TRX_R_DTX_N1 CT640 1 2 0.33U_0201_25V6K TypeC@
ASSRXn2 BSSRXn2 TBT_2_TRX_C_DTX_N1 <43>
TypeC@ TypeC@
CT641 1 2 0.22U_0201_10V6M TBT_2_TRX_C_RD_DTX_P1 E1 E12 TBT_2_TTX_RD_DRX_P1 RT1348 1 TypeC@ 2 2.2_0201_1% TBT_2_TTX_R_DRX_P1 CT642 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_2_TRX_DTX_P1 ASSTXp2 BSSTXp2 TBT_2_TTX_C_DRX_P1 <43>
CT643 1 2 0.22U_0201_10V6M TBT_2_TRX_C_RD_DTX_N1 E2 E11 TBT_2_TTX_RD_DRX_N1 RT1349 1 TypeC@ 2 2.2_0201_1% TBT_2_TTX_R_DRX_N1 CT644 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_2_TRX_DTX_N1 ASSTXn2 BSSTXn2 TBT_2_TTX_C_DRX_N1 <43>
+3VS TypeC@
M7 M10 TBT_2_SBU1 RT1350 1 @ 2 0_0201_5% TBT_2_SBU1_R
DG0_POC_GPIO6 <6> TBT_2_LSX_TX PA_LSTX_SBU1 BSBU1 TBT_2_SBU1_R <43>
RT13511 TypeC@ 2 10K_0201_5% L7 L10 TBT_2_SBU2 RT1352 1 2 0_0201_5% TBT_2_SBU2_R

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%
@
<6> TBT_2_LSX_RX PA_LSRX_SBU2 BSBU2 TBT_2_SBU2_R <43>

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1
RT1353

RT1354

RT1355

RT1356

RT1357

RT1358

RT1359

RT1360
L8
<6> TBT_2_DP_AUXP_R PA_AUX_P
M8
<6> TBT_2_DP_AUXN_R PA_AUX_N
TBT_2_TTX_R_DRX_P0 1 2 TBT_2_TTX_R_DRX_P1 1 2
1

1
DT14 EMC@ DT15 EMC@
RT1361 RT1362 BURNSIDE-BRIDGE_BGA105
1M_0201_5% @ @ 1M_0201_5% @
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
2

AC coupling caps and PU/PD on AUX lines are TBT_2_TTX_R_DRX_N0 1 2 TBT_2_TTX_R_DRX_N1 1 2

implemented inside Burnside Bridge DT16 EMC@ DT17 EMC@

UT4C
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
B1 F12
B12 VSS_ANA VSS_ANA G7 TBT_2_TRX_R_DTX_P0 1 2 TBT_2_TRX_R_DTX_P1 1 2
D1 VSS_ANA VSS_ANA H1 DT18 EMC@ DT19 EMC@
D2 VSS_ANA VSS_ANA H2
D11 VSS_ANA VSS_ANA H11
D12
F1
VSS_ANA
VSS_ANA GND VSS_ANA
VSS_ANA
H12
J9
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2

F2 VSS_ANA VSS_ANA K1 TBT_2_TRX_R_DTX_N0 1 2 TBT_2_TRX_R_DTX_N1 1 2

F7 VSS_ANA VSS_ANA K2 DT20 EMC@ DT21 EMC@
20200811
F9 VSS_ANA VSS_ANA K11 - DT14~DT21 change to SC40000H800 for ESD
F11 VSS_ANA VSS_ANA K12
VSS_ANA VSS_ANA PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
G5
VSS F5
VSS F3
VSS Follow Burmside Bridge Rev0.84
BURNSIDE-BRIDGE_BGA105
change J5 pin to NC
C
@ Power Supply Decoupling of Type-C Port0 C

+3VO_TBT_2_ANA UT4B +3VS_TBT_2_RETIMER +0.9VO_TBT_2_SVR_IND +0.9VO_TBT_2_SVR

+3VO_TBT_2_LC LT33 +0.9VO_TBT_2_LVR +0.9VO_TBT_2_LC

L2 E6 0.9V@850mA
VCC3P3_ANA VCC3P3_SX 1 2
+0.9VO_TBT_2_SVR E5 M4
VCC3P3_LC VCC3P3_SVR +3VS_TBT_2_RETIMER_R

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

10U_0402_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
M5 0.68UH_DFE252012P-R68M-P2_3.5A_20%
VCC3P3_SVR

47U_0603_6.3V6M
CT645 TypeC@

47U_0603_6.3V6M
CT646 TypeC@

18P_0201_50V8J
F6 J5 TypeC@ 1 2 2 2 2 2 2 1 2 2
VCC0P9_SVR_ANA VCC3P3_SVR

1
+0.9VO_TBT_2_SVR_IND

C483 TypeC@

CT647 TypeC@

CT648 @

CT649 TypeC@

CT650 @

CT651 TypeC@

CT652 @

CT654 TypeC@

CT655 TypeC@
G6 J7
25M XTAL (Type-C Port0)

Pin F6

Pin G6

Pin E3

Pin G3

Pin E9

Pin G9

Pin L6

Pin J3
VCC0P9_SVR_ANA VCC3P3A

CT653
Power

E3 L1

2
VCC0P9_SVR SVR_IND 2 1 1 1 1 1 1 2 1 1

TypeC@
G3 M1
VCC0P9_SVR SVR_IND
DG0_XTAL_25M_XI E9 M2
+0.9VO_TBT_2_LC G9 VCC0P9_SVR_PB_ANA SVR_VSS M3
VCC0P9_SVR_PB_ANA SVR_VSS
YT3 TypeC@ DG0_XTAL_25M_XO +0.9VO_TBT_2_LVR J3
25MHZ 10PF EXS00A-CG03482 VCC0P9_LC +3VO_TBT_2_LC +3VO_TBT_2_ANA
L6 RT1419 +3VS_TBT_2_RETIMER
1 3 Must use Metal shielded crystal M6 VCC0P9_LVR J6 NC_J6_BB1 1 @ 2 0_0201_5%
1 3 VCC0P9_LVR_SENSE NC_J6

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
for better noise immunity.
GND GND
10P_0201_50V8J

10P_0201_50V8J

Suggest adding GND shield Share Same GND plane 2 2

Pin E5

Pin L2
CT656 TypeC@

CT657 TypeC@
BURNSIDE-BRIDGE_BGA105 @
C484 TypeC@

C485 TypeC@

2 4 across Crystal and 18pF caps

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
1 1 for better RFI. and connect to M2 & M3

47U_0603_6.3V6M
2 2

1
1 1

CT658 TypeC@

CT659 TypeC@

CT660 TypeC@
pins (SVR_VSS) of BB

Pin M4

Pin J5

Pin E6
2 2

2
1 1

Rev0.2 change from 18P to 10P

+3VALW +3VS_TBT_2_RETIMER +3VS_TBT_2_RETIMER_R

JTAG (Type-C Port0) SPI ROM (Type-C Port0)
1 RT1365 2 @ 1 0_0402_5% 3.3V@50mA
+3VO_TBT_2_LC CT661

10U_0402_6.3V6M

2.2U_0201_6.3V6M
2.2U_0201_6.3V6M

18P_0201_50V8J
TypeC@ Follow Burmside Bridge
2 All 0201 decoupling caps should be places 1 2 1

CT663 TypeC@

CT664 TypeC@
D Ref Schematic D

Pin J7

Pin J7
2

CT662
TypeC@ RT1366

TypeC@ RT1367

TypeC@ RT1368

TypeC@ RT1369

as close as possible to
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

UT35 @
DG0_SPI_CS# RT1370 1 @ 2 0_0201_5% DG0_SPI_CS#_R 1 8
DG0_SPI_DO 2 0_0201_5% DG0_SPI_DO_R CS# VCC DG0_SPI_HOLD# 2 1 2
RT1371 1 @
DG0_SPI_W P#
2
3 DO(IO1) HOLD#(IO3)
7
6 DG0_SPI_CLK_R1 RT1372 1 @ 2 0_0201_5% DG0_SPI_CLK_R the re-timer power pins Place holder for RC filter to reduce
ripple to VCC3v3A pin
4 WP#(IO2) CLK 5 DG0_SPI_DI_R RT1373 1 @ 2 0_0201_5% DG0_SPI_DI
1

GND DI(IO0)
W 25Q80DVSSIG_SO8
DG0_JTAG_TDI +3VALW
TypeC@
DG0_JTAG_TMS
DG0_JTAG_TCK SA0000B8720
DG0_JTAG_TDO DG0_SPI_CS# RT13741 TypeC@ 2 2.2K_0201_5%
DG0_SPI_DO RT13751 TypeC@ 2 2.2K_0201_5%
remove connector 2/14 DG0_SPI_W P# RT13761 TypeC@ 2 3.3K_0201_5% Security Classification Compal Secret Data Compal Electronics, Inc.
DG0_SPI_HOLD# RT13771 TypeC@ 2 3.3K_0201_5% 2020/07/20 2021/07/20 Title
Issued Date Deciphered Date

DG0_SPI_CLK_R1 1 XEMC@ 2
XEMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (1/2)
2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

EMI RT1378 33_0201_5% CT665 22P_0201_50V8J DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
HH67A MB LA-M241P
Friday, December 24, 2021 Sheet 42 of 112
0.1

1 2 3 4 5
 5 4 3 2 1

+20V_VIN_TYPEC_0 +5V_IN_PW R_PD1 Slave Adderss setting

VBUS Discharge Local PWR Voltage Monitor VBUS Voltage/current Monitor+20V_VIN_TYPEC_0 +3V_TBT2_PDLDO
+3V_TBT2_PDLDO +3VLP
addr3:0xCa

1
EC_PD1_INT# RT1160 2 @ 1 10K_0201_5%
RT69 RT1168 RT1166
200K_0402_1% 200K_0402_1% Slave Addr Ra 5% Rb 5% RT22

82P_0402_50V8J
10U_0402_6.3V6M

0.1U_0201_25V6K
4.7K_0805_5%
10K_0402_5% RF@ 1 RF@ 1 RF@ 1
addr0:0xC4 NC 10K <0.2V

CT52

CT53

CT54
2

2
PD1_LOC_PW R_MON PD1_VMON addr1:0xC6 75K 10K >=0.2V&&<0.6V PD1_ADDR_CFG
addr2:0xC8 33K 10K >=0.6V&&<1.0V

1
D 2 2 2
PD1_VBUS_DSCHG 2 QT1 RT1169 RT1167 addr3:0xCa 10K 10K >=1.0V RT1165
G L2N7002W T1G_SC-70-3 10K_0402_1% 10K_0402_1% 10K_0402_1%
S 20200811

3
It's is used for SMBUS slave addr0/1/2/3
setting during power on initialization. - Remove TYPEC_IN_STATUS# (RT1159)

2
D PD1 +20V_VIN_TYPEC_0_L EMC Suggestion +20V_VIN_TYPEC_0 D
UT14 SA0000DUO10
need check TI (ref sch 330p)
RTS5452E-GR QFN 32P TYPE-C PD CTRL LT34 EMC@
RT1170 POP: Disable Dead battery function 5A_Z80_0805_2P
PD1_ADDR_CFG 20 19 RT1170 1 @ 2 0_0402_5% EC_I2C_3_SCL 1 2
+3V_TBT2_PDLDO ADDR_CFG /MGPIO11 DB_DIS EC_I2C_3_SDA
PD1_LOC_PW R_MON 23 +TBT_2_PD_CC1 1 2
LOC_PWR_MON/MGPIO10 2

2
PD1_MGPIO2 RT3986 1 @ 2 4.7K_0201_5% LT35 EMC@
PD1_MGPIO3 RT3987 1 2 4.7K_0201_5% PD1_VMON 21 16 +TBT_2_PD_CC1

EMC@

EMC@
@ CT37 5A_Z80_0805_2P

1000P_0201_50V7K
VMON/MGPIO9 PD CU CC1 18 +TBT_2_PD_CC2

EMC@

EMC@
100P_0201_50V8J

100P_0201_50V8J
0.1U_0201_25V6K
220P_0201_25V7K
PD1_MGPIO6 RT3988 1 @ 2 4.7K_0201_5% PD1_MGPIO8 22 CC2 1 @ DVE11
IMON/MGPIO8 1 1 1 1
PD1_MGPIO7 RT3989 1 @ 2 4.7K_0201_5% YSLC05CH_SOT23-3
PD1_MGPIO8 RT3990 1 @ 2 4.7K_0402_5%

CT670

CT671
0_0402_5% 1 2 PD1_USB2_SRC_HI_ILIM_R_PD 8 10 PD1_MGPIO6 2 2 2 2

CT672

CT673
RT1183 @
<50,59> PD1_USB2_SRC_HI_ILIM SOC_DG_BB_FORCE_PW R_R_PD1 AUX_P/ MGPIO4 SBU1/MGPIO6 PD1_MGPIO7 +TBT_2_PD_CC2
RT1185 0_0402_5% 1 @ 2 9 11
<13,42,44,45,46> SOC_DG_BB_FORCE_PW R_R AUX MUX 2

1
AUX_N/ MGPIO5 SBU2/MGPIO7 EC_PD1_INT#
PD1_MGPIO2 RT3994 1 @ 2 4.7K_0201_5% RT104 0_0201_5% 2 @ 1 PD1_R_PROCHOT# 32 CT38
PD1_MGPIO3 RT3995 1 @ 2 4.7K_0201_5% <7,17,46> VCCIN_AUX_CORE_ALERT#_R HPD/GPIO3 I2C3_PD1_R_CLK_R
220P_0201_25V7K
1 I2C3_PD1_R_DAT_R
PD1_MGPIO6 RT3996 1 @ 2 4.7K_0201_5%

2
PD1_MGPIO7 RT3997 1 @ 2 4.7K_0201_5%
PD1_MGPIO8 RT3998 1 @ 2 4.7K_0402_5%

PD1_MGPIO2 12 14 @ DVE13
H_DP/MGPIO2 USB2.0 SWITCH C_DP/MGPIO0 TYPE-C_20V_0_VIN_EN <83>

1
+3V_TBT2_PDLDO PD1_MGPIO3 13 15 PD1_VBUS_DSCHG YSLC05CH_SOT23-3
H_DM/MGPIO3 C_DM/MGPIO1 RT1171
100K_0402_5%

4.7K_0402_5% 2 1 RT1149 EC_I2C_3_SCL

1
4.7K_0402_5% 2 1 RT1150 EC_I2C_3_SDA I2C3_PD1_R_INT#_R
10K_0201_5% 2 1 RT1151 EC_PD1_INT#
EC_I2C_3_SCL 3
EC BBR 4 I2C3_PD1_R_CLK_R
I2C1(Slave) to EC <46,58> EC_I2C_3_SCL EC_I2C_3_SDA 30 SMBUS1_SCL/GPIO5 I2C_M_SCL/GPIO13 5 I2C3_PD1_R_DAT_R 20200819 - Add for TI Kit Debug +5VLP
<46,58> EC_I2C_3_SDA EC_PD1_INT# 31 SMBUS1_SDA/GPIO6 I2C_M_SDA/GPIO14 29 I2C3_PD1_R_INT#_R I2C3(Master) to BB
4.7K_0402_5% 2 1 RT1152 PD1_I2C_2_SCL 20200722 <58> EC_PD1_INT# SMBUS1_INT/GPIO4 I2C_M_INT/GPIO8 RT1180
4.7K_0402_5% 2 1 RT1153 PD1_I2C_2_SDA - Need confirm with EC 1 @ 2 0_0402_5%
10K_0201_5% 2 1 RT1154 PD1_INT#_R +5V_IN_PW R_PD1
PD1_DG0_RST#_R 7
PCH 1 PD1_I2C_2_SCL Dead Battery circuit +5VALW
EN_USB2_5V_OUT# 27 SMBUS2_SCL/GPIO9 GPIOs I2C_S_SCL/GPIO11 2 PD1_I2C_2_SDA
I2C2(Slave) to PCH +20V_VIN_TYPEC_0 RT1178 DT28
<50> EN_USB2_5V_OUT# TBT_2_RETIMER_LS_EN 6 SMBUS2_SDA/GPIO10 I2C_S_SDA/GPIO12 28 PD1_INT#_R 1 @ 2 0_0402_5% 2 1
4.7K_0402_5% 1 2 RT96 I2C3_PD1_R_CLK_R <42> TBT_2_RETIMER_LS_EN SMBUS2_INT/GPIO7 I2C_S_INT/GPIO21 SA00008FS00
C I2C3_PD1_R_DAT_R C
4.7K_0402_5% 1 2 RT97 RT9069-50GB_SOT23-5 RB751S-40_SOD523-2
10K_0201_5% 2 1 RT98 I2C3_PD1_R_INT#_R UT46 DBLDO@ DT27
1 5 2 1
VCC OUT

10U_0603_25V6M
20200806 K Power

1
24 2 RB751S-40_SOD523-2
- INT# pull up from 2.2k to 10k ohm REXT GND

CT145
1
3 4

VCONN_IN

2
RT1164 33 NC EN +20V_VIN_TYPEC_0

LDO_3V3
0_0201_5% 2 1 RT108 PD1_R_PROCHOT# EPAD
change from r-short to 0ohm 6.2K_0402_1%

5V_IN
100K_0201_5% 2 1 RT1161 PD1_DG0_RST#_R RT4061 2 1 0_0201_5%

2
DBLDO@
100K_0201_5% 2 1 RT1184 TBT_2_RETIMER_LS_EN +3V_TBT2_PDLDO

17

25

26
+5VLP +5VALW DBLDO@
RT105 2 1 0_0201_5% 1.0 add 0 ohm on pin3 and pin4 for 2nd source 75K_0201_5% 1 2 RT1206
+5VALW
1.0 add diode for leakage 20210914 change to @

1
+3VS_TBT_2_RETIMER @ RT300 2 @ 1 0_0402_5% D
1 1
2 1 PD1_DG0_RST#_R +5V_IN_PW R_PD1 CT47 CT536 RT375 RT1207 2 DBLDO@1 75K_0201_5% 2
<42> PD1_DG0_RST# @ 0.1U_0201_10V6K 4.7U_0402_6.3V6M 47K_0402_5% G

2
DT29 SCS00006300 RB751S-40_SOD523-2 RT4053 1 2 0_0402_5% QT29 S

3
2 2 RT4059 0_0201_5% 2 @ 1 RT1208
1 1 CT568 L2N7002W T1G_SC-70-3

2
PD1_DG0_RST# <46,87,88> 5V_3V_EN
100K_0201_5% 2 @ 1 RT1131 1.0 pop RT4034 and change net name CT46 1 1 100K_0201_5% 1U_0201_6.3V6M DBLDO@
from PD1_DG0_RST#_R to PD1_DG0_RST# for leakage 10U_0402_6.3V6M CT535 CT534 RT4063 0_0201_5% 2 @ 1 DBLDO@ DBLDO@
<11,46,58,87,88> SPOK_5V
0.1U_0201_10V6K 10U_0402_6.3V6M

1
2 2
+5VALW 2 2 +3VS_TBT_2_RETIMER
CC/SBU OVP +3VALW +3VS_TBT_2_RETIMER

1
@ @
2

2
TypeC@ RT4055 RT4051 @
G

G
1

QT14A 2.2K_0402_5% 2.2K_0402_5% QT19A

RT3999 2N7002KDW _SOT363-6 2N7002KDW _SOT363-6
1

470_0201_5% +5V_IN_PW R_PD1 +3V_TBT2_PDLDO

2
TBTNOVP@ RT4000 SOC_SML1DATA 1 6 PD1_I2C_2_SDA I2C3_PD1_R_DAT 1 6 I2C3_PD1_R_DAT_R DT22
S

S
<9,46> SOC_SML1DATA <42> I2C3_PD1_R_DAT
D

D
470_0201_5% TBT_2_SBU1_R_SW 1 1 10 9 TBT_2_SBU1_R_SW
2

TBTNOVP@
5

TypeC@ 1 @ 2 RT1179 1 2 0_0402_5% +TBT_2_PD_CC1_SW 2 2 9 8 +TBT_2_PD_CC1_SW

G
2

QT14B RT1187 0_0402_5%

5
20200904 2N7002KDW _SOT363-6 @ PD_3V@ TBT_2_SBU2_R_SW 4 4 7 7 TBT_2_SBU2_R_SW

G
5

TBTNOVP@ QT19B
G

B - UT5/UT6(single) change to QT10(2N2002KDW) for COST . SOC_SML1CLK PD1_I2C_2_SCL I2C3_PD1_R_CLK +TBT_2_PD_CC2_SW 5 5 +TBT_2_PD_CC2_SW
B
QT20B 4 3 2N7002KDW _SOT363-6 Note: 6 6
S

<9,46> SOC_SML1CLK <42> I2C3_PD1_R_CLK

D

2N7002KDW _SOT363-6 1.If the 5V_IN power supply

2

TBTNOVP@ +3VALW +3VS_TBT_2_RETIMER 4 3 I2C3_PD1_R_CLK_R 3 3

G

voltage is fixed 5V or

D
TBT_2_SBU1_R 4 3 TBT_2_SBU1_R_SW QT20A variable
S

2N7002KDW _SOT363-6 from 3.3V to 5V. Remove the 8 EMC@

2

1
G

@ +3VS_TBT_2_RETIMER 1 @ 2
+5VALW TBT_2_SBU2_R 1 6 TBT_2_SBU2_R_SW 0ohm resistor.
RT4054 RT1186 0_0402_5% AZ1045-04F_DFN2510P10E-10-9
S

SOC_PD_INT# PD1_INT#_R 2.If the 5V_IN power supply

D

3 1 2.2K_0402_5% @ SC300001Y00
<11,46> SOC_PD_INT# voltage is fixed 3.3V, stuff

2
G
QT15
S

2 L2N7002W T1G_SC-70-3 the 0ohm resistor.

TypeC@ QT12 I2C3_PD1_R_INT# 3 1 I2C3_PD1_R_INT#_R
<42> I2C3_PD1_R_INT#
L2N7002W T1G_SC-70-3

D
1

RT1204 +20V_VIN_TYPEC_0_L 1 @ 2
1

470_0201_5% RT1188
@ RT1205 0_0402_5%
470_0201_5%
1000P_0201_50V7K

W = 200 mils
2

@ 0520 Remove EMI 0 ohm

0.1U_0201_25V6K
0.022U_0402_25V7K

1 1 1 DT23
2

CT692

CEST23NC24VU_SOT23-3 LT36 EMC@

Need check pin define USB20_P2 1 2 USB20_P2_R
CT693

CT694

EMC@
<13> USB20_P2 1 2
5

QT22A @
PJT138KA 2N SOT363-6 2 2 2
G

1
2

+TBT_2_PD_CC2 4 3 +TBT_2_PD_CC2_SW EMC@ EMC@ JTYPEC2 USB20_N2 4 3 USB20_N2_R

<13> USB20_N2 4 3
A1 B12
S

+TBT_2_PD_CC1 1 6 +TBT_2_PD_CC1_SW EMC@ GND_A1 GND_B12 DLM0NSN900HY2D_4P

TBT_2_TTX_C_DRX_P0 A2 B11 TBT_2_TRX_C_DTX_P0
S

TBT_2_TRX_C_DTX_P0 <42> SM070005U00

<42> TBT_2_TTX_C_DRX_P0 TBT_2_TTX_C_DRX_N0 SSTXP1 SSRXP1 TBT_2_TRX_C_DTX_N0
A3 B10
QT22B <42> TBT_2_TTX_C_DRX_N0 SSTXN1 SSRXN1 TBT_2_TRX_C_DTX_N0 <42>
@
PJT138KA 2N SOT363-6 0.1U_0201_25V6K 1 2 CT695 A4 B9 CT696 1 2 0.1U_0201_25V6K
TBTNOVP@ VBUS_A4 VBUS_B9
+TBT_2_PD_CC1 0_0402_5% 2 1 RT76 +TBT_2_PD_CC1_SW +TBT_2_PD_CC1_SW A5 B8 TBT_2_SBU2_R_SW
TBTNOVP@ CC1 SBU2
20200924A
+TBT_2_PD_CC2 0_0402_5% 2 1 RT77 +TBT_2_PD_CC2_SW USB20_P2_R A6 B7 USB20_N2_R
USB20_N2_R DP1 DN2 USB20_P2_R
- DT11 USB2 P/N Swap
A7 B6 EMC@
DN1 DP2 DT24
+3V_TBT2_PDLDO TBT_2_SBU1_R_SW A8 B5 +TBT_2_PD_CC2_SW USB20_N2_R 1 1 10 9 USB20_N2_R
Bottom

SBU1 CC2
TOP

UT15 0.1U_0201_25V6K 1 2 CT697 A9 B4 CT698 1 2 0.1U_0201_25V6K USB20_P2_R 2 2 9 8 USB20_P2_R

10 3 CT565 1 2 0.1U_0201_25V6K VBUS_A9 VBUS_B4
VPWR VBIAS TBT_2_TRX_C_DTX_N1 A10 B3 TBT_2_TTX_C_DRX_N1 4 4
1 TBTOVP@ <42> TBT_2_TRX_C_DTX_N1 TBT_2_TTX_C_DRX_N1 <42> 7 7
A CT566 TBT_2_SBU1_R 15 1 TBT_2_SBU1_R_SW TBT_2_TRX_C_DTX_P1 A11 SSRXN2 SSTXN2 B2 TBT_2_TTX_C_DRX_P1 A
TBT_2_SBU2_R SBU1 C_SBU1 TBT_2_SBU2_R_SW <42> TBT_2_TRX_C_DTX_P1 SSRXP2 SSTXP2 TBT_2_TTX_C_DRX_P1 <42>
14 2 5 5 6 6
1U_0201_6.3V6M SBU2 C_SBU2 A12 B1
TBTOVP@ 2 4 +TBT_2_PD_CC1_SW GND_A12 GND_B1 3 3
+TBT_2_PD_CC1
+TBT_2_PD_CC2
12
11 CC1
CC2
C_CC1
C_CC2
5 +TBT_2_PD_CC2_SW
1
GND1 GND4
4
Double 8
7 RT1203 2 @ 1 +TBT_2_PD_CC1_SW
0_0402_5% TBT_2_SBU1_R
RPD_G1 +TBT_2_PD_CC2_SW <42> TBT_2_SBU1_R TBT_2_SBU2_R
2 1 9 6 RT1202 2 @ 1 0_0402_5% 2 3
+3V_TBT2_PDLDO FLT RPD_G2 <42> TBT_2_SBU2_R GND2 GND3 AZ1045-04F_DFN2510P10E-10-9
100K_0201_5% TBTOVP@RT1201
6 5 SC300001Y00
NC1 NC2
1

20
8 D1 19 RT1415 RT1416 LOTES_AUSB0528-P306A
13 GND D2 16 1M_0201_5% 1M_0201_5% CONN@
18
21
GND
GND
N.C.
N.C.
17 TypeC@ TypeC@ Security Classification
20200901
Compal Secret Data
2021/09/01
Compal Electronics, Inc.
20200917 Issued Date Deciphered Date Title
2

THERMAL_PAD
TPD6S300ARUKR_W QFN20_3X3 - Update SYMBOL/Footprint
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (2/2)
TBTOVP@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L151P
Date: Friday, December 24, 2021 Sheet 43 of 102
5 4 3 2 1
 1 2 3 4 5

+3VS_RETIMER_0 Tolerance (+ 5%/-7.5%):

TBT Conn. (Port 0/ Re-Timer1) UT2

+3VALW Burnside Bridge power pins which connected to +3VS_RETIMER_0 should
be 3.465v maximum and 3.07v minimum for normal operation.
+3VS_RETIMER_0 ripple: 40mVp-p +3VS_TBT_0_RETIMER
Delete FIP@ Part

1U_0201_6.3V6M
1

CT1
10/23 UT1 1 TypeC@
remove SOC_DG_BB_FORCE_PWR_R PU(unpop)、PD (pop)path 5 1 CT2
keep on p.42 @ IN OUT 4.7U_0402_6.3V6M
S IC JHL8040R SLMN7 A1 THUNDERBOLT ABO ! 2 2
TypeC@ GND 2
SA0000CAH60 4 3
RT6 1 TypeC@ 2 100_0201_1% TBT_0_DG0_TEST_PW R_GOOD EN OC
RT12 1 @ 2 0_0201_5% TBT_0_RETIMER_LS_EN_R SY6288C20AAC_SOT23-5
TBT_0_DG0_POC_GPIO5 <46> TBT_0_RETIMER_LS_EN +3VS_TBT_0_RETIMER
RT7 1 TypeC@ 2 10K_0201_5%
RT13 1 2 0_0201_5%
SA000079400
@ High active
UT2A BB2 <12> SOC_SLP_DS0#
EN_VL:1.1V TypeC@ RT14 1 @ 2 10K_0201_5%

TBT_0_DG0_SPI_DI C6 C9 TBT_0_BBR0_I2C_SCL RT8 2 @ 1 0_0201_5%

A +3VS_TBT_0_RETIMER TBT_0_DG0_SPI_DO EE_DI I2C_SCL TBT_0_BBR0_I2C_SDA I2C3_PD2_R_CLK <45,46> A
B4 E7 RT9 2 @ 1 0_0201_5% I (Max) : 0.37 A(+3V_PRIM)

FLASH
Change DG0_FLSH_SHARE_EN to PD TBT_0_DG0_SPI_CS# B6 EE_DO I2C_SDA A10 TBT_0_BBR0_I2C_INT# RT84 2 @ 1 0_0201_5%
I2C3_PD2_R_DAT
I2C3_PD2_R_INT#
<45,46>
<45,46>
I2C(slave) from PD2 RDS(Typ) : 70 mohm
TBT_0_DG0_SPI_CLK_R 1 @ 2 TBT_0_DG0_SPI_CLK C7 EE_CS# I2C_INT B10 SOC_DG_BB_FORCE_PW R_R
Delete DG0_FLSH_MSTR_SLV 1/7 RT1181 0_0201_5% EE_CLK FORCE_PWR A9 TBT_0_DG0_FLASH_BUSY# SOC_DG_BB_FORCE_PW R_R <13,42,43,45,46> V drop : 0.026 V

POC GPIO
RT11 1 @ 2 10K_0201_5% TBT_0_DG0_FLSH_SHARE_EN EMC Suggestion
TBT_0_DG0_JTAG_TDI
MISC & FLASH_BUSY#
POC_GPIO_5
POC_GPIO_6
B9
A8
TBT_0_DG0_POC_GPIO5
TBT_0_DG0_POC_GPIO6
TBT_RETIMER_RESET#_R0
RT10 1 TypeC@ 2 10K_0201_5%
TBT_0_DG0_JTAG_TMS
TBT_0_DG0_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
RT2_SML0CLK
RT2_SML0DATA
RT1 2 @ 1 0_0201_5%
RT299 1 VPRO@ 2 0_0201_5%
RT298 1 VPRO@ 2 0_0201_5%
PLT_RST_R# <11,26,42,45,51,53,66,68,69,70>
SOC_SML0CLK <9,42,45>
+3VS_TBT_0_RETIMER

SML0 from PCH

JTAG
TBT_0_DG0_FLSH_MSTR_SLV TBT_0_DG0_JTAG_TDO TCK SMBUS_SDA TBT_0_DG0_FLSH_SHARE_EN SOC_SML0DATA <9,42,45> TBT_RETIMER_RESET#_R0
RT15 1 @ 2 10K_0201_5% C5 A4 RT42 2 1 10K_0201_5%
TDO POC_GPIO_10 TBT_0_DG0_FLSH_MSTR_SLV <45> TBT_RETIMER_RESET#_R0
RT1144 1 @ 2 10K_0201_5% A5 Reserved v-pro only RT43 2 @ 1 10K_0201_5%
RT17 1 @ 2 10K_0201_5% TBT_0_DG0_POC_GPIO12 POC_GPIO_11 A6 TBT_0_DG0_POC_GPIO12
POC_GPIO_12 & PU at CPU side
RT1145 1 @ 2 10K_0201_5% L3
1TBT_0_AN0_THERMDA M11 NC_L3
TBT_0_DG0_SPI_CLK_R T143 TP@ THERMDA
CT131 2 1 10P_0201_50V8J DG2_RST# need to be output from PD
M12 controller to reset BBR main power NVPRO@
XEMC@ B2 TEST_EDM RT2_SML0CLK RT94 2 1 100K_0201_5%
EMC Suggestion FUSE_VQPS_64 L11 PD2_DG0_RST# RT2_SML0DATA RT95 2 1 100K_0201_5%
+3VALW RESET# PD2_DG0_RST# <45,46>
A11 NVPRO@
A12 MONDC L9 TBT_0_DG0_XTAL_25M_XI
Follow E team design PD 100K

DEBUG

Main
RT19 1 TypeC@ 2 10K_0201_5% TBT_0_DG0_FLASH_BUSY# L12 NC_A12 XTAL_25_IN M9 TBT_0_DG0_XTAL_25M_XO
MONDC_SVR XTAL_25_OUT
Delete Port1 Share Rom Part 1/7 TBT_0_DG0_TEST_PW R_GOOD B3 L5 TBT_0_AN2_RSENSE
B11 TEST_PWR_GOOD
TEST_EN
RSENSE
RBIAS
L4 TBT_0_AN2_RBIAS 1 2 SMBUS:
A1
RT21 TypeC@
4.75K_0201_0.5%
No support Vpro
A2 ATEST_P
ATEST_N
Intel recommended PD 100K NOTE:
DG1_RST#: Re-Timer with TBT , AC Caps should be use 0201/25V package.
For PD based systems, DG1_RST# should be output from PD.
For TCPC based systems, DG1_RST# should be output from SOC/EC. Re-Timer without TBT , AC Caps can be use 0402/25V package.
BURNSIDE-BRIDGE_BGA105 For non-PD support 25V rating is no must.
DG1_BB_FORCE_PWR: @
Connect to EC/PCH for FW update
'0' - by default
'1' - for debug only

DG1_FLASH_BUSY#: UT2D
If Flash sharing is being used, PU should be used.
20200813 RT1 Remove 2.2ohm
If Flash sharing isn't being used, PD should be used.

DG1_FLSH_SHARE_EN: <6> TBT_0_TTX_DRX_P0 CT11

TypeC@
1 2 0.22U_0201_10V6M TBT_0_TTX_C_DRX_P0 J1
TBT PORTS J12 TBT_0_TRX_RD1_DTX_P0 CT12 1 2 0.22U_0201_25V6K TypeC@
TBT_0_TRX_RD1_C_DTX_P0 <45>
'0' - Flash isn't shared. 1 Flash per Re-timer CT13 1 2 0.22U_0201_10V6M TBT_0_TTX_C_DRX_N0 J2 ASSRXp1 BSSRXp1 J11 TBT_0_TRX_RD1_DTX_N0 CT14 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TTX_DRX_N0 ASSRXn1 BSSRXn1 TBT_0_TRX_RD1_C_DTX_N0 <45>
'1' - Flash is shared between 2 Re-timers TypeC@ TypeC@

Port B - TypeC Side

CT15 1 2 0.22U_0201_10V6M TBT_0_TRX_C_DTX_P0 G1 G12 TBT_0_TTX_RD1_DRX_P0 CT16 1 2 0.22U_0201_25V6K TypeC@

Port A - Host Side

B DG1_FLSH_MSTR_SLV: <6> TBT_0_TRX_DTX_P0 ASSTXp1 BSSTXp1 TBT_0_TTX_RD1_C_DRX_P0 <45> B
CT17 1 2 0.22U_0201_10V6M TBT_0_TRX_C_DTX_N0 G2 G11 TBT_0_TTX_RD1_DRX_N0 CT18 1 2 0.22U_0201_25V6K TypeC@
'0' - Set Re-timer to be Slave on shared flash SPI I/F. <6> TBT_0_TRX_DTX_N0 ASSTXn1 BSSTXn1 TBT_0_TTX_RD1_C_DRX_N0 <45>
'1' - Set Re-timer to be Master on shared flash SPI I/F TypeC@ TypeC@
CT3 1 2 0.22U_0201_10V6M TBT_0_TTX_C_DRX_P1 C1 C12 TBT_0_TRX_RD1_DTX_P1 CT4 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TTX_DRX_P1 ASSRXp2 BSSRXp2 TBT_0_TRX_RD1_C_DTX_P1 <45>
<6> TBT_0_TTX_DRX_N1 CT5 1 2 0.22U_0201_10V6M TBT_0_TTX_C_DRX_N1 C2 C11 TBT_0_TRX_RD1_DTX_N1 CT6 1 2 0.22U_0201_25V6K TypeC@
ASSRXn2 BSSRXn2 TBT_0_TRX_RD1_C_DTX_N1 <45>
TypeC@ TypeC@
CT7 1 2 0.22U_0201_10V6M TBT_0_TRX_C_DTX_P1 E1 E12 TBT_0_TTX_RD1_DRX_P1 CT8 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TRX_DTX_P1 ASSTXp2 BSSTXp2 TBT_0_TTX_RD1_C_DRX_P1 <45>
CT9 1 2 0.22U_0201_10V6M TBT_0_TRX_C_DTX_N1 E2 E11 TBT_0_TTX_RD1_DRX_N1 CT10 1 2 0.22U_0201_25V6K TypeC@
<6> TBT_0_TRX_DTX_N1 ASSTXn2 BSSTXn2 TBT_0_TTX_RD1_C_DRX_N1 <45>
+3VS TypeC@
M7 M10 TBT_0_RD1_SBU1 RT31 1 TypeC@ 2 0_0201_5% TBT_0_RD1_SBU1_R 20200813 RT1 Remove 220K PD RB
TBT_0_DG0_POC_GPIO6 <6> TBT_0_LSX_TX PA_LSTX_SBU1 BSBU1 TBT_0_RD1_SBU1_R <45>
RT32 1 TypeC@ 2 10K_0201_5% L7 L10 TBT_0_RD1_SBU2 RT33 1 TypeC@ 2 0_0201_5% TBT_0_RD1_SBU2_R
<6> TBT_0_LSX_RX PA_LSRX_SBU2 BSBU2 TBT_0_RD1_SBU2_R <45>
L8
<6> TBT_0_DP_AUXP_R PA_AUX_P
M8
<6> TBT_0_DP_AUXN_R PA_AUX_N
1

1
RT44 RT45 BURNSIDE-BRIDGE_BGA105
1M_0201_5% @ @ 1M_0201_5% @
2

AC coupling caps and PU/PD on AUX lines are

implemented inside Burnside Bridge
UT2C

B1 F12
B12 VSS_ANA VSS_ANA G7
D1 VSS_ANA VSS_ANA H1
D2 VSS_ANA VSS_ANA H2
D11 VSS_ANA VSS_ANA H11
D12
F1
VSS_ANA
VSS_ANA GND VSS_ANA
VSS_ANA
H12
J9
F2 VSS_ANA VSS_ANA K1
F7 VSS_ANA VSS_ANA K2
F9 VSS_ANA VSS_ANA K11
F11 VSS_ANA VSS_ANA K12
VSS_ANA VSS_ANA
G5
VSS F5
VSS F3
VSS Follow Burmside Bridge Rev0.84
BURNSIDE-BRIDGE_BGA105
change J5 pin to NC
C
@ Power Supply Decoupling of Type-C Port0 C

+3VO_TBT_0_RD1_ANA UT2B +3VS_TBT_0_RETIMER +0.9VO_TBT_0_RD1_SVR_IND +0.9VO_TBT_0_RD1_SVR

+3VO_TBT_0_RD1_LC LT1 +0.9VO_TBT_0_RD1_LVR +0.9VO_TBT_0_RD1_LC

L2 E6 0.9V@850mA
VCC3P3_ANA VCC3P3_SX 1 2
+0.9VO_TBT_0_RD1_SVR E5 M4
VCC3P3_LC VCC3P3_SVR +3VS_TBT_0_RETIMER

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

10U_0402_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
M5 0.68UH_DFE252012P-R68M-P2_3.5A_20%
VCC3P3_SVR

47U_0603_6.3V6M
CT235 TypeC@

47U_0603_6.3V6M
CT19 TypeC@

18P_0201_50V8J
F6 J5 TypeC@ 1 2 2 2 2 2 2 1 2 2
VCC0P9_SVR_ANA VCC3P3_SVR

1
+0.9VO_TBT_0_RD1_SVR_IND

C55

CT20 TypeC@

CT21 @

CT22 TypeC@

CT23 @

CT24 TypeC@

CT25 @

CT27 TypeC@

CT28 TypeC@
G6 J7
25M XTAL (Type-C Port0)

Pin F6

Pin G6

Pin E3

Pin G3

Pin E9

Pin G9

Pin L6

Pin J3
VCC0P9_SVR_ANA VCC3P3A

CT26TypeC@
Power

E3 L1

2
VCC0P9_SVR SVR_IND 2 1 1 1 1 1 1 2 1 1

TypeC@
G3 M1
+0.9VO_TBT_0_RD1_LVR VCC0P9_SVR SVR_IND
TBT_0_DG0_XTAL_25M_XI E9 M2
+0.9VO_TBT_0_RD1_LC G9 VCC0P9_SVR_PB_ANA SVR_VSS M3
TBT_0_DG0_XTAL_25M_XO VCC0P9_SVR_PB_ANA SVR_VSS
YT1 TypeC@ J3
25MHZ 10PF EXS00A-CG03482 VCC0P9_LC +3VO_TBT_0_RD1_LC +3VO_TBT_0_RD1_ANA
L6 RT1196 +3VS_TBT_0_RETIMER
1 3 Must use Metal shielded crystal M6 VCC0P9_LVR J6 NC_J6_BB2 1 @ 2 0_0201_5%
1 3 VCC0P9_LVR_SENSE NC_J6

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
for better noise immunity.
GND GND
10P_0201_50V8J

10P_0201_50V8J

Suggest adding GND shield Share Same GND plane 2 2

Pin E5

Pin L2
CT29 TypeC@

CT30 TypeC@
BURNSIDE-BRIDGE_BGA105 @
C56 TypeC@

C57 TypeC@

2 4 across Crystal and 18pF caps

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
1 1 for better RFI. and connect to M2 & M3

47U_0603_6.3V6M
2 2

1
1 1

CT31 TypeC@

CT32 TypeC@

CT33 TypeC@
pins (SVR_VSS) of BB

Pin M4

Pin J5

Pin E6
2 2

2
1 1

Rev0.2 change from 18P to 10P Rev0.2 remove RT60 and

change 3VS_TBT_2_RETIMER_R
to +3VS_TBT_2_RETIMER
+3VALW +3VS_TBT_0_RETIMER
JTAG (Type-C Port0) SPI ROM (Type-C Port0) 3.3V@50mA
1
+3VO_TBT_0_RD1_LC CT34

10U_0402_6.3V6M

2.2U_0201_6.3V6M
2.2U_0201_6.3V6M

18P_0201_50V8J
20210316 TypeC@ Follow Burmside Bridge
2 All 0201 decoupling caps should be places 1 2 1

CT36 TypeC@

CT530 TypeC@
D change from 0 ohm to R-short Ref Schematic D

Pin J7

Pin J7
2

CT35
TypeC@ RT56

TypeC@ RT57

TypeC@ RT58

TypeC@ RT59

as close as possible to
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

UT3 20210316 @
TBT_0_DG0_SPI_CS# RT62 1 @ 2 0_0201_5% TBT_0_DG0_SPI_CS#_R 1 8
TBT_0_DG0_SPI_DO /CS VCC change from 0 ohm to R-short 2 1 2
2 0_0201_5% TBT_0_DG0_SPI_DO_R TBT_0_DG0_SPI_HOLD#
RT63 1 @
TBT_0_DG0_SPI_W P#
2
3 DO(IO1) /HOLD(IO3)
7
6 TBT_0_DG0_SPI_CLK_R1 RT64 1 @ 2 0_0201_5% TBT_0_DG0_SPI_CLK_R
the re-timer power pins Place holder for RC filter to reduce
ripple to VCC3v3A pin
4 /WP(IO2) CLK 5 TBT_0_DG0_SPI_DI_R RT65 1 @ 2 0_0201_5% TBT_0_DG0_SPI_DI
1

GND DI(IO0)
W 25Q80DVSNIG_SO8
TBT_0_DG0_JTAG_TDI +3VALW
TBT_0_DG0_JTAG_TMS SA0000BDR00
TBT_0_DG0_JTAG_TCK
TBT_0_DG0_JTAG_TDO TBT_0_DG0_SPI_CS# RT52 1 TypeC@ 2 2.2K_0201_5%
TBT_0_DG0_SPI_DO RT53 1 TypeC@ 2 2.2K_0201_5%
remove connector 2/14 TBT_0_DG0_SPI_W P# RT54 1 TypeC@ 2 3.3K_0201_5% Security Classification Compal Secret Data Compal Electronics, Inc.
TBT_0_DG0_SPI_HOLD# RT55 1 TypeC@ 2 3.3K_0201_5% 2019/09/20 2021/03/01 Title
Issued Date Deciphered Date

TBT_0_DG0_SPI_CLK_R1
XEMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (1/3)
1 XEMC@ 2 2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For EMI RT1182 33_0201_5% CT229 22P_0201_50V8J DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
HH67A MB LA-M241P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 24, 2021 Sheet 44 of 121
1 2 3 4 5
 1 2 3 4 5

TBT Conn. (Port 0/ Re-Timer2) UT7

10/23
remove SOC_DG_BB_FORCE_PWR_R PU(unpop)、PD (pop)path
keep on p.42
S IC JHL8040R SLMN7 A1 THUNDERBOLT ABO !
TypeC@

TBT_0_DG1_TEST_PW R_GOOD
SA0000CAH60
RT233 1 TypeC@ 2 100_0201_1%

RT248 1 TypeC@ 2 10K_0201_5% TBT_0_DG1_POC_GPIO5

UT7A BB3
TBT_0_DG1_SPI_DI C6 C9 TBT_0_BBR1_I2C_SCL RT201 2 @ 1 0_0201_5%
A +3VS_TBT_0_RETIMER TBT_0_DG1_SPI_DO EE_DI I2C_SCL TBT_0_BBR1_I2C_SDA RT244 I2C3_PD2_R_CLK <44,46> A
B4 E7 2 @ 1 0_0201_5%

FLASH
Change DG0_FLSH_SHARE_EN to PD TBT_0_DG1_SPI_CS# B6 EE_DO I2C_SDA A10 TBT_0_BBR1_I2C_INT# RT215 2 @ 1 0_0201_5%
I2C3_PD2_R_DAT
I2C3_PD2_R_INT#
<44,46>
<44,46>
I2C(slave) from PD2
TBT_0_DG1_SPI_CLK_R 1 @ 2 TBT_0_DG1_SPI_CLK C7 EE_CS# I2C_INT B10 SOC_DG_BB_FORCE_PW R_R
Delete DG0_FLSH_MSTR_SLV 1/7 RT234 0_0201_5% EE_CLK FORCE_PWR A9 TBT_0_DG1_FLASH_BUSY# SOC_DG_BB_FORCE_PW R_R <13,42,43,44,46>

POC GPIO
RT208 1 @ 2 10K_0201_5% TBT_0_DG1_FLSH_SHARE_EN EMC Suggestion
TBT_0_DG1_JTAG_TDI
MISC & FLASH_BUSY#
POC_GPIO_5
POC_GPIO_6
B9
A8
TBT_0_DG1_POC_GPIO5
TBT_0_DG1_POC_GPIO6
TBT_RETIMER_RESET#_R0
TBT_RETIMER_RESET#_R0 <44>
RT214 1 TypeC@ 2 10K_0201_5%
TBT_0_DG1_JTAG_TMS
TBT_0_DG1_JTAG_TCK
A3
C3
B5
TDI
TMS
DEBUG PERST#
SMBUS_SCL
B8
A7
B7
RT1_SML0CLK
RT1_SML0DATA
RT239 2 @ 1 0_0201_5%
RT220 1 VPRO@ 2 0_0201_5%
RT253 1 VPRO@ 2 0_0201_5%
PLT_RST_R# <11,26,42,44,51,53,66,68,69,70>
SOC_SML0CLK <9,42,44> PCH SML0

JTAG
TBT_0_DG1_FLSH_MSTR_SLV TBT_0_DG1_JTAG_TDO TCK SMBUS_SDA TBT_0_DG1_FLSH_SHARE_EN SOC_SML0DATA <9,42,44>
RT240 1 @ 2 10K_0201_5% C5 A4
RT241 1 2 TDO POC_GPIO_10 A5 TBT_0_DG1_FLSH_MSTR_SLV
@ 10K_0201_5%
POC_GPIO_11
Reserved v-pro only
RT247 1 @ 2 10K_0201_5% TBT_0_DG1_POC_GPIO12 A6 TBT_0_DG1_POC_GPIO12
POC_GPIO_12 & PU at CPU side
RT249 1 @ 2 10K_0201_5% L3
1TBT_0_AN1_THERMDA M11 NC_L3
TBT_0_DG1_SPI_CLK_R T219 TP@ THERMDA
CT306 2 1 10P_0201_50V8J DG2_RST# need to be output from PD
M12 controller to reset BBR main power NVPRO@
B2 TEST_EDM RT1_SML0CLK RT204 2 1 100K_0201_5%
XEMC@
FUSE_VQPS_64
20200813 remove double PU/PD TBT_RETIMER_RESET#_R
EMC Suggestion L11 PD2_DG0_RST# RT1_SML0DATA RT245 2 1 100K_0201_5%
+3VALW RESET# PD2_DG0_RST# <44,46>
A11 NVPRO@
A12 MONDC L9 TBT_0_DG1_XTAL_25M_XI
Follow E team design PD 100K

DEBUG

Main
RT206 1 TypeC@ 2 10K_0201_5% TBT_0_DG1_FLASH_BUSY# L12 NC_A12 XTAL_25_IN M9 TBT_0_DG1_XTAL_25M_XO
MONDC_SVR XTAL_25_OUT
Delete Port1 Share Rom Part 1/7 TBT_0_DG1_TEST_PW R_GOOD B3 L5 TBT_0_AN1_RSENSE
B11 TEST_PWR_GOOD
TEST_EN
RSENSE
RBIAS
L4 TBT_0_AN1_RBIAS 1 2 SMBUS:
A1
RT207 TypeC@
4.75K_0201_0.5%
No support Vpro
A2 ATEST_P
ATEST_N
Intel recommended PD 100K
DG1_RST#:
For PD based systems, DG1_RST# should be output from PD.
For TCPC based systems, DG1_RST# should be output from SOC/EC. BURNSIDE-BRIDGE_BGA105
DG1_BB_FORCE_PWR: @
Connect to EC/PCH for FW update NOTE:
'0' - by default Re-Timer with TBT , AC Caps should be use 0201/25V package.
'1' - for debug only Re-Timer without TBT , AC Caps can be use 0402/25V package.
DG1_FLASH_BUSY#: For non-PD support 25V rating is no must.
UT7D
If Flash sharing is being used, PU should be used.
If Flash sharing isn't being used, PD should be used.

DG1_FLSH_SHARE_EN: <44> TBT_0_TTX_RD1_C_DRX_P0

J1
TBT PORTS J12 TBT_0_TRX_RD2_DTX_P0 RT230 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_RD2_R_DTX_P0 CT319 1 2 0.33U_0201_25V6K TypeC@
TBT_0_TRX_RD2_C_DTX_P0 <46>
'0' - Flash isn't shared. 1 Flash per Re-timer J2 ASSRXp1 BSSRXp1 J11 TBT_0_TRX_RD2_DTX_N0 RT238 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_RD2_R_DTX_N0 CT329 1 2 0.33U_0201_25V6K TypeC@
<44> TBT_0_TTX_RD1_C_DRX_N0 ASSRXn1 BSSRXn1 TBT_0_TRX_RD2_C_DTX_N0 <46>
'1' - Flash is shared between 2 Re-timers

Port B - TypeC Side

G1 G12 TBT_0_TTX_RD2_DRX_P0 RT261 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_RD2_R_DRX_P0 CT317 1 2 0.22U_0201_25V6K TypeC@

Port A - Host Side

B DG1_FLSH_MSTR_SLV: <44> TBT_0_TRX_RD1_C_DTX_P0 ASSTXp1 BSSTXp1 TBT_0_TTX_RD2_C_DRX_P0 <46> B
G2 G11 TBT_0_TTX_RD2_DRX_N0 RT216 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_RD2_R_DRX_N0 CT325 1 2 0.22U_0201_25V6K TypeC@
'0' - Set Re-timer to be Slave on shared flash SPI I/F. <44> TBT_0_TRX_RD1_C_DTX_N0 ASSTXn1 BSSTXn1 TBT_0_TTX_RD2_C_DRX_N0 <46>
'1' - Set Re-timer to be Master on shared flash SPI I/F
C1 C12 TBT_0_TRX_RD2_DTX_P1 RT202 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_RD2_R_DTX_P1 CT305 1 2 0.33U_0201_25V6K TypeC@
<44> TBT_0_TTX_RD1_C_DRX_P1 ASSRXp2 BSSRXp2 TBT_0_TRX_RD2_C_DTX_P1 <46>
C2 C11 TBT_0_TRX_RD2_DTX_N1 RT210 1 TypeC@ 2 2.2_0201_1% TBT_0_TRX_RD2_R_DTX_N1 CT302 1 2 0.33U_0201_25V6K TypeC@
<44> TBT_0_TTX_RD1_C_DRX_N1 ASSRXn2 BSSRXn2 TBT_0_TRX_RD2_C_DTX_N1 <46>
E1 E12 TBT_0_TTX_RD2_DRX_P1 RT256 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_RD2_R_DRX_P1 CT314 1 2 0.22U_0201_25V6K TypeC@
<44> TBT_0_TRX_RD1_C_DTX_P1 ASSTXp2 BSSTXp2 TBT_0_TTX_RD2_C_DRX_P1 <46>
E2 E11 TBT_0_TTX_RD2_DRX_N1 RT212 1 TypeC@ 2 2.2_0201_1% TBT_0_TTX_RD2_R_DRX_N1 CT331 1 2 0.22U_0201_25V6K TypeC@
<44> TBT_0_TRX_RD1_C_DTX_N1 ASSTXn2 BSSTXn2 TBT_0_TTX_RD2_C_DRX_N1 <46>
+3VS
M7 M10 TBT_0_RD2_SBU1 RT231 1 @ 2 0_0201_5% TBT_0_RD2_SBU1_R
TBT_0_DG1_POC_GPIO6 <44> TBT_0_RD1_SBU1_R PA_LSTX_SBU1 BSBU1 TBT_0_RD2_SBU1_R <46>
RT217 1 TypeC@ 2 10K_0201_5% L7 L10 TBT_0_RD2_SBU2 1 2 0_0201_5% TBT_0_RD2_SBU2_R

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%

220K_0201_5%
RT254 @
<44> TBT_0_RD1_SBU2_R PA_LSRX_SBU2 BSBU2 TBT_0_RD2_SBU2_R <46>

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

2TypeC@ 1

1
RT229

RT228

RT227

RT226

RT225

RT224

RT223

RT222
T223 TP@
1 L8 @ @ @ @
1 M8 PA_AUX_P
T224 TP@ PA_AUX_N
TBT_0_TTX_RD2_R_DRX_P0 1 2 TBT_0_TTX_RD2_R_DRX_P1 1 2

2
1

1
20200813 Follow DG remove AUX DT1 EMC@ DT2 EMC@
RT243 RT257 BURNSIDE-BRIDGE_BGA105
1M_0201_5% @ @ 1M_0201_5% @
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
NOTE:
2

AC coupling caps and PU/PD on AUX lines are TBT_0_TTX_RD2_R_DRX_N0 1 2 TBT_0_TTX_RD2_R_DRX_N1 1 2 TX Rb intel recommand resevel
implemented inside Burnside Bridge DT3 EMC@ DT4 EMC@

UT7C
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
B1 F12
B12 VSS_ANA VSS_ANA G7 TBT_0_TRX_RD2_R_DTX_P0 1 2 TBT_0_TRX_RD2_R_DTX_P1 1 2
D1 VSS_ANA VSS_ANA H1 DT5 EMC@ DT6 EMC@
D2 VSS_ANA VSS_ANA H2
D11 VSS_ANA VSS_ANA H11
D12
F1
VSS_ANA
VSS_ANA GND VSS_ANA
VSS_ANA
H12
J9
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
DT1~DT8 change to SC40000H800 for ESD
F2 VSS_ANA VSS_ANA K1 TBT_0_TRX_RD2_R_DTX_N0 1 2 TBT_0_TRX_RD2_R_DTX_N1 1 2
F7 VSS_ANA VSS_ANA K2 DT7 EMC@ DT8 EMC@
F9 VSS_ANA VSS_ANA K11
F11 VSS_ANA VSS_ANA K12
VSS_ANA VSS_ANA PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
G5
VSS F5
VSS F3
VSS Follow Burmside Bridge Rev0.84
BURNSIDE-BRIDGE_BGA105
change J5 pin to NC
C
@ Power Supply Decoupling of Type-C Port0 C

+3VO_TBT_0_RD2_ANA UT7B +3VS_TBT_0_RETIMER +0.9VO_TBT_0_RD2_SVR_IND +0.9VO_TBT_0_RD2_SVR

+3VO_TBT_0_RD2_LC LT7 +0.9VO_TBT_0_RD2_LVR +0.9VO_TBT_0_RD2_LC

L2 E6 0.9V@850mA
VCC3P3_ANA VCC3P3_SX 1 2
+0.9VO_TBT_0_RD2_SVR E5 M4
VCC3P3_LC VCC3P3_SVR +3VS_TBT_0_RETIMER_2

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M

10U_0402_6.3V6M

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
M5 0.68UH_DFE252012P-R68M-P2_3.5A_20%
VCC3P3_SVR

47U_0603_6.3V6M
CT318 TypeC@

47U_0603_6.3V6M
CT320 TypeC@

18P_0201_50V8J
F6 J5 TypeC@ 1 2 2 2 2 2 2 1 2 2
VCC0P9_SVR_ANA VCC3P3_SVR

1
+0.9VO_TBT_0_RD2_SVR_IND

C92

CT332 TypeC@

CT303 @

CT312 TypeC@

CT324 @

CT316 TypeC@

CT327 @

CT323 TypeC@

CT307 TypeC@
G6 J7
25M XTAL (Type-C Port0)

Pin F6

Pin G6

Pin E3

Pin G3

Pin E9

Pin G9

Pin L6

Pin J3
VCC0P9_SVR_ANA VCC3P3A

CT322
Power

E3 L1

2
VCC0P9_SVR SVR_IND 2 1 1 1 1 1 1 2 1 1

TypeC@

TypeC@
G3 M1
+0.9VO_TBT_0_RD2_LVR VCC0P9_SVR SVR_IND
TBT_0_DG1_XTAL_25M_XI E9 M2
+0.9VO_TBT_0_RD2_LC G9 VCC0P9_SVR_PB_ANA SVR_VSS M3
TBT_0_DG1_XTAL_25M_XO VCC0P9_SVR_PB_ANA SVR_VSS
YT2 TypeC@ J3
25MHZ 10PF EXS00A-CG03482 VCC0P9_LC +3VO_TBT_0_RD2_LC +3VO_TBT_0_RD2_ANA
L6 RT1197 +3VS_TBT_0_RETIMER
1 3 Must use Metal shielded crystal M6 VCC0P9_LVR J6 NC_J6_BB3 1 @ 2 0_0201_5%
1 3 VCC0P9_LVR_SENSE NC_J6

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
for better noise immunity.
GND GND
10P_0201_50V8J

10P_0201_50V8J

Suggest adding GND shield Share Same GND plane 2 2

Pin E5

Pin L2
CT313 TypeC@

CT330 TypeC@
BURNSIDE-BRIDGE_BGA105 @
C90 TypeC@

C91 TypeC@

2 4 across Crystal and 18pF caps

2.2U_0201_6.3V6M

2.2U_0201_6.3V6M
1 1 for better RFI. and connect to M2 & M3

47U_0603_6.3V6M
2 2

1
1 1

CT311 TypeC@

CT304 TypeC@

CT309 TypeC@
pins (SVR_VSS) of BB

Pin M4

Pin J5

Pin E6
2 2

2
1 1

Rev0.2 change from 15P to 12P

+3VALW +3VS_TBT_0_RETIMER +3VS_TBT_0_RETIMER_2

JTAG (Type-C Port0) SPI ROM (Type-C Port0)
1 RT258 2 @ 1 0_0402_5% 3.3V@50mA
+3VO_TBT_0_RD2_LC CT321

10U_0402_6.3V6M

2.2U_0201_6.3V6M
20210316 2.2U_0201_6.3V6M

18P_0201_50V8J
TypeC@ Follow Burmside Bridge
change from 0 ohm to R-short 2 All 0201 decoupling caps should be places 1 2 1

CT308 TypeC@

CT326 TypeC@
D Ref Schematic D

Pin J7

Pin J7
2

CT310
TypeC@ RT242

TypeC@ RT236

TypeC@ RT251

TypeC@ RT218

as close as possible to
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

UT9 @
TBT_0_DG1_SPI_CS# RT237 1 @ 2 0_0201_5% TBT_0_DG1_SPI_CS#_R 1 8
TBT_0_DG1_SPI_DO 2 0_0201_5% TBT_0_DG1_SPI_DO_R 2 CS# VCC TBT_0_DG1_SPI_HOLD# 2 1 2
RT250 1 @
TBT_0_DG1_SPI_W P# 3 DO(IO1) HOLD#(IO3)
7
6 TBT_0_DG1_SPI_CLK_R1 RT205 1 @ 2 0_0201_5% TBT_0_DG1_SPI_CLK_R the re-timer power pins Place holder for RC filter to reduce
ripple to VCC3v3A pin
4 WP#(IO2) CLK 5 TBT_0_DG1_SPI_DI_R RT260 1 @ 2 0_0201_5% TBT_0_DG1_SPI_DI
1

GND DI(IO0)
W 25Q80DVSSIG_SO8
TBT_0_DG1_JTAG_TDI +3VALW
TypeC@
TBT_0_DG1_JTAG_TMS
TBT_0_DG1_JTAG_TCK
TBT_0_DG1_JTAG_TDO
SA00003EW10 TBT_0_DG1_SPI_CS# RT219 1 TypeC@ 2 2.2K_0201_5%
TBT_0_DG1_SPI_DO RT203 1 TypeC@ 2 2.2K_0201_5%
remove connector 2/14 TBT_0_DG1_SPI_W P# RT209 1 TypeC@ 2 3.3K_0201_5% Security Classification Compal Secret Data Compal Electronics, Inc.
TBT_0_DG1_SPI_HOLD# RT213 1 TypeC@ 2 3.3K_0201_5% 2019/09/20 2021/03/01 Title
Issued Date Deciphered Date

TBT_0_DG1_SPI_CLK_R1 1 XEMC@ 2
XEMC@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (2/3)
2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For EMI RT211 33_0201_5% CT315 22P_0201_50V8J DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
HH67A MB LA-M241P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 24, 2021 Sheet 45 of 121
1 2 3 4 5
 5 4 3 2 1

Slave Adderss setting +3V_TBT0_PDLDO +20V_VIN_TYPEC_1_L EMC Suggestion +20V_VIN_TYPEC_1

VBUS Discharge Local PWR Voltage Monitor VBUS Voltage/current Monitor +3V_TBT0_PDLDO
20200811
+3VLP
- Remove TYPEC_IN_STATUS# (RT1159)
addr2:0xC8 LT5 EMC@

1
+20V_VIN_TYPEC_1 +5V_IN_PW R_PD2 +20V_VIN_TYPEC_1 5A_Z80_0805_2P EC_PD2_INT# RT4001 2 @ 1 10K_0201_5%
RT4005 1 2
Slave Addr Ra 5% Rb 5% 33K_0201_5%

82P_0402_50V8J
10U_0402_6.3V6M

0.1U_0201_25V6K
1

1
RF@ 1 RF@ 1 RF@ 1 1 2
addr0:0xC4 NC 10K <0.2V

CT718

CT719

CT720
RT4002 RT4003 RT4004 LT6 EMC@

2
PD2_ADDR_CFG

EMC@

EMC@
200K_0402_1% 200K_0402_1% addr1:0xC6 75K 10K >=0.2V&&<0.6V 5A_Z80_0805_2P

1000P_0201_50V7K
4.7K_0805_5%

EMC@

EMC@
100P_0201_50V8J

100P_0201_50V8J
0.1U_0201_25V6K
addr2:0xC8 33K 10K >=0.6V&&<1.0V

1
2 2 2
1 1 1 1
2

2
PD2_LOC_PW R_MON PD2_VMON addr3:0xCa 10K 10K >=1.0V RT4009
1 10K_0201_5%

1
D

CT132

CT221
PD2_VBUS_DSCHG It's is used for SMBUS slave addr0/1/2/3 2 2 2 2
2

CT223

CT222
QT23 RT4007 RT4008 setting during power on initialization.

2
G L2N7002W T1G_SC-70-3 10K_0201_5% 10K_0201_5%
S
3

2
D I2C3_PD2_R_CLK_R D
UT42 SA0000DUO10 I2C3_PD2_R_DAT_R
RTS5452E-GR QFN 32P TYPE-C PD CTRL +TBT_0_PD_CC1
2

2
+3V_TBT0_PDLDO RT1170 POP: Disable Dead battery function
PD2_ADDR_CFG 20 19 RT4010 1 @ 2 0_0201_5% CT721
PD2_MGPIO2 RT1189 1 @ 2 4.7K_0201_5% PD2_MGPIO2 RT1194 1 @ 2 4.7K_0201_5% ADDR_CFG /MGPIO11 DB_DIS +5V_IN_PW R_PD2 +3V_TBT0_PDLDO
220P_0201_25V7K
PD2_MGPIO3 RT1190 1 @ 2 4.7K_0201_5% PD2_MGPIO3 RT1195 1 @ 2 4.7K_0201_5% PD2_LOC_PW R_MON 23 1 @ DVE10
PD2_MGPIO6 RT1191 1 @ 2 4.7K_0201_5% PD2_MGPIO6 RT4011 1 @ 2 4.7K_0201_5% LOC_PWR_MON/MGPIO10 YSLC05CH_SOT23-3
PD2_MGPIO7 RT1192 1 @ 2 4.7K_0201_5% PD2_MGPIO7 RT4012 1 @ 2 4.7K_0201_5% PD2_VMON 21 16 +TBT_0_PD_CC1
PD2_MGPIO8 RT1193 1 @ 2 4.7K_0201_5% PD2_MGPIO8 RT1198 1 @ 2 4.7K_0201_5% VMON/MGPIO9 PD CU CC1
CC2
18 +TBT_0_PD_CC2 RT4040 1 2 0_0402_5%
PD2_MGPIO8 22
IMON/MGPIO8 +TBT_0_PD_CC2 PD_3V@
2

1
CT722 I2C3_PD2_R_INT#_R Note:
RT4013 0_0201_5% 1 @ 2 PD2_USB1_SRC_HI_ILIM_R_PD 8 10 PD2_MGPIO6 220P_0201_25V7K 1.If the 5V_IN power supply
<50,59> PD2_USB1_SRC_HI_ILIM SOC_DG_BB_FORCE_PW R_R_PD2 AUX_P/ MGPIO4 SBU1/MGPIO6 PD2_MGPIO7 1
RT4014 0_0201_5% 1 @ 2 9 11
+3V_TBT0_PDLDO <13,42,43,44,45> SOC_DG_BB_FORCE_PW R_R AUX_N/ MGPIO5 AUX MUX SBU2/MGPIO7
voltage is fixed 5V or
variable
RT4015 0_0201_5% 2 @ 1 PD2_R_PROCHOT# 32
<7,17,43> VCCIN_AUX_CORE_ALERT#_R HPD/GPIO3 from 3.3V to 5V. Remove the
0ohm resistor.
+3VALW
2.If the 5V_IN power supply
voltage is fixed 3.3V, stuff
10K_0201_5% 2 1 RT4018 EC_PD2_INT# need check TI (ref sch 330p) the 0ohm resistor.

2
TypeC@

G
PD2_MGPIO2 12 14 QT17A
PD2_MGPIO3 13 H_DP/MGPIO2 USB2.0 SWITCH C_DP/MGPIO0 15 PD2_VBUS_DSCHG TYPE-C_20V_1_VIN_EN <83>
2N7002KDW _SOT363-6

1
4.7K_0201_5% 2 1 RT4019 PD2_I2C_2_SCL H_DM/MGPIO3 C_DM/MGPIO1
4.7K_0201_5% 2 1 RT4020 PD2_I2C_2_SDA RT4021 SOC_SML1DATA 1 6 PD2_I2C_2_SDA

S
<9,43> SOC_SML1DATA

D
10K_0201_5% 2 1 RT4023 PD2_INT#_R 100K_0201_5%

5
TypeC@

G
2
EC BBR QT17B
4.7K_0201_5% 1 2 RT4024 I2C3_PD2_R_CLK_R EC_I2C_3_SCL 3 4 I2C3_PD2_R_CLK_R 2N7002KDW _SOT363-6
4.7K_0201_5% 1 2 RT4025 I2C3_PD2_R_DAT_R I2C1(Slave) to EC <43,58> EC_I2C_3_SCL EC_I2C_3_SDA 30 SMBUS1_SCL/GPIO5 I2C_M_SCL/GPIO13 5 I2C3_PD2_R_DAT_R
10K_0201_5% 2 1 RT4026 I2C3_PD2_R_INT#_R <43,58> EC_I2C_3_SDA EC_PD2_INT# 31 SMBUS1_SDA/GPIO6 I2C_M_SDA/GPIO14 29 I2C3_PD2_R_INT#_R I2C3(Master) to BB SOC_SML1CLK 4 3 PD2_I2C_2_SCL
20200722

S
<58> EC_PD2_INT# SMBUS1_INT/GPIO4 I2C_M_INT/GPIO8 <9,43> SOC_SML1CLK

D
- Need confirm with EC
20200806 K
- INT# pull up from 2.2k to 10k ohm PD2_DG0_RST#_R 7
PCH 1 PD2_I2C_2_SCL
20200904
EN_USB1_5V_OUT# 27 SMBUS2_SCL/GPIO9 GPIOs I2C_S_SCL/GPIO11 2 PD2_I2C_2_SDA
I2C2(Slave) to PCH
- UT5/UT6(single) change to QT10(2N2002KDW) for COST .
+3VALW
0_0201_5% 2 1 RT4029 PD2_R_PROCHOT# <50> EN_USB1_5V_OUT# TBT_0_RETIMER_LS_EN 6 SMBUS2_SDA/GPIO10 I2C_S_SDA/GPIO12 28 PD2_INT#_R
<44> TBT_0_RETIMER_LS_EN SMBUS2_INT/GPIO7 I2C_S_INT/GPIO21 +5VLP_2 +5V_IN_PW R_PD2
C C

2
G
100K_0201_5% 2 1 RT4030 PD2_DG0_RST#_R PD_5V@ RT4027
1 2 0_0402_5%
100K_0201_5% 2 1 RT4032 TBT_0_RETIMER_LS_EN SOC_PD_INT# 3 1 PD2_INT#_R
<11,43> SOC_PD_INT# +5VALW _L

D
24
REXT
Power RT4031 DT26
TypeC@ QT5 1 @ 2 0_0402_5% 2 1
Dead Battery circuit

1
L2N7002W T1G_SC-70-3

VCONN_IN
+3VS_TBT_0_RETIMER RT4033 33 RB751S-40_SOD523-2

LDO_3V3
6.2K_0402_1% EPAD +20V_VIN_TYPEC_1

5V_IN
SA00008FS00
RT9069-50GB_SOT23-5

2
UT43 DBLDO@ DT25
100K_0201_5% 2 @ 1 RT4034 PD2_DG0_RST# +3V_TBT0_PDLDO 1 5 2 1

17

25

26
1.0 pop RT4034 and change net name +5VLP_2 +5VALW _L VCC OUT
from PD2_DG0_RST#_R to PD2_DG0_RST# for leakage 2 RB751S-40_SOD523-2
GND

10U_0603_25V6M
1
RT4028 2 1 0_0201_5% +5V_IN_PW R_PD2 20210914 change to @ 3 4
NC EN

1
1 2 0_0402_5% +20V_VIN_TYPEC_1

CT723
RT376 @ 1 1
CT724 CT563 RT4035

2
1.0 add diode for leakage @ 0.1U_0201_10V6K 4.7U_0402_6.3V6M 47K_0402_5% 1.0 add 0 ohm on pin3 and
2 1 PD2_DG0_RST#_R RT4036 1 2 0_0402_5% pin4 for 2nd source DBLDO@
1 1
<44,45> PD2_DG0_RST# @ CT562 CT564 2 2 1 2 RT4056
1

2
DT30 SCS00006300 RB751S-40_SOD523-2 CT725 0.1U_0201_10V6K 10U_0402_6.3V6M RT4062 2 1 0_0201_5% 75K_0201_5%
10U_0402_6.3V6M +5VALW _L DBLDO@

1
2 2 D
2 RT4057 2 DBLDO@1 75K_0201_5% 2
CC/SBU OVP G

2
+3VS_TBT_0_RETIMER RT4060 0_0201_5% 2 @ 1 QT30 S
<43,87,88> 5V_3V_EN

3
+3V_TBT0_PDLDO +3VS_TBT_0_RETIMER RT4058 1 CT728 L2N7002W T1G_SC-70-3
RT4064 0_0201_5% 2 @ 1 100K_0201_5% 1U_0201_6.3V6M DBLDO@
<11,43,58,87,88> SPOK_5V
UT45 DBLDO@ DBLDO@

1
10 3 CT726 1 2 0.1U_0201_25V6K @ @
U2 redriver

1
VPWR VBIAS TBTOVP@ RT4037 RT4038 2
CT727
1
TBT_0_RD2_SBU1_R 15 1 TBT_0_RD2_SBU1_R_SW 2.2K_0402_5% 2.2K_0402_5% +3VALW 30mA

2
TBT_0_RD2_SBU2_R 14 SBU1 C_SBU1 2 TBT_0_RD2_SBU2_R_SW @

G
1U_0201_6.3V6M SBU2 C_SBU2 QT25A CS98 2 1 1U_0201_6.3V6M

2
TBTOVP@ 2 4 +TBT_0_PD_CC1_SW 2N7002KDW _SOT363-6 U2RD@ US8
+TBT_0_PD_CC1 12 C_CC1 5 +TBT_0_PD_CC2_SW +3VALW CS99 2 1 .1U_0402_16V7K 12
+TBT_0_PD_CC2 11 CC1 C_CC2 I2C3_PD2_R_DAT 1 6 I2C3_PD2_R_DAT_R U2RD@ VCC 2 USB20_P4

S
CC2 <44,45> I2C3_PD2_R_DAT D1P
1 0_0402_5%+TBT_0_PD_CC1_SW USB20_P4 USB20_N4

D
7 RT4041 2 @ 7 1
RPD_G1 <13> USB20_P4 D2P D1M

1
2 1 9 6 RT4043 2 @ 1 0_0402_5%+TBT_0_PD_CC2_SW @ USB20_N4 8

G
+3V_TBT0_PDLDO FLT RPD_G2 <13> USB20_N4 D2M
B 100K_0201_5% TBTOVP@RT4042 RT4039 1 @ 2 0_0201_5% QT25B RS97 RS98 1 U2RD@ 2 0_0402_5% REQ = RS36 B
2N7002KDW _SOT363-6 47K_0402_5% U2RD@ 6
20 U2RD@ CS100 2 1 .1U_0402_16V7K 5 EQ 11 1 2
8 D1 19 I2C3_PD2_R_CLK 4 3 I2C3_PD2_R_CLK_R @ T337 4 RSTN VREG CS101 .1U_0402_16V7K

S
<44,45> I2C3_PD2_R_CLK

2
GND D2 SCL/CD

D
13 16 @ T338 3 U2RD@
18 GND N.C. 17 +3VS_TBT_0_RETIMER +3VS_TBT_0_RETIMER 9 SDA 10
21 GND N.C. RT4044 1 @ 2 0_0201_5% ENA_HS GND
THERMAL_PAD
1

1
G
TPD6S300ARUKR_W QFN20_3X3 RT4045 RDC1 = RS37 , RCD2 = RS38 TUSB212RW BR_X2QFN12_1P6X1P6
TBTOVP@ 2.2K_0402_5% RS99 U2RD@
QT26 @ 3 1 I2C3_PD2_R_INT#_R 47K_0402_5%
+5VALW _L L2N7002W T1G_SC-70-3 U2RD@ SA0000C8Z00

D
2

I2C3_PD2_R_INT#
<44,45> I2C3_PD2_R_INT#

2
1 @ 2 Use SA0000C8Z00 symbol
+20V_VIN_TYPEC_1_L RT4046 0_0201_5% EMC@ ESD Request
DT10
TBT_0_RD2_SBU1_R_SW 1 1 10 9 TBT_0_RD2_SBU1_R_SW
1

W = 200 mils
3

RT80 TBT_0_RD2_SBU2_R_SW 2 2 9 8 TBT_0_RD2_SBU2_R_SW

1000P_0201_50V7K

0.1U_0201_25V6K
0.022U_0402_25V7K
1

470_0201_5% 1 1 1 DT13
+TBT_0_PD_CC2_SW 4 4 7 7 +TBT_0_PD_CC2_SW
CT61

TBTNOVP@ RT109 CEST23NC24VU_SOT23-3

Need check pin define
CT59

CT60

470_0201_5% EMC@
2

TBTNOVP@ ESD Request +TBT_0_PD_CC1_SW 5 5 6 6 +TBT_0_PD_CC1_SW

2 2 2
2

EMC@ EMC@ JTYPEC1 3 3

20200904 A1 B12
GND_A1 GND_B12
5

TBTNOVP@ EMC@ 8
G

- UT5/UT6(single) change to QT10(2N2002KDW) for COST . TBT_0_TTX_RD2_C_DRX_P0 TBT_0_TRX_RD2_C_DTX_P0

QT10B A2 B11 TBT_0_TRX_RD2_C_DTX_P0 <45>
<45> TBT_0_TTX_RD2_C_DRX_P0 TBT_0_TTX_RD2_C_DRX_N0 SSTXP1 SSRXP1 TBT_0_TRX_RD2_C_DTX_N0
2N7002KDW _SOT363-6 A3 B10 AZ1045-04F_DFN2510P10E-10-9
<45> TBT_0_TTX_RD2_C_DRX_N0 SSTXN1 SSRXN1 TBT_0_TRX_RD2_C_DTX_N0 <45>
2

TBTNOVP@ TypeC@ TypeC@ SC300001Y00

G

TBT_0_RD2_SBU1_R 4 3 TBT_0_RD2_SBU1_R_SW QT10A 0.1U_0201_25V6K 1 2 CT62 A4 B9 CT63 1 2 0.1U_0201_25V6K

S

VBUS_A4 VBUS_B9
D

2N7002KDW _SOT363-6
+TBT_0_PD_CC1_SW A5 B8 TBT_0_RD2_SBU2_R_SW
+5VALW _L TBT_0_RD2_SBU2_R 1 6 TBT_0_RD2_SBU2_R_SW CC1 SBU2
S

USB20_P4_R A6 B7 USB20_N4_R
USB20_N4_R A7 DP1 DN2 B6 USB20_P4_R ESD Request
DN1 DP2 PIN SWAP 0205 DT11
EMC@

TBT_0_RD2_SBU1_R_SW A8 B5 +TBT_0_PD_CC2_SW USB20_N4_R 1 1 10 9 USB20_N4_R

Bottom

TypeC@ SBU1 CC2 TypeC@

1

TOP

0.1U_0201_25V6K 1 2 CT65 A9 B4 CT64 1 2 0.1U_0201_25V6K USB20_P4_R 2 2 9 8 USB20_P4_R

RT4047 VBUS_A9 VBUS_B4
1

470_0201_5% TBT_0_TRX_RD2_C_DTX_N1 A10 B3 TBT_0_TTX_RD2_C_DRX_N1 4 4 7 7

<45> TBT_0_TRX_RD2_C_DTX_N1 TBT_0_TRX_RD2_C_DTX_P1 SSRXN2 SSTXN2 TBT_0_TTX_RD2_C_DRX_P1 TBT_0_TTX_RD2_C_DRX_N1 <45>
A @ RT4048 <45> TBT_0_TRX_RD2_C_DTX_P1 A11 B2 A
SSRXP2 SSTXP2 TBT_0_TTX_RD2_C_DRX_P1 <45>
470_0201_5% LT2 EMC@ 5 5 6 6
2

@ 11/03 A12 B1 USB20_N4 1 2 USB20_N4_R

RT81 and RT82 near to connector GND_A12 GND_B1 1 2 3 3
Double
2

1 4 USB20_P4 4 3 USB20_P4_R 8
5

QT28A @ TBT_0_RD2_SBU1_R GND1 GND4 4 3

<45> TBT_0_RD2_SBU1_R TBT_0_RD2_SBU2_R
PJT138KA 2N SOT363-6 2 3 DLM0NSN900HY2D_4P
G

<45> TBT_0_RD2_SBU2_R GND2 GND3

2

+TBT_0_PD_CC1 4 3 +TBT_0_PD_CC1_SW SM070005U00 AZ1045-04F_DFN2510P10E-10-9

6 5 SC300001Y00
S

NC1 NC2
1

+TBT_0_PD_CC2 1 6 +TBT_0_PD_CC2_SW
0520 Remove EMI 0 ohm
S

RT81 RT82 LOTES_AUSB0528-P306A

1M_0201_5% 1M_0201_5% CONN@
QT28B @
PJT138KA 2N SOT363-6
TypeC@ TypeC@ Security Classification
20200901
Compal Secret Data
2021/09/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
2

TBTNOVP@
+TBT_0_PD_CC1 0_0402_5% 2 1 RT4049 +TBT_0_PD_CC1_SW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (3/3)
TBTNOVP@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
+TBT_0_PD_CC2 0_0402_5% 2 1 RT4050 +TBT_0_PD_CC2_SW Custom 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 46 of 102
5 4 3 2 1
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for TYPE-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 47 of 112
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for TYPE-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 48 of 112
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for TYPE-C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 49 of 112
A B C D E
 A B C D E

MB_USB3.1 TypeC Conn. (Power Path)

- For Realtek 5452E

+5VALW

1 1
1
TypeC@
+ CT537
150U_B2_6.3VM_R35M
+3V_TBT2_PDLDO SGA00009M00 +20V_VIN_TYPEC_0_L
2

UT40
6 1
IN OUT

47P_0201_50V8J
0.1U_0201_25V6K
RT1422 RT1423

CT232 @RF@

CT233 @RF@
1 1

1
100K_0201_5% 100K_0201_5% PD1_USB2_ILIM 5 2 TypeC@
TypeC@ TypeC@ SET GND CT230
10U_0603_25V6M

2
Initial High EN_USB2_5V_OUT 4 3 2 2
EN FLAG
H: Provider 5V OFF SY6861B1ABC_TSOT23-6
L: Provider 5V ON TypeC@

6
D RF Suggestion
EN_USB2_5V_OUT# 2 QT16A SA0000BDN00
<43> EN_USB2_5V_OUT# G 2N7002KDW _SOT363-6 TypeC@ TypeC@

1
S RT1424 RT1425

1
4.02K_0402_1% 4.02K_0402_1%
TypeC@

2
PreMP:
change to 12K ,set limit with 3.5A Typ.

3
D
PD1_USB2_SRC_HI_ILIM 5 QT16B
<43,59> PD1_USB2_SRC_HI_ILIM SILERGY SY6861B1 MOS Current Limit
G 2N7002KDW _SOT363-6
PD1_USB2_SRC_HI_ILIM RSET(kΩ) MODE limit point
S PD2_USB1_SRC_HI_ILIM

4
1
PD1_USB2_SRC_HI_ILIM : TypeC@ L 4.02 1.5A 1.69A
RT1426
H = 5V/3A 100K_0201_5%
L = 5V/1.5A *H 2.01 3A 3.38A
@
I= 6800/R SET

2
2 2

+5VALW_L

1
TypeC@
+ CT714
150U_B2_6.3VM_R35M
+3V_TBT0_PDLDO SGA00009M00 +20V_VIN_TYPEC_1_L
2

UT47
6 1
IN OUT

47P_0201_50V8J
0.1U_0201_25V6K
RT1427 RT1428

CT715 @RF@

CT716 @RF@
1 1

1
100K_0201_5% 100K_0201_5% PD2_USB1_ILIM 5 2 TypeC@
TypeC@ TypeC@ SET GND CT717
10U_0603_25V6M

2
Initial High EN_USB1_5V_OUT 4 3 2 2
EN FLAG
H: Provider 5V OFF SY6861B1ABC_TSOT23-6
L: Provider 5V ON TypeC@

6
D RF Suggestion
EN_USB1_5V_OUT# 2 QT18A SA0000BDN00
<46> EN_USB1_5V_OUT# G 2N7002KDW _SOT363-6 TypeC@ TypeC@

1
S RT1429 RT1430
1 4.02K_0402_1% 4.02K_0402_1%
TypeC@

3 3

2
PreMP:
change to 12K ,set limit with 3.5A Typ.

3
D
PD2_USB1_SRC_HI_ILIM 5 QT18B
<46,59> PD2_USB1_SRC_HI_ILIM G 2N7002KDW _SOT363-6

4
1

PD2_USB1_SRC_HI_ILIM : TypeC@
RT1431
H = 5V/3A 100K_0201_5%
L = 5V/1.5A @
I=21/RSET
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Power Path
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 50 of 112
A B C D E
 A B C D E

PCIE redriver(Remove)

1 1

+3VALW +3VALW _LAN +VDD095_EXT +VDD095_EXT

@
RL1 1 2 0_0805_5% CL52 +5VALW _L +3VALW _LAN
1 22U_0603_6.3V6M 1U_0201_6.3V6M Place close Pin11,16,22 Place close Pin8,28,47 Place close Pin34

1
2 1 RL4 1 @ 2 +VDD095_LAN

22P_0201_50V8J

10U_0402_6.3V6M

10U_0402_6.3V6M
1
CL1 RL24 0_0603_5%

CL8

CL9

CL10

CL11

CL12

CL13

CL14

CL15

CL24

CL25

CL22

CL23

CL26

CL27

CL20
CL56
UL5 1.8K_0402_1% 20210316
UL2 2 +1.8VALW _PRIM 10 1
1 1 VDD VOUT 2
1 1 change from 0 ohm to R-short
5 1 9 2

CL54

CL55
CL2 CL3 CL53

2
IN OUT VIN VOUT

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0402_6.3V6M 10U_0402_6.3V6M 8 3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VIN VOUT

10U_0402_6.3V6M
0.1U_0402_16V7K 2 2 1 7 4
2 2 GND POW _EXT_SW R 6 VIN ADJ/NC 5 2 2 @
4 3 EN PGOOD

1
EN OC 11 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 PAD 2
SY6288C20AAC_SOT23-5 RL25
RT9059GQW _W DFN10_3X3 10K_0402_1%
SA000071S00
S IC RT9059GQW W DFN 10P LDO Place close Pin43

2
<58> LAN_PW R_EN

1 *Vout = 0.8 * ((1.8K+10K)/10K) = 0.944V

CL16 10/23 Place close Pin37 Place close Pin19,33 Place close Pin29,46
change from SWR to LDO
nee check with vendor
0.1U_0402_16V7K

+3VALW _LAN

Place close Pin15

LL2
1 @ 2 LAN_PME# 1 2 AVDD33_PLL
RL11 4.7K_0201_5%
1 @ 2 POW _EXT_SW R BLM15PX330SN1D_2P
RL12 4.7K_0201_5% +3VALW _LAN
+3VALW _LAN 10/4 DVT modify UL3
check PU on EC sied or LAN side Power Manahement/Isolation 1 1
1

CL30

CL31
ISOLATEB
1 2 LAN_PME# LAN_PME# 2 ISOLATEB Power
<58> LAN_PME# LANWAKEB
RL6 4.7K_0201_5% 29
1 2 LAN_DISABLE_N_R DVDD33 46 2 2

22U_0603_6.3V6M
0.1U_0402_16V7K
RL7 4.7K_0201_5% PCI-Express DVDD33
1 2 POW _EXT_SW R CLK_PCIE_LAN 44 15 AVDD33_PLL
+3VS RL8 4.7K_0201_5% <11> CLK_PCIE_LAN CLK_PCIE_LAN# 45 REFCLK_P AVDD33 19
1 2 LED_LINK_ACT# <11> CLK_PCIE_LAN# REFCLK_N AVDD33 33
AVDD33
1

SJ10000TO00 RL9 4.7K_0201_5% PLT_RST_R# 36

YL1 <11,26,42,44,45,53,66,68,69,70> PLT_RST_R# CLKREQ_LAN# PERSTB
RL13 Place close to pin 27 48 34 +3VALW _LAN
25MHZ_20PF_7R25000001 <11> CLKREQ_LAN# CLKREQB AVDD33_XTAL
1K_0402_5%
CL64 1 2 .1U_0402_16V7K PCIE_CRX_C_DTX_P12 38 43 RL10 1 @ 2 0_0402_5% 20210316 change from 0 ohm to R-short
<13> PCIE_CRX_DTX_P12 PCIE_CRX_C_DTX_N12 HSOP EVDD33
3 XTLI 1 3 XTLO CL62 1 2 .1U_0402_16V7K 39 3
2

1 3 <13> PCIE_CRX_DTX_N12 PCIE_CTX_C_DRX_P12 HSON

ISOLATEB CL60 1 2 .1U_0402_16V7K 41
NC NC <13> PCIE_CTX_DRX_P12 PCIE_CTX_C_DRX_N12 HSIP +VDD095_LAN
1 1 <13> PCIE_CTX_DRX_N12 CL58 1 2 .1U_0402_16V7K 42 8
2

HSIN DVDD09 28
CL28 2 4 CL29 RL17 Transceiver Interface DVDD09 47
33P_0402_50V8J 33P_0402_50V8J Place close Pin38~42 LAN_MDIP0 13 DVDD09
15K_0402_1%
2 2 LAN_MDIN0 14 MDIP0 11
LAN_MDIP1 17 MDIN0 AVDD09 16 Enable external switch regulator to generate power of 0.95V.
1

LAN_MDIN1 18 MDIP1 AVDD09 22 1: Enable 0: Disable.

LAN_MDIP2 20 MDIN1 AVDD09
LAN_MDIN2 21 MDIP2 37
MDIN2 EVDD09 20210316
LAN_MDIP3 23
LAN_MDIN3 MDIP3 change from 0 ohm to R-short
24
MDIN3 Other pins RL14
JRJ1 6 POW _EXT_SW R_R 1 @ 2 0_0201_5% POW _EXT_SW R
XTLI RL15 1 2 0_0402_5% XTLI_R 10 POW_EXT_SWR 4
XTLO RL16 1 2 0_0402_5% XTLO_R 9 CKXTAL1 Clock NC1 5 10/4
CKXTAL2 NC2 7 check with vendor
UL4 NC3 Pin4 and Pin5 VDDREG is need or not
RL20 RJ45_MDIN3 8
1 24 2 1 RJ45_GND PR4- GPIO RL18
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_MDIN3 RJ45_MDIP3 7 Reference 3 LAN_DISABLE_N_R 1 @ 2 0_0201_5% LAN_DISABLE_N
LAN_MDIP3 TD1+ MX1+ RJ45_MDIP3 PR4+ LAN_RST GPI LAN_DISABLE_N <11>
3 22 75_0402_1%~D 2 1 12
TD1- MX1- RJ45_MDIN1 6 RL19 2.49K_0402_1% RSET
RL21 PR2- 10/4
4 21 2 1 RJ45_MDIN2 5 Place close to IC General Purpose Input / Output Pin. connect to PCH GPIO
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_MDIN2 PR3- 10/4 1. Power Saving Feature: Output pin check venndor 用用
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_MDIP2 75_0402_1%~D RJ45_MDIP2 4 check venndor is need or not 2. Link OK Feature: Output pin
TD2- MX2- PR3+ EEPROM/SPI Flash/LED 3. PHY Disable mode (active low): Input pin
RJ45_MDIP1 LED_LINK_ACT# 4. LAN Disable mode (active low): Input Pin
RL22 3 TP@ PAD~D T339 1 27
7 18 2 1 PR2+ TP@ PAD~D T340 1 LED_SPEED_2500# 30 LED1/EESK/SPISCK
LAN_MDIN1 8 TCT3 MCT3 17 RJ45_MDIN1 RJ45_MDIN0 2 TP@ PAD~D T341 1 LAN_SPISO 25 LED0/EEDI/SPISI/SDA
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_MDIP1 75_0402_1%~D PR1- 10 TP@ PAD~D T342 1 LAN_SCL 31 LED2/EEDO/SPISO
TD3- MX3- RJ45_MDIP0 1 SHLD2 9 TP@ PAD~D T343 1 LAN_ROM_SEL 32 EECS/SCL 10/4
RL23 PR1+ SHLD1 TP@ PAD~D T344 1 LAN_SPICS# 26 EEPROM_SEL vendor recommand pin40 reserve 0 ohm to GND
10 15 2 1 35 SPICSB 40
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_MDIN0 LED3 GND 49
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_MDIP0 75_0402_1%~D E_Pad
TD4- MX4-
MHPC_NS892436 SANTA_130452-0E1
CONN@ E3100G-CG_QFN48_6X6

4 SP050009V00 4 mm High DC23400GH00 SA0000DDG10

1000P_0201_50V7K

1000P_0201_50V7K

1000P_0201_50V7K

1000P_0201_50V7K

4
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

USE DC234006L00 symbol

RJ45_GND 1 2 LANGND
CL38
40mil 10P_0201_50V8J

1 1 1 1 1 1 1 1
2

1
EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

@ LANGND
CL32

CL33

CL34

CL35

CL36

CL37

CL39

CL40

J1 EMC@ JP1
2 2 2 2 2 2 2 2 JUMP_43X118 XEMC@
B88069X9231T203_4P5X3P2-2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

DL1
For EMI AZ5125-02S.R7G_SOT23-3 LAN-Killer3100G w/redriver
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCA00001A00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 51 of 112
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 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Power Path
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 52 of 112
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 5 4 3 2 1

WLAN INTEL AX411

+3VALW +3VS_WLAN
+3VS_WLAN +3VS_WLAN

1 UM6 AX1675S@
CM147 UM7 W=60mils 1 1 1 1 1 1

10U_0402_6.3V6M

10U_0402_6.3V6M
0.01U_0402_16V7K

0.1U_0201_10V6K

0.01U_0402_16V7K

0.1U_0201_10V6K
5 1

CM152

CM155

CM150

CM154

CM151

CM153
1U_0201_6.3V6M IN OUT
2 2
GND 1 1 2 2 2 2 2 2
CM148 CM149
EC_WLAN_ON 4 3 S_W/L_MOD KILLER AX1675S BT 999M3K ABO!
<58> EC_WLAN_ON EN OC 4.7U_0402_6.3V6M 0.1U_0201_10V6K PK29S00D120
SY6288C20AAC_SOT23-5 2 2

Close to pin 4, 5 Close to pin 72,73

D D

+3VS_WLAN
Symbol need to creat
+3VS_WLAN UM6B
UM6A GG01 GG37
4 2 RM12 1 GG02 GND_44 GND_80 GG38
5 3.3V_1 200K_0402_1% GG03 GND_45 GND_81 GG39
72 3.3V_2 29 GG04 GND_46 GND_82 GG40
3.3V_3 PEWAKE# CLKREQ_WLAN# WLAN_PME# <59> GND_47 GND_83
73 30 GG05 GG41
3.3V_4 CLKREQ# WL_RST#_R CLKREQ_WLAN# <11> GND_48 GND_84
A48 31 1 @ 2 PLT_RST_R# <11,26,42,44,45,51,66,68,69,70> GG06 GG42
A49 3.3V_5 PERST# RW15 0_0201_5% GG07 GND_49 GND_85 GG43
3.3V_6 GG08 GND_50 GND_86 GG44
27 GG09 GND_51 GND_87 GG45
SUSCLK(32KHZ)(3.3V) GG10 GND_52 GND_88 GG46
1 Refer ORB NC GG11 GND_53 GND_89 GG47
2 UIM_POWER_SRC/GPIO1 14 GG12 GND_54 GND_90 GG48
3 UIM_POWER_SNK SYSCLK/GNSS0 15 GG13 GND_55 GND_91 GG49
UIM_SWP TX_BLANKING/GNSS1 GG14 GND_56 GND_92 GG50
GG15 GND_57 GND_93 GG51
11 7 GG16 GND_58 GND_94 GG52
12 COEX_TXD RESERVED GG17 GND_59 GND_95 GG53
13 COEX_RXD GG18 GND_60 GND_96 GG54
COEX3 GG19 GND_61 GND_97 GG55
6 GG20 GND_62 GND_98 GG56
16 GND_1 17 GG21 GND_63 GND_99 GG57
18 RESERVED_1 GND_2 20 GG22 GND_64 GND_100 GG58
19 RESERVED_2 GND_3 23 GG23 GND_65 GND_101 GG59
66 RESERVED_3 GND_4 26 GG24 GND_66 GND_102 GG60
67 RESERVED_4 GND_5 32 GG25 GND_67 GND_103 GG61
21 RESERVED_5 GND_6 35 GG26 GND_68 GND_104 GG62
22 RESERVED_6 GND_7 38 GG27 GND_69 GND_105 GG63
24 RESERVED_7 GND_8 41 GG28 GND_70 GND_106 GG64
25 RESERVED_8 GND_9 62 GG29 GND_71 GND_107 GG65
RESERVED_9 GND_10 68 GG30 GND_72 GND_108 GG66
1.0 change CW11 CW12 to RW53 RW54 GND_11 71 GG31 GND_73 GND_109 GG67
CLK_PCIE_WLAN# 33 GND_12 74 GG32 GND_74 GND_110 GG68
<11> CLK_PCIE_WLAN# CLK_PCIE_WLAN 34 REFCLKN0 GND_13 75 GG33 GND_75 GND_111 GG69
<11> CLK_PCIE_WLAN REFCLKP0 GND_14 GND_76 GND_112
76 GG34 GG70
PCIE_CRX_DTX_N4 RW54 1 2 0_0201_5% PCIE_CRX_C_DTX_N4 36 GND_15 77 GG35 GND_77 GND_113 GG71
C <13> PCIE_CRX_DTX_N4 PERN0 GND_16 GND_78 GND_114 C
PCIE_CRX_DTX_P4 RW53 1 2 0_0201_5% PCIE_CRX_C_DTX_P4 37 78 GG36 GG72
<13> PCIE_CRX_DTX_P4 PERP0 GND_17 79 GND_79 GND_115
PCIE_CTX_DRX_N4 CW10 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_N4 39 GND_18 80
<13> PCIE_CTX_DRX_N4 PETN0 GND_19 AX201.D2WG_152P
PCIE_CTX_DRX_P4 CW9 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P4 40 81
<13> PCIE_CTX_DRX_P4 PETP0 GND_20 82 @
GND_21 83
42 GND_22 84
43 CLINK_CLK GND_23 85
44 CLINK_DATA GND_24 86
CLINK_RESET GND_25 87
GND_26 88
45 GND_27 89
46 SDIO_RESET# GND_28 90
47 SDIO_WAKE# GND_29 91
48 SDIO_DATA3 GND_30 92
49 SDIO_DATA2 GND_31 93
50 SDIO_DATA1 GND_32 94
51 SDIO_DATA0 GND_33 95
52 SDIO_CMD GND_34 96
SDIO_CLK GND_35 G1
GND_36 G2
53 GND_37 G3
54 UART WAKE#(3.3V) GND_38 G4
55 LPSS_UART_RTS/BRI_DT GND_39
56 LPSS_UART_RXD/BRI_RSP
Reserve for BT_ON OD pull high (1.0) LPSS_UART_TXD/RGI_DT
+3VS_WLAN 57
LPSS_UART_CTS/RGI_RSP
RW20 1 @ 2 10K_0201_5% WL_OFF#
RW21 1 @ 2 10K_0201_5% BT_ON 58
59 PCM_SYNC/I2S_WS
60 PCM_OUT/I2S_SD_OUT
61 PCM_IN/I2S_SD_IN A07
PCM_CLK/I2S_SCK GND_40 A26
GND_41 A31
WL_OFF# 28 GND_42 A50
<58> WL_OFF# BT_ON W_DISABLE1# GND_43
63
<10> BT_ON W_DISABLE2#
A11
65 RESERVED_10 A12
64 LED1# RESERVED_11 A13
LED2# RESERVED_12 A14
RESERVED_13 A16
USB20_N10 69 RESERVED_14 A17
<13> USB20_N10 USB20_P10 USB_D- RESERVED_15
70 A18
<13> USB20_P10 USB_D+ RESERVED_16
B
A27 B
RESERVED_17 A28
8 RESERVED_18 A29
9 ALERT# RESERVED_19 A30
10 I2C_CLK RESERVED_20 A46
I2C_DATA RESERVED_21 A47
RESERVED_22
CNV_RF_RESET# RW51 1 2 CNV_RF_RESET_N A42
<14> CNV_RF_RESET# RF_RESET_B
0_0201_5% A08
CLKREQ_CNV# RW52 1 2 MODEM_CLKREQ A43 A4WP_IRQ# A09
<14> CLKREQ_CNV# CLKREQ0 A4WP_CLK
0_0201_5% A44 A10
CNVI_REFCLK0 REFCLK0 A4WP_DATA A15
T349 @ LNA_EN A25
Refer ORB NC A45 C_P32K WLAN_SUS_CLK_R RW29 1 @ 2 33_0201_5%
NC SUSCLK <11>
A19 CLK_CNV_CTX_DRX_P
WT_CLKP CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P <14>
A20
CNV_RF_RESET# WT_CLKN CNV_CTX_DRX_P0 CLK_CNV_CTX_DRX_N <14>
A21
WT_D0P CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 <14>
A22
WT_D0N CNV_CTX_DRX_N0 <14>
1

A23 CNV_CTX_DRX_P1
WT_D1P CNV_CTX_DRX_N1 CNV_CTX_DRX_P1 <14>
RM61 A24
WT_D1N CNV_CTX_DRX_N1 <14>
75K_0402_5%
A32 CLK_CNV_CRX_DTX_P
WGR_CLKP CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P <14>
A33
CLK_CNV_CRX_DTX_N <14>
2

WGR_CLKN A34 CNV_CRX_DTX_P0

WGR_D0P CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 <14>
A35
WGR_D0N CNV_CRX_DTX_P1 CNV_CRX_DTX_N0 <14>
A36
WGR_D1P CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 <14>
A37
WGR_D1N CNV_CRX_DTX_N1 <14>
A38 CNV_BRI_DT RW25 1 2 0_0201_5% CNV_BRI_CTX_DRX
BRI_DT CNV_BRI_RSP CNV_BRI_CTX_DRX <14>
A39 RW26 1 2 39_0201_1% CNV_BRI_CRX_DTX CNV_BRI_CRX_DTX <14>
BRI_RSP A40 CNV_RGI_DT RW30 1 2 0_0201_5% CNV_RGI_CTX_DRX
RGI_DT CNV_RGI_RSP CNV_RGI_CTX_DRX <14>
A41 RW31 1 2 39_0201_1% CNV_RGI_CRX_DTX CNV_RGI_CRX_DTX <14>
RM10 RGI_RSP
MODEM_CLKREQ 1 2
75K_0402_1%

AX201.D2WG_152P
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2021/5/30 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 53 of 121
5 4 3 2 1
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PCIE Device
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 54 of 112
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PCIE Device
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 55 of 112
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 A B C D E

HD Audio Codec Speaker SPKR+ LA6 1

EMC@
2 HCB1608KF-121T30_0603 SPK_R+ 1
CONN@
JSPK1

SPKR- LA7 1 2 HCB1608KF-121T30_0603 SPK_R- 2 1

EMC@ 2 3
G1 4
G2

1
680P_0402_50V7K

680P_0402_50V7K
CONN@

CV4221

CV4222
EMC@ JSPK2 CVILU_CI4202M2HR0-NH

2
SPKL+ LA4 1 2 HCB1608KF-121T30_0603 SPK_L+ 1 SP02001CK00
SPKL- 1 2 HCB1608KF-121T30_0603 SPK_L- 2 1
LA5 EMC@ 2 3
G1 4
G2

1
680P_0402_50V7K

680P_0402_50V7K
CVILU_CI4202M2HR0-NH

CV757

CV758
1 SP02001CK00 1
SM01000EJ00 SM01000EJ00

2
+5V_AUDIO
3000ma 220ohm@100mhz +5VS_PVDD +5VS_AVDD
3000ma 220ohm@100mhz +5V_AUDIO
DCR 0.05 DCR 0.04
LA10 LA1
1 2 1 2
HCB2012KF-221T30_2P_0805 HCB2012KF-221T30_2P_0805 vender suggest 2021/05/14
1 1 1 1 1 1

10U_0402_6.3V6M
CA8

0.1U_0201_10V6K
CA9

10U_0402_6.3V6M
CA5

0.1U_0201_10V6K
CA3

10U_0402_6.3V6M
CA6

0.1U_0201_10V6K
CA4
1 1 1 1

10U_0402_6.3V6M
CA10

0.1U_0201_10V6K
CA11

10U_0402_6.3V6M
CA12

0.1U_0201_10V6K
CA13
2 2
2 2 2 2
2 2 2 2 Headphone Out
near Confirm with ESD
near near Pin40 20211122
GNDA
Pin41 Pin46 - RA16/RA17 change to 47 ohm by Vender test

+1.8V_AUDIO HPOUT_R RA16 1 2 47_0402_5% HPOUT_R_1

HPOUT_L RA17 1 2 47_0402_5% HPOUT_L_1

near CA14 1 2 0.1U_0201_10V6K
Pin18 1 1 No LINE signal from codec

10U_0402_6.3V6M
CA15

0.1U_0201_10V6K
CA16
CA17 1 2 10U_0402_6.3V6M
+3V_AUDIO 2 2

3
330P_0402_50V7K
CA26
@

330P_0402_50V7K
CA27
@

TVNST52302AB0_SOT523-3
D2
@
RA85 1 @ 2 0_0402_5% +3VS_DVDD_IO 2 2

@ JPA1 1 1
1 2 +3VS_DVDD near
+5VS 1 2 +5V_AUDIO Pin20
GNDA

1
RA81 1 @ 2 0_0402_5%
JUMP_43X79
1 @ 2 GNDA GND
SCA00004700
20191104
+3VS +3V_AUDIO - Config change to @
RA82 0_0402_5% 1 1 1

10U_0402_6.3V6M
CA18

0.1U_0201_10V6K
CA19

0.1U_0201_10V6K
CA20
1 @ 2
+1.8VS +1.8V_AUDIO 2 2 2
RA83 0_0402_5%
2 2
HDA_BIT_CLK_AUDIO

1
XEMC@

18

41

46

40

20
JP5

3
UA1 RA73 SLEEVE_L 4
near 0_0402_5% RING2_L 3
Audio vender request (change from 62 ohm to 0ohm)

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
Pin3 HPOUT_R_1 1 R66 2 0_0603_5% HPOUT_R_2 2

2
HPOUT_L_1 1 R9 2 0_0603_5% HPOUT_L_2 1
1

330P_0402_50V7K

330P_0402_50V7K
43 SPKL- XEMC@ 5
SPK-OUT-L- 42 SPKL+ CA39 7
SPK-OUT-L+ HP_PLUG# G
22P_0201_50V8J 6 8
2 G
RING2 33 45 SPKR+
MIC2-L(PORT-F-L)/RING2 SPK-OUT-R+

D4 AZ5123-02S.R7G_SOT23-3
SLEEVE 34 44 SPKR- SINGA_2SJ3082-020111F
MIC2-R(PORT-F-R)/SLEEVE SPK-OUT-R-

2
CONN@

@
2 2
DMIC_DATA HPOUT_L

@
4 30 @
CODEC_MUTE_LED# <38> DMIC_DATA SPK_MUTE# GPIO0/DMIC-DATA12 HP-OUT-L(PORT-I-L) HPOUT_R
RA86 1 @ 2 0_0201_5% 1 29 GNDA
<59,63> CODEC_MUTE_LED# DMIC_CLK DMIC_CLK_AUDIO GPIO2/DMIC-DATA34 HP-OUT-R(PORT-I-R)

C13

C12
RC449 1 2 22_0402_5% 5 GNDA
<38> DMIC_CLK GPIO1/DMIC-CLK 1 1

SCA00001B00
7 28 CA41 1 2 1U_0201_6.3V6M GNDA
6 I2C-CLK CPVPP 27 CBN1 CA40 1 2 1U_0201_6.3V6M
1 I2C-DATA CBN1
EMC@ 26 CBP1

1
CA7 CBP1
10P_0201_50V8J 11 15 HDA_SYNC_R
2 8 I2S-MCLK/GPIO3 AUDIOLINK:SYNC 14 HDA_BIT_CLK_AUDIO RA14 1 @ 2 0_0402_5% HDA_SYNC_R <10>
I2S-IN AUDIOLINK:BCLK HDA_SDOUT_R HDA_BIT_CLK_R <10> GND
12 17 GNDA
Near PIN5 10 I2S-LRCK AUDIOLINK:SDATA-OUT 16 HDA_SDIN0_AUDIO RA15 1 2 33_0402_5% HDA_SDOUT_R <10>
I2S-BCLK AUDIOLINK:SDATA-IN HDA_SDIN0 <10>
9
+3VS I2S-OUT
ALC3324 32
MIC2-VREFO-R +MIC2_VREFO_R
31
MIC2-VREFO-L +MIC2_VREFO_L +MIC2_VREFO_R
CBN2 24
CBN2
1

CBP2 25
R4087 CA25 2 1 1U_0201_6.3V6M CBP2 39 +MIC2_VREFO_L
LDO1-CAP

1
2.2K_0402_5%
RA8
10K_0402_5% 21
@ MONO_IN 36 LDO2-CAP 19
PCBEEP LDO3-CAP

1
2.2K_0402_5%
RA10
2

1
CODEC_VREF

10U_0402_6.3V6M
CA29

10U_0402_6.3V6M
CA30

10U_0402_6.3V6M
CA38

100K_0402_5%
RA19
3 13 38 1 1 1
3

2
CODEC_MUTE_LED# EC_MUTE#_R 2 DC-DET/EAPD VREF
PDB

2
SENSE_A 47 23 CPVEE
CODEC_MUTE_LED# RA87 1 2 0_0201_5% MIC_MUTE# 48 JD1(HP JD) CPVEE 2 2 2

2
GPIO4/JD2(I2S-IN/I2S-OUT JD)

2.2U_0402_6.3V6M
CA33
1U_0201_6.3V6M
37 1 1 EMC@
35 AVSS1 22
Follow vendor suggest change CA34 from 10U to 0.22UF MIC2-CAP AVSS2
BLM15PX330SN1D_2P
20210727 49 CA32 SLEEVE L1 1 2 SLEEVE_L
1 Thermal Pad RING2 L2 1 2 RING2_L
CA34 2 2 GNDA GNDA BLM15PX330SN1D_2P

2
0.22U_0402_16V7K S IC ALC287-CG MQFN 48P EMC@
2

AZ5123-02S.R7G_SOT23-3

EMC@
SA0000EDG10

D3
GNDA GNDA GNDA
2 2
GNDA S IC ALC287-CG MQFN 48P AUDIO CODEC 0FA C11 C10
ALC3324 using ALC287 Symbol EMC@ EMC@
680P_0402_50V7K 680P_0402_50V7K ESD Request
1 1

1
GND GND
GND

+3VS_DVDD

+3VS_DVDD
RA39 2 1 22K_0402_5% BEEP#_R CA36 1 2 0.1U_0201_10V6K MONO_IN
<58> BEEP# Raptor:289
1

1
RA38 2 1 22K_0402_5%
20200903 RA22 RA20
<7> PCH_SPKR - RA23 10K change to 0 ohm for MUTE# issue
1

RA30 1 @ 2 0_0402_5% 1 10K_0402_5% 100K_0402_1%

@ RA23 2 @ 1 0_0402_5% TO Audio Jack
2

1 2 0_0402_5% <59> EC_MUTE# 2 1 10K_0402_5% EC_MUTE#_R

RA31 @ CA37 RA40 RA24 @

2
100P_0201_50V8J 5.1K_0402_1% <10> HDA_RST#_R SENSE_A 2 1 HP_PLUG#
1

RA32 1 @ 2 0_0402_5% 2 200K_0402_1% RA21

JACK Detect 1
2

CA35
0.1U_0201_10V6K
RA33 1 @ 2 0_0402_5% @ RA25
4 4
RA34 1 @ 2 0_0402_5%
10K_0402_5% JD1 2
2

RA35 1 @ 2 0_0402_5%
HP-JD LINE1-JD

RA36 1 @ 2 0_0402_5%
200K 100K
Near pin 48
@
CA31 1 2 .1U_0402_16V7K

GND GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/08/26 Deciphered Date 2020/08/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA CODEC(ALC3324)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 56 of 121
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2020/09/25 Deciphered Date 2021/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for Audio
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HH67A MB LA-M241P
Date: Friday, December 24, 2021 Sheet 57 of 112
A B C D E
 5 4 3 2 1

+1.8VALW_PRIM
near SOC SOC_RTCRST# <11>

1
EC_RST# +VTT_EC +1.05V_PROC D

1U_0201_6.3V6M
C63 1 2 0.1U_0201_10V6K 1

C87
EC_CLR_CMOS 2 QB1
G L2N7002WT1G_SC-70-3

1
R27 2 @ 1 0_0402_5% 20210727 S

3
2 change net name from RB4
+1.05V_VCCST to 10K_0402_5%
1 +1.05V_PROC
Vendor suggest C54

2
+3VLP +3VLP_EC +3VLP_ECA 0.1U_0201_10V6K
20200720-Remove EC_PME# PU@ R35 2
0_0603_5% L4 Vendor suggest
D
1 @ 2 1 2 D
BLM15AX601SN1D _2P

4.7U_0402_6.3V6M
SM01000KL00 CONN@ SP010028W00 For EC debug

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1 ACES_51625-01201-001

C62

C60
+3VLP_EC +1.8VALW_PRIM +1.8VALW_ESPI +VTT_EC

C59
C58 14
0.1U_0201_10V6K GND 13 +3VS
R32 1 2 2.2K_0402_5% EC_SMB_CK0 2 2 2 R28 2 GND
R31 1 2 2.2K_0402_5% EC_SMB_DA0 0_0402_5% 12 0_0201_5% RB70
1 2 12 11 UART_EC_CRXD_DTXD 1 @ 2
11 UART_EC_CTXD_DRXD UART_2_CTXD_DRXD <12>
10 1 @ 2
10 9 E51TXD_P80DATA 0_0201_5% UART_2_CRXD_DTXD <12>
@ ECAGND RB71
ECAGND <83>

111

117

124
9 8 E51RXD_P80CLK

22
33
96

67
U6 8

9
7 0_0201_5% 1 @ 2 RB34 KSI0
7 KSI0 <58,63>
ESPI Bus Pin : 1~14 6 0_0201_5% 1 @ 2 RB29 KSO3

PECI_VTT
VCC_ESPI
VCC
VCC
VCC

AVCC
VCC0

VCC_IO2
6 KSO3 <58,63>
5
Power rail 1.8V
C86
XEMC@
2 1 2
XEMC@

R29
1 ESPI_CLK_R EMI 2021/08/19 change from eSPI_ALERT to HAPTIC_EN
TP_PWR_EN 1
eSPI & MISC
21
5
4
3
4
3
2
0_0201_5%
0_0201_5%
0_0201_5%
1
1
1
@
@
@
2
2
2
RB30
RB31
RB32
KSI4
KSI5
KSI6
KSI4
KSI5
<58,63>
<58,63>
<66> TP_PWR_EN HAPTIC_EN GA20/GPIO00 PWM0/GPIO0F EC_VCCST_PG_R <11> 2 KSI6 <58,63>
22P_0201_50V8J 33_0402_5% 2 23 1 0_0201_5% 1 @ 2 RB33 KSI7
<66> HAPTIC_EN FP_PWR_EN ESPI_ALERT#/GPIO01 PWM1/GPIO10 FAN_PWM1 BEEP# <56> 1 KSI7 <58,63>
3 PWM Output 26
<66> FP_PWR_EN 4 GPIO02 FANPWM0/GPIO12 27 FAN_PWM2 FAN_PWM1 <77>
<9> ESPI_CS# ESPI_CS# FANPWM1/GPIO13 FAN_PWM2 <77> JDB1
5 1.0 RB70、RB71、RB29~RB34 change to 0 ohm
<9> ESPI_IO3_R ESPI_IO3
Reserved R3874,as Schematic checklist requirement, 7
<9> ESPI_IO2_R ESPI_IO2 BATT_TEMP CONN@ +3VS
remove R33 (PD @ PCH side) 8 63
<9> ESPI_IO1_R ESPI_IO1 AD0/GPIO38 VRAM_TEMP BATT_TEMP <82,85>
10 64 ACES_50208-00801-003 Transfer to debug card
<9> ESPI_IO0_R ESPI_IO0 AD1/GPIO39 VRAM_TEMP <83>
65 1
ESPI_CLK_R AD2/GPIO3A AD_BID ADP_I <83,85> 1 2 UART_EC_CRXD_DTXD
12 AD Input 66
<9> ESPI_CLK_R EC_USB_EN 13 ESPICLK AD3/GPIO3B 75 EC_PERKEY_INT# 2 3 UART_EC_CTXD_DRXD
<71> EC_USB_EN EC_RST# GPIO05 AD4/GPIO42 EC_PERKEY_INT# <63> 3 4 E51TXD_P80DATA
37 76 IDCHG
<77> EC_RST# CHG_EN ECRST# AD5/GPIO43 IDCHG <85> 4 5 E51RXD_P80CLK
20
<72> CHG_EN CHG_CTL1 GPIO0E 5 6
38
<72> CHG_CTL1 ESPI_RST# GPIO1D 6 7
14
<9> ESPI_RST# ESPI_RST#/GPIO07 SPOK_5V 7 8
68
DA0/GPIO3C SPOK_5V <11,43,46,87,88> 8
R34 1 @ 2 4.7K_0402_5% OPMODE DA Output 70 OPMODE
KSI0 55 DA1/GPIO3D 71 EC_WLAN_ON 9
C KSI0/GPIO30 DA2/GPIO3E WL_OFF# EC_WLAN_ON <53> GND1 C
KSI1 56 72 10
KSI1/GPIO31 DA3/GPIO3F WL_OFF# <53> GND2
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_SMB_CK2 JDB2
KSI3/GPIO33 SCL2/GPIO4A EC_SMB_DA2 EC_SMB_CK2 <39,62,63,66,72>
KSI4 59 84
KSI4/GPIO34 SDA2/GPIO4B EC_I2C_3_SCL EC_SMB_DA2 <39,62,63,66,72>
OPMODE (Internal Pull High) : KSI5 60 85
61 KSI5/GPIO35 SCL3/GPIO4C 86 EC_I2C_3_SDA EC_I2C_3_SCL <43,46>
KSI6
KSO[0..17] KSI6/GPIO36 SDA3/GPIO4D TP_CLK EC_I2C_3_SDA <43,46>20200806 - I2C 3 for PD 20200817
KSI7 62 87
Pull Up : Intel eSPI Master Attached Flash Sharing Topology <58,63> KSO[0..17] KSO0 39 KSI7/GPIO37
PS2 Interface
PSCLK3/GPIO4E 88 TP_DATA TP_CLK <66> - Follow FH51M
KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA <66>
--> For KB9042 / KB9052 KSI[0..7] KSO1 40
KSO1/GPIO21
(change power source to +5VS for power leakage) +5VS
<58,63> KSI[0..7] KSO2 41
KSO3 42 KSO2/GPIO22 97 SOC_ENBKL EC_SMB_CK2 R69 1 @ 2 4.7K_0402_5%
Pull Down : Intel Legacy Wire-OR share ROM. KSO4 43 KSO3/GPIO23 SHICS#/GPIO60 98 EC_PD1_INT# SOC_ENBKL <6,39> EC_SMB_DA2 R70 1 @ 2 4.7K_0402_5%
--> For KB9022/9042 Use KSO5 44 KSO4/GPIO24 SHICLK/GPIO61 99 SLP_SUS# EC_PD1_INT# <43>
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62 VCIN0_PH SLP_SUS# <11> +5VALW
KSO6 45 109
KSO7 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH <83>
KSO8 47 KSO7/GPIO27 EC_SMB_CK2 R4089 1 2 4.7K_0402_5%
+3VLP_EC KSO9 48 KSO8/GPIO28 119 DGPU_AC_DETECT EC_SMB_DA2 R4090 1 2 4.7K_0402_5%
49 KSO9/GPIO29 MISO_SHR_ROM/GPIO5B 120 ADP_DET DGPU_AC_DETECT <26,85>
KSO10 20200720-Remove BT_ON from EC (GPIO5C)
EC_SMB_CK1 KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C EC_CLR_CMOS ADP_DET <83> 20200722-Add
R67 1