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Experiment1 - VLSI Design Lab Manual

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46 views9 pages

Experiment1 - VLSI Design Lab Manual

Uploaded by

Harikrishna Vallapuneni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE DEPT, PRESIDENCY UNIVERSITY

VLSI Design Lab Laboratory Manual


(ECE 3008)

for

5th Semester B. Tech.


Prepared by Verified by
1. Mr. SYED ABRAR AHMED 1. Dr. BHANU REKHA K

Edited by: Ms Akshaya M


Ganorkar

Department of Electronics and Communication


Engineering

Presidency University
School of Engineering
Itagalpura, Rajanukunte, Yelahanka, Bangalore-560064
08-09-2022

VLSI Design Lab (ECE 3008) Page 1


ECE DEPT, PRESIDENCY UNIVERSITY

VLSI Design Lab (ECE 3008) Page 2


ECE DEPT, PRESIDENCY UNIVERSITY

Contents
Program
TITLE Page No.
No.

P1 Design of Basic Logic Gates using Verilog 3

P2 Design of Half adder, half subtractor, Full Adder using Verilog 8

P3 Design of Multiplexer, De-multiplexer and Encoder using Verilog. 12

P4 Design of SR, JK, D & T Flip Flops and Counters using Verilog 15

Understanding the basic steps for Cadence 22

P5 Plot the Static Characteristics of MOS Transistor 31

P6 Measurement of Parameters of an Inverter 35

P7 Design of 2-Input CMOS NAND and NOR Gate 43

P8 Design of Common Source (CS) with and without resistive load 47

VLSI Design Lab (ECE 3008) Page 3


ECE DEPT, PRESIDENCY UNIVERSITY

Experiment No. 1
Design of Basic Logic Gates using Verilog
Objective: The aim of the experiment is to write verilog code for the basic logic Gate circuit
and observe the waveform.
Tool required: Xilinx ISE tool
Theory: Digital systems are said to be constructed by using logic gates. These gates are
the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are
described below with the aid of truth tables
1. NOT Gate

Test Bench for NOT Gate


Verilog Code module notgate_tb;
wire t_y;
module not1(input a, output b ); reg t_a;
andgate dut1( .a(t_a), .y(t_y) );
assign b= ~a;
initial begin
endmodule t_a = 1'b0;
#5
t_a = 1'b1;
Simulation Waveforms
#5
t_a = 1'b1;
end
initial begin
$monitor (" %d", $time,t_y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

VLSI Design Lab (ECE 3008) Page 4


ECE DEPT, PRESIDENCY UNIVERSITY

2. And Gate

Test Bench for All Other Gates


VERILOG CODE
module logicgate_tb;
module and1( input a,b, output c); wire t_y;
reg t_a, t_b;
assign c= a & b; basicgate dut1( .a(t_a), .b(t_b), .
endmodule y(t_y) );
initial begin
$monitor(t_a, t_b, t_y);
t_a = 1'b0;
t_b = 1'b0;
#5
Simulation Waveforms
t_a = 1'b0;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b1;
end
initial begin
$monitor ("%t | t_a = %d| t_b = %d|
t_y = %d", $time, t_a, t_b, t_y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

VLSI Design Lab (ECE 3008) Page 5


ECE DEPT, PRESIDENCY UNIVERSITY

3. OR Gate

VERILOG CODE
module OR1(input a,b, output c);
assign c=a | b;
Endmodule

Simulation Waveforms

4. NAND Gate

VLSI Design Lab (ECE 3008) Page 6


ECE DEPT, PRESIDENCY UNIVERSITY

VERILOG CODE
module nand1( input a,b, output c);

assign c= ~(a & b);


endmodule

Simulation Waveforms

5. NOR Gate

VERILOG CODE
module nor1(input a,b, output c);
assign c=~(a | b);
endmodule

Simulation Waveforms

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ECE DEPT, PRESIDENCY UNIVERSITY

6. EX-OR Gate

VERILOG CODE
module xor1(input a,b, output c );
assign c= a ^ b;
endmodule

Simulation Waveforms

Result: The logic Gates Design have been realized and simulated using HDL codes.

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ECE DEPT, PRESIDENCY UNIVERSITY

VLSI Design Lab (ECE262) Page 9

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