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DIGITAL BASIC - 1.5 : Multiplexer (MUX)
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1.1 1.2 1.3a 1.3b 1.4 1.5 1.6

Number Digital Logic Logic Combinational Multiplex Vlsi ex
System Arithmetic Gates Gates Circuits (MUX)
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De-Multiplexer:

Receives information on a single line and transmits that information on one of 2n possible output lines.
The selection of specific output line is controlled by the bit values of ‘n’ selection lines.
Multiplexer:

Secure
Multiplexing means transmitting a large number of information units over a smaller number of channels lines.
A digital multiplexer is a combinational circuit that selects binary information from one of many inputs lines and directs it in a signal
output line. store
The selection of a particular line is controlled by a set of selection lines.
Normally, there are 2n input lines and ‘n’ selection lines whose bit combinations determine which input is selected.”
100+ fil
Multiplexers can be used for the implementation of Boolean functions, combinational circuits. They can also used for parallel to serial
with up to
conversion.
in Google D
Multiplexer is also called data selector or universal circuit.
It is used for connection two or more sources to a single destination among computer units and it is useful for constructing a common
bus system

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 Timing Paths : Sta
Timing Analysis (STA
basic (Part 1)
6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts
Basic of Timing
Analysis in Physical
Design

"Setup and Hold Tim

: Static Timing Analy
(STA) basic (Part 3a

"Examples Of Setup
Total number of 2: 1 MUX = 3 and Hold time" : Sta
Timing Analysis (STA
MUX as a universal logic gate basic (Part 3c)

"Setup and Hold Tim

Gate Type Implemented by MUX + Equation Violation" : Static
Buffer Y=output = A Timing Analysis (STA
basic (Part 3b)

10 Ways to fix SETU

and HOLD violation:
Static Timing Analys
(STA) Basic (Part-8)

Delay - "Wire Load

Model" : Static Timin
Analysis (STA) basic
(Part 4c)

"Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)

Delay - "Interconnec
NOT/Inverter Y=A’ Delay Models" : Stat
Timing Analysis (STA
basic (Part 4b)

Maximum Clock
Frequency : Static
Timing Analysis (STA
basic (Part 5b)

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AND Y=A.B

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 NOR Y=(A+B)’
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NAND Y=(A.B)’
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XOR

XNOR

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 If the 2 minterms in a column are not circled, 0 is placed to the corresponding multiplexer inputs.
If the 2 minterms in a column are circled, 1 is placed to the corresponding multiplexer inputs.
6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts
If the minterms in the second row is circled and the first row is not circled, apply second row of variable to the
corresponding multiplexer inputs.
If the minterms in the first row is circled and not the second row, apply first row of the variable to the corresponding
multiplexer inputs.
Example: Implementation of given function using 8 to 1 multiplexer
F(A,B,C,D) = Ʃ (1,3,4,11,12,13,14,15)
Solution.
Total number of variable n = 4 (A,B,C,D)
Number of select lines: n-1= 3 (B, C, D)
The given function has 4 variable, so 16 possible minterms (0 – 15) are entered in the implementation table.
All the minterms are divided into 2 groups
The first group (0-7) minterms are entered in the first row (Variable A =0)
The second group (8–15) minterms are entered in the second row (Variable A= 1)
Circle the minterm number as per function, which you have to implement (in this case it’s 1,3,4,11,12,13,14,15)
Find out the multiplexer input as per above given steps.

Implementation Table

Given multiplexer is 8:1

Logic diagram

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6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts

Example
Implement the following Boolean function with 8 : 1 multiplexer
F(A,B,C,D) = ∏M (0,3,5,6,8,9,10,12,14)

Solution
The given maxterms are inverted to obtain minterms. From the minterms, we can implement the above Boolean function by using 8 : 1
multiplexer. Select lines are B, C and D, the input variable is A.
F(A,B,C,D) = Ʃ m(1,2,4,7,11,13,15)

Example
Implement the following Boolean function with 8 : 1 multiplexer
F(A,B,C,D) = Ʃ m (0,2,6,10,11,12,13) + Ʃ d(3,8,14)
Solution.

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6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts
26 comments:
Anonymous October 10, 2014 at 7:34 AM

Very good explaination

Reply

Anonymous November 4, 2014 at 6:12 PM

very helpful..are you going to post remaining concepts of digital designing

Reply

Replies

VLSI Expert November 4, 2014 at 11:45 PM

Yes I will do. but it will take some time.

Reply

Ketan January 2, 2016 at 11:21 PM

How many 16:1mux required for 64:1 mux

Reply

Replies

Unknown June 29, 2019 at 9:09 AM

[64/16]+[64/16²] = 4

Reply

Ketan January 2, 2016 at 11:23 PM

Someone gave me answer as 4 -64/16= 4

And some as 5- 64/16=4+1(for next one)=5
So which one is correct 5 or 4

Reply

Replies

VLSI Expert January 4, 2016 at 7:31 PM

if you can't use anyother gate.. like AND, OR, XOR .. then 5 is correct. but in case you can use any such basic gates - then 4 is correct
answer.

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 Unknown February 23, 2017 at 9:47 PM
6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts
Well said !!!!!! Really useful
Reply

Anonymous March 7, 2017 at 7:58 PM

it is very helping...thanxxx....:-)

Reply

happy room August 8, 2017 at 9:11 AM

This artical is posted right when I finished my postgraduate study in 2014. Quite late to know about this. But still useful.

Reply

bloxorz August 8, 2017 at 9:24 AM

Many thanks for sharing this very diverse opinion post where each expert has no doubt shared his best knowledge on the topic. Have more success in
your journey.

Reply

happy wheels August 9, 2017 at 1:20 PM

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 Reply

6/25/24, 12:13 PM DIGITAL BASIC - 1.5 : Multiplexer (MUX) |VLSI Concepts

Vijay Verma November 4, 2018 at 11:55 AM

its really helpfull, thanks:)

Reply

Unknown June 20, 2020 at 7:51 PM

can you explain about 256:1 mux using 8:1 mux that requires 37 mux!

Reply

AVAP2311 May 12, 2021 at 3:21 PM

How can this method(used in the examples above),be used to implement a boolean expression using 4:1 instead of 8:1?
we would have 4 input lines, so how would the table be made?

Reply

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