| oF i | F Darshan | Unit 1 — Introduction to Micropracesser ao = Ln uInlene rocesner Address Hus © itis a group of wires or lines that are used to transfer the addresses of Memory oF ya devices fh isuniditeetonat 8 the woth ef the address bus Caesponds to the minimum addrevene capacity of he bus, Of the largest adexs wathen meimary hat the Bur can york with The addresses are transfered in binary farmat, wth each ling of the address us carrying a single binary oy 4 Tnerelore the manmum address capacity 1 equal to twro to the power of the number of lines peesent (2*lines) Data Bus fr wiez to transfer data within Micropeccessor ang Memanyfinput ar Output devaces mabceectional at Microprocessor requires to pend or receive dts Each wire is used for the transfer of signals corresponding to a single bit of binary data As iwch, a greatet wath allows greater amounts of data fo be transferred at the same : heme Control Buss © Microprocenct uses contrat but to process data, ie, what ta do sith the velected memary location # Same conteo! signals ave Read, Wiae and Opcoste fetchete # Various operations ate performed by microprocessor with the help of contra! bw & Tht a dedicated bus, becauie all timing signals are generated 2< cording to control signal + 4, Microprocessor systems with bus organization Figure: Microprocessor systems with bus organization “arma CE Dept | 2290797 -— Micropiotesior and interfacing_ Darshan Unit 1 — Introduction to Microprocessor To design any meaningful application micropraessar requires support a athor auxitary devices In most sumysified form a mereprocessor based system consist af a microprocessor, Yo do pviouiput) devices and memory These components are interfaced (connected) with micropracesser over a common fommunication path called system bus Typical structure of a microprocessor based system is shawn on Figure: Here, micraaracessor is master of the system and responsible fir exe and coordinating with connected peripherals at required Memory is responsible for staring pragrart as wet! as data, System generally consists of twa types of memories ROM (Read only and non-volatile) ang RAM (Read/Write and volatile). YO Cevices are used to communicate with the environment. Keyboard can be examale of input devices and LED, LCD 4r monitor can be example of output device Bepending an the application ‘evel of saphestication varies in a microprocessor based systems, For example: washing machine, computer, Prot Swati Rshatea,CE Dept. | 2150707 Microprocessor ana iatenacingUnit-2 Microprocessor Architecture sification of Memory Memory | ‘ ff a Prime [Storage Memory Memory Secondary | Gockup f= Storage = Rw Semi-random Serial | | rom | sce feces I] ] Permanent || ishs | | Memary Rewes |) B/W Ficepy hm ee Non | | Integrated Masked nOmt | |comox | PaGat ip Disk Figure: Classification: of Memory ROM (Read Only Memory}: The first classifieation of memory is ROM. The data inthis memory can only be read, ne writing Wsallawed .tis used to store permanent programs. It is a naavalatile type of memory. | static |) Oymannie The classification of ROM memory is as follows: 1. Masked ROM: the program or data are Permanently installed at the time of manufacturing as per requirement, The dota cannot be altered. The process of permanent recording is expensive but econemic for large quantities, 2. PROM {Programmable Read Only Memory]: The basi¢ function is same as that of masked ROM, but in PROM, we howe fuse links, Depending upon the bit pattern, the fuse can be burnt ar kept intact. This jobis performed by PAOM programmer. To do this, it uses high current pulse between twa lines Because of high current, the fuse will get burnt, effectively making two lines open. Once a PAOM 1s programmed we Cannot change connections, only a facility provided over masked ROM ws, the user can load his progeara in it, The disadvantage is a chance of ee-growing af the fuse and Changes the programmed data because of aging, sha nd Interlacing omy FIS0707 = Micropraces Siaa wel —— Parshan | __Unit-2 Micraproce: ar Architecture 3 EPROM {Erasable Programmable Read Only Memory}! the EPROM w programmable bythe user Ituses MOS circuitnyta store data. They store 1°s and 0's The information stared can be erased by exposing the memory te ul wituich erases the data stored sn 3%! memory locations, For ulteavialot bght, 4 quart: window 's provided wich is covered duling normal operation Upon eeasing it can be repropronimed busing EPROM programmer. This tyne of memory is used in a project ‘Sevelored and for experiment use, The advantage ist can be programmed erssed and reprogrammed, The disadvantage + all the data get eraxec even if you want ta change single dat Form of charg 4. EEPROM: EEPROM stands for electrically erasable programmable read only memory. This is similar to EPROM except that the erasing is done by electrical signals instead of wleravintet light. The main advantage is the memory location can be selectively crased and reprogrammed But the manvfacturing process is complex and expensive su de Fat commonly used. R/W Memory (Read/Write Memory): The RAM is alsa called a3 read/write memory, The RAM is a valatile type of memory. It allows the programmer to read or write data. If the user wants te check the execution of any program, user feeds the program in RAM memory and executes it. The result of executian is, then checked by either reading memory tocation contents er by register contents Following is the classification of RAM memory. At is available in two types: 1, SRAM (Static RAM); SRAM consists of the flip-lop; using either transistor or MOS, for cach bit we require ane flip-flop. Bit status will remain as it is; untess and until you perform next write operatian or pawer supply is switched off Advantages of SRAM: © Fast memary [less access time) = Refreshing ¢ircuit is not required, Disadvantages of SRAM: * Low package density + Costly ‘Swati R Sharma, CE Oepartment 2150707 ~ Micioprocessor and Intertating |Darshan _ Unit-2 Microprocessor Architecture 2 DRAM (Dynamic RAM): 14 this type of memary a data is stored i form of charge in capacitors. When data 6 1. the capacitor wall ke charged and of data 15-0, the capacitor will not be charged: © of capacitor leakage currents, the data will not be held by these cells, Sathe DRAMS require relreshing, of memory celts. Iisa process in which same data is read and written after a fixed interval Advantages of DRAM: * Hegh package density + Low cost # Disadvantages of DRAM: + Required refreshing circuit to maintain or refeesh charge on the eapacitar, every after few milliseconds. Secondary Memory = Magnetic Disk: The Magnetic Disk is Flat, citcular platter with metallic coating that is rotated beneath read/write heads, Issa Random access device: read/write head can be moved to any location on the platter + Floppy Disk: iheseare small removable disks that are plastic coated with magnetic recording material, Floppy disks are typically 3.5” in size diameter} and can hold 144 MB of data. This portable storage device is a rewritable media and can be reused.a number of times, Floppy disks are commonly used ta move tiles between different computers, The main disadvantage of floppy disks 1s that they can be damaged easily and, therefore, are not very reliable. The tollawing figure shows an example of the floppy disk. Figure 3 shows a picture of the floppy disk, Hard Disk: Anather form of ausuliary storage & a had disk, A hard disk consists of ‘one oF more rigid metal plates coated with a metal oxide material that allows data to be magnetically recorded on the surface of the platters. The hard disk platters spin at $ a high rate of speed, typically $400 to 7200 revolutions per minute (RPM).S1orage capacities of hard disks for personal computers range from 10 GB to 120.68 [one billion bytes are called a gigabyte} © Optical Disks: Optical Mass Storage Devices Store bit values at variations in light tellection. They have higher area density & longer data life than magnetic storage They are also standardieed and relatively inexpensive, Their Uses: read-only storage with low performance requirements, applications with high capacity requirements & where portability in a standardized format is needed. Swati. Sharma, CE Gepartment 2150707 ~ Microprocessar and Intertacing 3estan | itecture types of Optical Disk 1. £B-ROM [read onl 2. CD-R: [record] to. 3 C0 3, CD-RW: can write and erage CO to couse it fee-writable) BVDIDigital Video Disk} 2 Explain 1/0 devices and their Interfacing Ans. Input / Output (I/O) + MPU communicates with outsae word through W/O device, « There are 2 different methods by which MPU ide and communicates Wath YO devices these methods arc: 1. Direct I/G [Peripheral] 2+ Memory-Mapped The methods differ in terms of the 4 No, of address lines used in identifying an I/O device, + Type of control lines used to enable the device. + Instructions used for data transfer. Direct 1/0 (Peripheral): This method uses two instructions (IN& GUT) for data transfer, 2 MPU uses @ address lines to send the address af 1/0 device (can identity 256 input dewces & 256 output dewces) 4 The (//P & OFF devices) can be differentiated by contral signals i/O Read [/O) and 4fO Write (O04 The steps in communicating with an 0 device are with memory and can be summarized as follows 1. The MAU places an B-bit device address on address bus then decoded 2 The MPU sends a contra! sigoal [JGR or IOW) 10 enable the /O device. 4 Data are placed on the data bus far transfer. ilar Lo those in communicating Memory-Mapped 1/0:- © The MPU uses 16 address tines ta identity an YO device. This is similar fo communicating with a memary location Use the same control signals (MEMR or MEMW) and instructions as those of memory, The MPU wews these I/O dewices as if they were memory tocatians There are ro special I/O instructions, it can identify 4k address shared between memory & HO devices, se eae Swati A. Sharma, CE Department 2150707 ~ Micsapeocesiot and Incertacingfeatures of O85 Microprocessor, Jed with AMOS technptagy, address Ws and Rene can addeess up 1a 216» 65546 Inve mary locations a ree fast lines of adkdtess bus. and 8 lines of data bus are multiplexed ADO ADT sa nroupat Blnes D0- UF eupttoguest.. + Bats Fe supports eatermat it A Teta pregiam counters (Pe) © ATE bit stack pointer |$P) $n 8.bit general gurpose register arranged in pairs: AC. OL, HL. ftrequires a signal +SV power supply and operates a 3.2 MHZ single phase clock fuss enclosed with 40 pins DIP [Dual in line package, 2. Explain 8085 microprocessor architecture, sn SoD: Seca D0 Coated Accumyiator is} Flip Hops Register OL RESET IN REABY Fagure: 8085 micropancevicn arebrinetare: 1 and ttestacing lar Shekhal, CE Deparment | 2180707 » Micropeoces4 ~ Register Unit: _ General Parpoxe Data Register ROSS hap ale genctal purpare dala = These repisters are named as 8, C, 0, €, Hand las shown in fig. 2 ©The user can use these repisters to store of copy a data temporarily during the execution af a program bby using data transfer instructions, © These registers are of B bits but whenever the microprocessor has ta handle 16-bit dats, these regitters fan be combined as register pairs = BC, Of and HL ‘There are two internal registers — W and X, These registers are only for internal aperation like earcution ‘of CALL and XCHG instructions and not available to the user, Program Counter (PC) * 16-bit register Geabs with sequencing the execution of instructions, © This register is a memory pointer. ‘Memory locations have 16-bit addresses which are why this is a 16-bit register. "The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is te point to the memory address from which the next byte fs to be fetched ‘When a byte (mathine code} is being fetched, the program counter is incremented ky one te point to the next memory location Staca i Port of Bortem Stack Pointer | © SP is also 16-bit registe- used as a memary pointer. * It points to a memory bocation in #/W memary, called the stack. “The beginning of the staek is defined by loading 16-bit address in the stack pointer. bit dan stets to store MUX/DEMUX unit = This unit (¢ used to select a repister out of all the available registers. This unit behaves as a MUX when data Is going from the register to the internal data bus. ft behaves a3 a DEMUX when data bs coming 16 2 regiter from the internal data bus of the microprocessor. The register select will behave as the function selection lines of the MUK/DEMUX, Address Buffer Register & Data/Address Buffer Register © These registers hold-the address/data, received from PC/imternal data bus and then load the external address and data buses, These registers actually behave as the bulfer stage between the micropracessor and external Hatem buses.Darshan Unit-3 - Microprocessor Architecture Control Uni © the conte! Knit generates signals wothen mcroprecessor taCatay Out the instructian, whath has been areo + by wealty causes connettions between blocks ef the microprorewor Le be opened or cloved, wo that the data gocs where Wis tequited and the ALU aperations G¢cut + The central ant quel connats of Uiree parts, the snsteachon regiiters (Ia), instruction decoder ang machine cyile ¢midter and timeng and coateol uid, Instruction Register +The repter hogs the machin code of the inslewesion Wher microprecester erecuter a program reads the opcode {rom the memory, this opcode is stored ia the wsteuction reget ruction Decoder & Machine Cycle Encoder +The IR sends ihe machine cede to this unit This unit, ag as name sugzetis, decodes the opcode and fines Gut what i to be done in response of the Intertamt Request. 1 1s used ay general purpose METERS | INTAY (Output) — Interrupt Acknowledge. tis wsed to acknowledge an imtesTUFt a RST75, ASTA.S, ASTS-5 (input] > Restart Interrunts |) These are vector interrupts that transfer the program central so saecific memory locations fo They have higher priorities than INTR inernupt JArnomg these J interrupts, the priarity order is RSTH 5, RSTES, RSTS-S TRAP {inputf >This a hon maskable interrupt & has the highest Pronk v ROLD {input} —+ This signal indicates that 2 peripheral such as OMA Comroller is requesting the use ef address 8 data buses e ROA {Output -» Hold Acknowledge, Ths signal acknowiedges the HOLD reavest READY (tagut] —» ‘This'signal is used to delay the mecropracessor read OF wile eycies vob a3 low respanding peripheral Is ready to send er accest data, when the signal goes law, the microprocessor waits for an integral no, of cock eveles until it goes MER ¢RESET In {input} > When the signal on thi pin gues low, the Program Counter is $53 to 2¢r0, the buses ace triestated & m-croprocesser is reset 6 RESET OUT (Output) > This signal in reget ather devites. ates that migtoprocessor is being reset, The signal can be wed 10 6) Serial 1/0 Parts 4 Two pins for serial teansmission 1) SID (Serial input Data-pi Ss) 3] $00 (Serial Output Bata-pin 4) « Insenial transmission, data bits are sent ever a single ine, one Bit at a time- Microprocessor Architecture 5. Explain Instruction Cycle uation Cyclo defined ox OSS instruction ceele V4 Aaguited ta cemmplete- regulon of an instruction RL OF 1a 6 Machine Cyetes oo ee aperatinny Instruction Cycle Fetch Cycle ~—++— Execute Cycle T, nh | Ty Te gate minationtnie 6. Explain Machine Cycle 1 Hlachine Sycle o: detined as time seguired by the menipragess0r te complete eperation of accessing memary demce or WO devi. this cycle may consist Ato T-atates “The tase maeropracentor operation such 33. leading # byte from (70 port or wsiting 2 byte to memary +f exlied as machine ever Opcode Fetch Memory Read —\ fo Machine Machine cyele-1 Cycle-2 figure Mehndi 7. Explain T-States ‘Mater sre defined 21. cre 1ubdension of operation pedformed en one clock pened These tub dhesions ave intemal states synchronized with aystem clock B each Trane is precisely equal ue one clack pone Pred. Uiay M. Sheth ‘Seethan CC Demantment: | 2150707 - Miaropsocesior and tmterdauneTState TeStabez Testates | Ngee tte 8. Compare Instruction Cycle, Machine Cycle and T-States Opcode Fetch Memory Read i t ty A wn af Nf Machine |— Machine Cycle-1 Cyele-2 Instruction Cycle Fetch Cycle Execute Cycle Tesatea | Siete? ogee vongten abe Tstyces a reve Commoatune betes ntrarion Cle Masvine Cycle ard State Instruction Cycle: Time requited to complete eeegution of an instruction + Mathine fycle: Tine requited by the miceeprocessos te complete an operation + TStutesGne 1ubderision af operation pertormed io ane check period POUMTEYM Shatbat CE Depadment | FIHGTG? —Mcioprocesi ang Itetiong Unit-3 ~ Microprocessor Architecture —_T atJ Darshan | Unites ~ Microprocessor Architecture 4. Explain 8085 Programming Modet ‘Ralirectianal Unicieectionat Agave BO Pag amoming Moe Registers 4G penenal purpone repters to sone bt data B.C, EMAL + Can be ceiniboved a tepeiter pairs — BC OM and 8 tp perform 34 wt operatans ou OF Koy data uung Gata Copy Hmtructiney Accumulator +B be ropste, went bi + parrot aus © Used oatore thie data to perform arthonetic & kepcal operations + Result operation o Hored mut. Flag Register ALU han S Flog Repeater that set/neset after an operation according to data conditions of tie reudt in aecueTlatoe otter regnters Netpld drcmcen making protest af Microprocessot + Garomori are tested through voltwale iste lions + toreg F. Ehere cn Carry) i mplemanied ta change the sequence of program when CY Wet Program Counter + Wobtregaten weata hold memory addresses 7 Sta Pelt because memory addeestes ave of 16 tee, ret e Verve Wether Ct Oepaitment ORE « Marraged rien andl inte ig awUnit-3 ~ Microprocessor Architecture Merropreectser uses 6¢ fe Bites tn sequence the execution afiestructlons Na funciona to point to mermarpadtdreis from which : nowt byte is lobe feiched Nehena ive i beng letched, Cis inciementod by 116 point to aget memory focatiah ack Pointer Used as memory pain Points 10 tte memory toration iy RAW memcy called Stack + Bepaming at statk y defined by loading a 16-bit addressin ine stock posite, 10. Explain Bus Organization of now control Bak | gui ten eaten BS Address Bus Groupe! 1B bnes generally identiied as AD te AIS + Hsuniae oral ie biti flow thom mcroprncesior te pteipheeval devine, 4) Maggareys Imes ave capaple ot adavessing 65538 memory locatiane. $0, 80085 has 64 memory iecations, Data Bus | 2 Gopal fines enitted as pate a7 They ate bathrectceal ie ate flow in both dvections between imycroproceisnr, merory & penpheral, \ | 8 Bata deed enable micrepeacestey ta manipulate data ranpng from Odbl to MH [269256 number |= tareestrumeer ssiea# on datstousis 1499 2891 os L2S8]10 [¢ #1 Par boris often, BOBS known as Bt Microprecetsor Control Bus. + Hicomprries of vrious singe lines that casey ypnehreni ation, ming & contra! signa Prat Way M$Sethat, CE Department | 2150707 - Mintnprotesur ane interlacing aq Darshan | Unit-3 - Microprocessor Architecture + These signals are used to dentity a demce type wath which MPU sntends ta communicate 11, Explain Demultiplexing ADO-ADT a Bit High Order “OR! Addeess dus ra A % fl oe ALE=1 Micropracessit| Address Bus os 7AaLSa73 hy Bo tew-trder AL Address Bus Ay ay Ay ALEZO £2 p ita Bus o, OF pi Data Bus Fone Bemdteleung ADOANT ‘The higher-order fui f@mainn on the Bus for three clock periods. However, the low-order address be toat afver the frat cheek persod, “4 address needin be latched and ured lor ientstying the memory sddess, the bus ADT-AD is used te entre memory locaton 2008], the address wll change to 208FH afte the first elock peviod + Pegure ows a vchemate thal wie a lateh and the ALE signal to.demultipiea the tus, The bus AD? AbD 1s conmected’ ai tee esput to-the latch, =the er F Binsls cornested to the Leable pin of Ne latch, and the SuIDut cHAtel Signal of the lateh wed, + Rigureshows 1 le INE ach atthe ALE goes hgh dune U3. And during 11 addess of lower-order address buy a elove aDarshan | Unit-3 - Microprocessor Architecture 12. Explain Memory Interfacing When we ate executing any insttuction, we noed the microprocessor to access the memory for reading snstragtion codes and the data slated in the memory, + For this, both the memory and the nikroprocessor eeauites some opnals to readfnrite Neytrom regters +The interfacing etcust therelore should be designed ir suche a way that it matches the memcey sepnal requirements with the signals of the micropsacesor Memory Read Cycle High-Order Aya, Addeoss Low-Order AD, AD, SX tees, | By ; Address 5] | Mode lo 0 HLT Read from fa). | ware meee 1jo | READ a | 1 | OPCODE L4 FETCH agate Mamny assole + Ineuresto fetch one bite fromthe memnary be requites 31 states + cam bewseg to terch operand.ee data tram the memery. During 11 AS-ALS contains hgher byte ef adeess, AL the same time ALE (high, Therefore Lower byte poladtess AO.AT is solectec Hem ADOT ‘Brce it memany ready ppEcabon, ‘C/N four) goes tow Gueing 12 ALE goes low, RO Iba) goed low, Adézets Is remaved fram ADO-AD? and data OO-OF appears on ADD AG? Buren 73, Data temains on AQG-apy LiMAD {bar} ist low signal (Peel SM, Seek CE Gagarin HS09S7 Resropcevis and ltertanne Tasor Architecture 12, Explain Memory Intertacing 4. Wneli oe ate eeecirirg: a inviuetiin; nie the lk dphogesioy a acgese the meme) tor Wading instrucla codes ard the data storesin the memory, ‘1 FREINS. Both the mernary and the miteeprace egy reaU vet imme varus to readiwite tation vepaiers “ne ibterlacog: cum thetclore shell or desigied in such a way that ol malches the memory BFS Teaustements with the signaty of the micragesessor. Memory Read Cycle Ty T, " Te 1 High Order Bev Aas (Pcl. | Raines, a Low Order Address ff f=0, 5,70, 5,91 Read from: Memory | Bagute: Memory Besa Cre + tis vied to fetch one byte trom the memory + requres 3 Tatates van be werd ta fetch operand oF d3ta from the memary, + During 15, AS-AIS contains highee byte of address. At the same time ALE is high Therefore Lower byte Of acidrens AG A? is selectesfiors ADO ADE + Since i memary reacy operation, HM (bar| gees Low + uring T2 AGE goes low, RD [tar pats low. Address removed (tom ADO.ADT and data 60-07 appears ‘on ADO-AD?. + Guring 13, Data remains wm ADO-AD7 till RO Ubar} is.at ow sige ‘Pest NnavMi Shethat CC Deparment [150007 ohm OceiOr and Inteststing cry| lew Order me Address wrote Memory Figure: Merny Mita Cale Mig Uued to send one Byte Into memory nvequires 1T-States During 11, ALE is high and cantaina Inver address AQ-AZ from AO-ADP. AB,AIS contains higher byte of adress As it sonemary cperaton, 1O/M (ba!) cers tow Dune 12, ALE gore Jaw, WR (bar) goes tow and Address is removed from AOO-ADT and thes data appears cn AD ABT. aga remains on ADO-ADF tl 8 (burl is tom taasa707 ropeocenior and tnterlacing a5Gout. 4~ Microprocessor Architecture als Generated tin 08! MACRARY 0 Vue | 0 | * tor’ 1 vow" 1 FALS32 eee Cente ognat Genetatnt HO eegure show that fous afferent coro! sitmal ate generated by combining IME signals RD fae, WEE bar are UM far The sipal KG/M [zat goes lew tor the riémery Operalen. thn. wenal it ANDO with RD (hae) and WE. bar npaaisb vung the 7ALS2 qua pe Pao) nowt OR Rates, shen tees 2 The OF pates ae funchanalty connected 4 nerative NAD gates, Wien bath eM! siprals go lew. the abut of the gates fa law and penevate EMR Char} and MEMY (bar) control Bn 2 When the S0/fet (tur) saral goes high, it ndicates the perpheral UO operation. cre snes iat tht ngnal a comelemerted uung the Hex esi 74I508 and Abed with th [por) onc WR bar signals to generate ¥OR (har) and ]OW (bar) central ign, T Prot gay Mt SAckit, CE Department | 2180207 ~Micteprocesnos and tntertas/ Ff Darshan yy, L Unit-4 - Assembly Language Program 1. BOSS instruction set, 31 Instruction, Description DATA TEANSE LR INSTRUCTIONS. _ 1 SMV Re, Ri ov fh ‘Ths instruction copies the contents of the source MOV ELC é Oe NL Hegester rate the destination register, the cenients.at MOV, M She sauice regster ate not allered if one af the opersads is a memory taextion, ts locaton Is specifies: by the contents of the ML regiters Frcove teuredvabe lated be ee, 2 avi Rd, gata” The at data ns stared in the destenation regeiter of WVEG, 97H MIB, data mn a memory ll the aperind a memary location, its MIM 7H location. 1 specitied by the contents of the HL daa acuamulele dock tegater: m 2. WDA 16-bit address ‘The contents of a memory lexatian, speciied by a 16 (0K 203¢H fat address in the operand, are copied to the . “ateumuiator. The contents of the saurce are rat Joe accumulate Gabeeck ——alteres 4 LOAKA/D Reg. pale The contents of the designated epster pais point te LAKE 3 memory location. This instruction copies the contests af ghat memary lecatign into the - accumulator, The cantents of either the cepister pair Load eps Pate teneedakd or the memary lecatan are nat atered. 1 nimeg- par, 16cit date The wsttuetion loads 26-bit data in the register pair UM. 203414 and HANES dlivect designated in the operand. nH, 208% G GHUD Lott arkdress ‘ine instruction copees the contents of the memory GHLG 20404 location pointed aut by the 16-bit address into register Land copies the contents of the neatmemary Jocatan inte register H. The contents ef source seyere qunmualakes duce memoryloration: we not tiered re 2 STA Libit address The ceatents of the accumulator are copied into the STA SIS0H femary tocatan specified by the operand. This 1s a F byte instruction, the second byte specifies the n- i feeder address and the thied byte specifies the high * yee eqeeumartader deeeh order address B SIAKAeg, pait The contents of the accumulator are copied into the | STAKE memory locatiar spegdied by he contents of the operand (repister pair), The contents ot the accumulates are net altered Pret WiayM.Shedhat, CE Ge partment | TESORO? ~ Microprocessor and Intertaci; : Unit-4 - Assembly Language Program St. Instruction. Ceseription Example i 3 SHLD 16-bit address The contents of register L are stored ita the memary SHLD 2470H Shoe HL Paw diveck location specified by the Lb-bit address in the ‘operand and the contents of H regater are stores into The next memory location by incrementing the aperand. The contents of registers HLare net altered, This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the pd Conkests of high-order address. 10 xCHG a The cantents of eegnter Hare exchanged with the XCHG | eerie eS vate contents of register D, and the contents of regster L are exchanged with the contents af repister E 1 SPHL ‘The instruction foads the eestents of tne and 1! SPHL | registers into the stack pointer rewster, the contents af The H register pravide the Ingh-order address and the contents af the | register provide the low-order address, The contents of the Hand L registers are mat altered 1a) KTHL Theontents of the Lregister are cxchanged with tne XTHL vi stack location pointed aut by the canteats of the stack pointer regster. The contents af the H register are exthanged with the next stack location (GB ths hawever, the contents of the stack pointer register are not altered. 13, PUSH Reg. pair ‘The contents of the cogiter paic desgnated inthe PUSH E operand are copied onta the stack in the foliowing PUSH A Sequence, The stack pointer repister is decremented and the contents of the high onde: register B, 0, M, A) are copied into that locaton, The stack pater register is decremented again and the contents of the low-arder rogister (C, E, L, flags} are copied to that tocation erday 1a POP Reg. pi The coments af the memory location pointed put by POP M the stack pointer register are copiet to the low-order PORA register (C, Et, status fags) of the operand, The stack pointer «. ncromonted ty t and the contents of that 7 sremory locavion am copied t6 the high order €7(B, ,M, A} of the operand. The stack pointer isagnin inceernented by 1. ‘The contents of the accumulator are co VO pot specified by the oporanc. The contents af the input port designated in the ‘Sperand are read and loaded inta the aceumulatar 15. OUT E-ba port addeess dinto the OUT FEH 16 NBR port address ea ARITHMETIC INSTRUCTIONS ‘Hol ViltyM. Shethar, CC Deparment | 2180707 ~ icroprocevar and intertong Ty f Darshan st. Instruction, aADDAL ADD 1B ADE R ADC Mt 19, ADIS-bt data 70. ACIB-bit data PL. DAD Reg. pair 22, UBER SUB Mt 23, S008 BBM Shekhat. CE Ocpanment Unit-4 ~ Assembly Language Program Description The centents of the operand (register ormemory] ate aitded 1e the contents of the accumulator and the results stared inthe accurmulatar. Whe ape-and os fmecnory letation, its location «6 specified by the contents of the Mk registers. All flags are meditied to relleet the result ot the add:tien ‘ne contents of the operand egster of memeryh and the Carry flag are added ta the contents of the accumplater ond the result is stared in the azeurulater, ifthe operand. a memary Pesation, ts locaticn 1s specitied by the sontents of the HL registers, all fags ate madified torefiect the result of the audition. “The f-but data [operand] «6 aeded to the contents of the accumulator and the cesuit 5 stored an the acumulater, All Flags are modified to reflect the result af the addition The 8:bt data (operand and the Carry flag are added no the contents of the accumulator and the eesult i stored in Ihe accumulator All flags are maditied to reflect the result of the addin ‘The 16-ba contents of the specified register pair are added to the cantents of the HL reg ster and the sum sstored in the HL register The contents at the souree regester pair are not alleres. Wthe result istarger than 16 bots, ho Cr Hlag is set. No ather (lags are alfected The contents af the operand [register or memany| are subtracted from the cantents af the accumulator, and the tesult is sioreriin the accumulatar. Ifthe operand 5 a meenory loration, ts lexation i speciied by the rontents of the Hi fogisters. All Mags are medslied 10 rellect the result of the subtraction. ‘The coments of the sperand (repister or memory] and the Borrow #lag are subtracted from the contents of the accumulator and the result i laced in the accumulator. the operand a memory locatien, ts Iccation o& specified by the contents of the HL registers. All flags are modified to reflect the result of the subtractian, 12189707 - ticeprocerton Example ADD B *DDM ance AGCM ADIs AC age DADH SUBB sua SBBB SBR MA{ Darsha 7 q mestge in | Unit-4 - Assembly Language Program se. Instruction Description Example 24. SUIS bitdata The S-bit data foperand| os subtracted from the SUI45H rantenté of the ageumulator and ihe 4eault is stored in the accumulatar, Alli Mags are modified to reflect the result of ction. 25. SBI Sbitdata The Stat data faperaed) 9nd the Borraw flag are SBI ASM wubrracted {rom the contents of the accurnulatar ahd tne resull stored in Ube accumulator, All Hogs are mmandified to reflect the result of the subtractian 26. INRR The contents of the dewgnated register er memory NEE ARR sre neremanted by 1 and the result is stored in the IHRM ‘ame place, (fthe operand ss 3. memory oration, iss Toeation is sperified by the contents of the HL regeters. 27, MKB The contents af the designated regsster pair are INAH incremented by Land the result it stated in the same place 28, GCRR ‘The cantents of the designated register or memory DCR B OCR M pe geeremented by ant the result is stored in thie BCR ME Same place, If he operand is.a memory Focasen, its facation is speciied bby the contents af the HL 5 registers 29. OOXR ‘The contents of the desigaated register pair are BCKH decremented by Land the result is stared in the same lace. 30. OAR The contents of the accumulatar are changed oma DAA binary value to twa d-but binary coded decimat [BCD} digits This i the anly struction that uses the auailary tlag to perform the binary to OCD conversion, and the conversion praceduee bb described belaw. 5, 2, AC, P, CY flags are altered 10 voflect the results af the operation HW the value ef the low-order 4. bits in the accumulator |g greater than 9 or if AC flag is set, the: is set, the instruction adds 6 to the bow order four Wis W othe value ef the Ingh-order 4-tas in the Stcumulatar is greater Than. or i the anor if the Carry flag is set, the insteuctian ads 6 10 the Bigh-order four bits Pref. Why. Shekhat. CE Department | F1b010) — Wl er me 7 pledetsoF an r i¢ Darshan | St, Instruction BRANCHING INSTRUCTIONS. 31. IMP AG tet address Jump canditianally 32. 1C 16-Ba adderess 33. INC AG-bit address 34 1P 16 bit adress, 35, 1M Let address 36. AZ 1e-nit address 37 INZ 16-bit address, 33. IPE Le-bit address 29, IPD 16bitaddress 40, CALL 16: ibaddress Coll gonditionally 41, CC AG-bit adeeess 42. CNE B6-tit address 43 CP Lib address 44. CM Lf-ba address 45. C2 bb address 46. CND 16-bit address 47, CPE Lott addteoss 48. CPO 16-bit address Unit-4 - Assembly Language Program Deesseipti jeseription pesmi ‘The program sequence is tanslerred 1a the memory IMP 201dH location specified by Uwe 16-bit address grvenin the IMP XTE operant The peagram sequence is transferred fa the mernary focation specified by the Té-bit cdctress given in the eperand based an the specified fag of the BSW descaied heiow Jump on Carry, Flag Status: O68 1 7080H Jumo on ao-Carry, Flag Status: C¥=0 anc 20504 Jump an pasitere, Flag Status: = yp asa Nionp on mirais, Flag Statue: $+} sm20smi Jueng cn cero, Flag Status! 292 FE 205DH Jump ono zero, Hage Status: 2° INE 20504 Jump on patity even, Flag Status: Pet SPE 20504 burn on parity bid, Flag Status: Pa JPO 2050H “The program sequence is transferred to the memory CALL 2OS4H location specified by the 1G-bie address given in the CALL XE operand. Gofore the transter, ine address of the rest instruction after CALL (the contents of the program counter] ispiushed-onte the stack {The srogrom sequence is transferred 40 the memory tocatian specified by the If-bit address given in the operand baved on the specified flog bf the PSU ar descuher below. Before the transfer, the address of the peat iestruction after the call the coatents of the arogram counter) is pushed onta the stock Calon Carry, Flag Status: OF=1 cc 20504 Call on no Carry, Flag Status: OF-0- NE 2050H Call on positive, Flag Status: $0 cr 2030H Call onvarumus, Flog Status: S*1. cm 20504 Call an tern, Flag Status: 2= C2 205eH Cation no eto, Flag Siatus 20 Nz 2050H Call en parity even, Flag Status: P21 che 20808 Call on panty odd, #ag Status: FeO PO 2050H Pref. ay M. Soebat, CL Department [2180107 — Microprocessor and tntertacing. q Darshan s Unit-4 - Assembly Language Program Se, Instruction: Description a9, RET eee War sequence vf tanglerred trem tne RET no to the calling pragtam, The twe bytes from the 10g of the stack are cogied mnto the pragrast ard program execution begins a Return from subroutine The progromsequence i tromsferveafram the wbrautine the <9 08 conditionally program based on the specified log of the PSI as described below The twa bytes flown the top of the stock are copied into the rogram “dounter, ond program erecufion begins at Ihe news wadress 50, RE Return on Carry, Flag Status: C72 Re St. RNC Return on no Carey, Flag Status: CF*5 ANC $2. ORF Retuen on postive, Flag Status 540 AP Sa ORM Returnon minus, Flag Status: S=1 RM 5a, RI etuin on ero, Flag Status: #41 a 48. BNE Return on.no tera, Flag Status: E BNE 96. APE Retuta on parity even, Flag Status: P2 RPE 87. RPO Return an parity odd, Flag Status: PO FO sa. PeML the contents of registers H and L are copied into the PCM. program counter, The contents af Hare placed at the Tigh-order tyte ara the comteats of Lax The FaWv> onderyte 55. RSTO? The RST imtruction gquiaient te a Lbyle call STS imation to one of eghE memory locations depending upes the number, The iesteuctions are frenerally used iA conjunction with internupts ard inserted using external hardware However these can be used as software instructors on a plagrare fo trars(er program execution te ane of the eight locations, the addresses are Instruction Restart Address RSID 0o00H wr ooagHt RST? oH RST 3 cones asta ooroH ABTS bg2gH RST ‘ozo ast? vous a eeeeSeSseree.saes— SPM Shekhat. CC Depanment | ZUR? - Micraprotesior and imtertacingDarshan Unit- 4~ Assembly Language Program St. Instruction Description The S085 has four adil wa The "3s four ediitiona} intesrupts. and these interrupts gener y Wis 60 ot seguir anyentemol eee PTS generate RST initructians internally ond TRAP it 40, Weestart trom address 0024H TRAP SL RST Waestart team addrass O02CH HORS. 62. RSTGS Aerestart fram address 0a34H 63. RST restart freew addrens QOL LOGICAL INSTRUCTIONS Bt CMP The contents of the aperanc (register ormemary)are CMP B cum compared with the contentsafthe accumulator Both CMP MA daHlentsare presemed. The result of the companson in shown by setting the flags.of the PSW35 totais: INA) = (regimen: carry Flog is set IAL = feeitenermy ora flag i set A 18)> leegimemt. carry and rere Mags are reset 65. CPL abit data The second byte [BE data) compared wth the CPLESH contents of the accumulator, The values being compared remain unchanged, The result of the comparisan is shown by setting the flags @f the PSM as Fallows: A (ap cata: carry Magis set fa} eave: zerootlagis set it (4) > data: carry and zero Nags are reset 66. ANAR The contents of the atcumulatar are logically ANDed ANA ANAM with the coments of the operand [register or ANAM mecnary}. a6 the result is laced sn the aceurmualator. HW the operand m # meenary location, its aildress is specified by the coments of HL registers. SZ, Pare modilied 10 reflect the result ef the aperataon. CY reset AC inset GP, Abi B-bit date ‘The contents of the aczumulater are logically ANDed AKI BGM ‘with the #-bit data (operand) and Voe resus placed ka the accumulator. 5, 2, P are modifved to reflect the Fesult of the Operation. CY is reset, AC is sei 6 RRA ‘The contents of the accuriulator are Exclusive ORE ARAB RAM with ihe contents of the operand (register or XRAM. memory], and ine result is placed in the accurmulater IF the operand is a ememory Sagaton, (1s address Is specified by the contents of HU registers. SZ, Pare modified to refiect the result of the aeration. C¥ and AC are reset. Pret ay Mt Shethat,cE Denariment | 2340707 - Mcraprocessor and interlacing 7q Darshan | Init-4 - Assembly Language Program St. Instruction : Dexctiption fain 69, KAI Bbicdata The xeniveiW dl wea ccumulater ive Exclusive ORed KAI SHH ‘with the 8-bit data (operand) and the results paced inthe accumulator $,2, P are moditied to vedleet the ‘sult of the operation. CY ard At arr reset The contents of the accurnulstor are topically GReé GRAB with the contents pl the operand Isegiiter or ORAM memary), and teresuites placeden ine accumwlator, the operand is a memary locabon, its adden is spocdes by the cantemts af ML regutors, 2, Pare modified to relied the result af he eperation. CY and AC are reset 70, OBA R ORAM. TA. ORI E-bit data The contents of the accumulator are logicaly ORed MIG with the &- bit data [operand] and the result is placed inthe accumulator. § 2, Pare moddhed to reflect the result of the aperation CY and AC ave reset. 72. RL Tach Binary bit of 1he accurmulater iy rotated lett by RUC ene position Bit OF is placedin the postion of OO as i well as on the Carey flag. C¥ is modified according 10 bit DP. §, 2, PAC are rat affected. 73, ARC Each binary bet of the accumulator is rotated right by ARC one position. Bit O is placed i the posiian of DT a \ well a5 in the Carry flag. C¥ is moditied according to | bit 00. §,2, PLAC are oat atfeered | Ta RAL Each binary bet of the accumulators rotated left by RAL | one position thiaugh the Carry flag. Bit DF is placed inthe Carry flag, ard the Carry flag placed 4n the feast dgnificant position GO. CV is modified according, yo b1D? $2, PAC are not attected. 7S, RAR Each binary bat the accumnglator is rotated night by RAR “qne pavilion through the Carry flag. Bit DO is placed in the Carry flag, and the Garry flag is placed in the most significant position OF C¥ is madified according ye bet OO. 4, 2, PAC are not affected. 76. CMA ‘The rontents of the accumwlater are camplemented, CM a flags are atfected ome the Carry tg 4 - Assembly Language Program BACK RAR, Rotate Accumulator Right though carry fag INC SHIP eB SOF DCR: Increment cf wish Is? RACE ar 13. Implement the Boolean equation D= [B+C) - E where B, C.D and E represents data in various registers of BOW MOV AD ORAL ANA E Mov DA wT 14. Write an 8085 assembly language program to add two decimal numbers using DAA instruction. Let 4 20500 Mov am ee Mov EM MVC OOH 008 DAL. Decenal adpustment of scewrruiator ret wen SPIN ncremens of C mil ee wav ise Move MutUnit-> - Assembly Language Program 15. Write an 8085 assembly Language program to find the minimum from two 8-bit numbers. MONE cba ronda oars Ye Aa STATI nut sara wo at sta 204aH rn 16. Write an 8085 program to copy block of five numbers starting from Jocations starting from J001h. 17. Anarray of ten data bytes 1 stored on memory locations 2100H onwards. Write an 8085 anembly Language program to fied the largest number and on memory locaton 22001.tot aps crcectngey i amet wor AM donb Done a oe vA at 10 Write an BOUS assembly Lamguage program to add block of B-bit numbers, (ab aces ae A 0 aR ace iba aw ahaa a. me nee ow ay ee program to count the length, location 2050h (More length in register Bi). tringUnit-5 - Assembly Language Program WNT BAC DERE wut 20. An array of ten numbers is stored from memory loration 2000H onwards. Write an 8085 assembly language program to separate out and store the EVEN and GDD numbers on new arrays from 2100H and 2200H. respectively. Lb os DODO un 7004 Uni 200 iy RH COUNTER STA 3000 Mow aM AMID INTCAREY wow ane stab wae ana rune CARRY UO AM Then Block ell are Oxegen STAKD on D AeMP Da 39006 ore a INK PAE COUNTER er 21. Anarray of ten data bytes is stored om memory locations 2100H onwards. Write an BORS auembly language program te find the bytes having complemented nibbles (eg. 2DH. 3CH. 7BH etc) and store them on anew array staring from memory locations 2200H cowards. ni 9300 Ux D 27006 CPIMEET « Weeenceae one earMVC OAM Loge: Mow A Mt ANLOFH MOV 8 & 4 Mov AM An Fes age RC. RAC BRE cre INT NEXT MOAN sTAKD ino Pept RC Iz 100 wT 22. respectively. bn 2600 Meda soo av BOO. wie Oo AODP: MOV AM Mee 1 FF Tenaitmant Write an BOBS assembly negative numbers, zeros, and to fis twenty bytes stored on memory locations 200 counts and the maximum number an memory nguage program to count the positive m {the maxinwm number from an HH onwards. Store the 1210107 - Micronrocewsor anc interiaeine mbers, ray of ¢ three locations 30011 to 3004H,Assembly Language Program FONEG Sh2 POS: ee OCR INT LOOP IMP STORE \ EG: INR D; Count Negative number \ UH pore gz [OOP snap STORE pos: INR E;Count Posting rumber | watt ry pcre nz LOOP IMP STORE STORE: MOW AE STA 3001 ova ST W002 bur 2000 mvic 14 vi 00 mvi8 00Unit-b — Asse é ssembly Language sav 00 Boage Program \oor 1: MOV AIM | Main Pragsam tor count 2era Ard Find Maximum CHAP BE sEZERO ome MAK, wa DERE wz LOOPL pap STORED ENO: WA D; For eaunt Tere INKH \ were wuz LOOP Ime STORER sax: Cee E thed Manimuet icsniP MOVER seam, Nm H otk yur oorl snap STORED STORLL: MOA DE syore Number of reo5 STA 3003 MOVAE 7A 2004 ; Store ensue ime 10Unit-5 ~ Assembly Language Program wir * : 23, Write am 8085 assembly language program t r RMD guage Program to separate out the munibers i : fom an array of ten numbers stored on memory locations 20004 onwards. Store the separated numbers on a new array from A000H onwards, vie 2000 wx D 3000 MLC OR LOOP: MOW AM cri aE WET JO NEXT ize INCNEAT SAK ac NEXT: INA HY; Skip Storing of Number BER E wn2LOOP mur 24, “Write an 8085 assembly language program sort an array of twenty bytes ‘stored on memory locations 20001 onwards in descending order. Myra ld LL 2000 MVECTT uo MovaM Ink HL CMP Mt HC SWAP BADE DERE JNEAL Sint Whe Mt theliaw Cenoamement 1 FISUIO?- Miroalocecmeand inlevanine T nw