CHAPTER 5

ARITHMETIC
CIRCUITS

Objectives

ƒ Half Adder and Full Adder

ƒ Parallel Adder and Subtractor

ƒ 2’s complement number

 Arithmetic Circuits 67

5.1 Binary Addition

Binary addition is performed in the same way as decimal addition except

that the values of individual digits can only be 0 or 1. The addition of a
one-bit number has 4 possible combinations as shown below.
A 0 0 1 1
+ B + 0 + 1 + 0 + 1
Carry → C S ← Sum 0 0 0 1 0 1 1 0

When adding a larger numbers that has multiple bits, it is still necessary
to add each pair of bits with a carry-in Cin. For example, A=1101 (13) and
B=0110 (6).
Cin Cin Cin Cin 1 1 0 0
A4 A3 A2 A1 1 1 0 1
+ B4 B3 B2 B1 + 0 1 1 0
Cout S4 S3 S2 S1 1 0 0 1 1

The 1s column is A1 + B1 producing the outputs Sum S1 and Carry Out

Cout. The carry out C0 is carried to 2s column as Cin. In the 2s column, we
have Cin + A 2 + B2 producing the outputs S2 dan Cout. The Co is carried to
the 4s column as Cin. In the 4s column, Cin + A3 + B3 = S3 and Cout . In the
last column 8s, Cin + A4 + B4 = S4 and Cout .

5.2 Half Adder and Full Adder Circuit

The 1s column adds 2 bits A + B and generates 2 outputs S and Co. This
is known as a half adder operation.

A Half S
Adder
B Co
68 Arithmetic Circuits

The half adder truth table and circuit are shown below.

A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S = A.B + A.B = A ⊕ B
C out = A.B

A
S
B

Cout

The 2s, 4s and 8s columns add 3 bits Cin + A + B and generates S and
Cout, which known as a full adder operation.

Cin S
Full
A Adder

B Co

The full adder truth table and circuit are shown below.

A B Cin S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Arithmetic Circuits 69

S = A.B.Cin + A.B.Cin + A.B.Cin + A.B.Cin

= A(B.Cin + B.Cin ) + A(B.Cin + B.Cin )
= A(B ⊕ Cin ) + A(B ⊕ Cin )
= A ⊕ B ⊕ Cin

Co = A.B.C in + A.B.Cin + A.B.Cin + A.B.Cin

= C in (A.B + A.B) + A.B.(C in + C in )
= Cin (A ⊕ B) + A.B

Cout
A
B

Cin S

5.3 Parallel Adder Circuit

To construct a 4 bit parallel adder, a single half adder and three full adder
circuits are used. The top half adder adds the 1s column ( A1 + B1 ) and
generates S1 and Co. The 2s, 4s and 8s columns use a full adder. Note
that the carry out Co is connected to the Cin of the next adder.

S1
Cin Cin Cin Cin
A1 Half
Adder A 4 A3 A 2 A1
B1 Co + B4 B3 B2 B1
Cout S4 S3 S2 S1
Cin S2
Full
A2 Adder

B2 Co

Cin S3
Full
A3 Adder

B3 Co

Cin S4
Full
A4 Adder

B4 Co
70 Arithmetic Circuits

7483 is a commercial 4-bit full adder. It has four full adders connected as
shown below. To perform a 4 bit addition, the Cin is connected to GND
(0).

74LS83A Cin = 0 S1
A4 Full
A3
A2 A2 Adder
A1 s4
B4 s3 B2 Co
B3 s2
B2 s1
B1
Cin Cout
Cin S2
Full
A2 Adder

B2 Co

Cin S3
Full
A3 Adder

B3 Co

Cin S4
Full
A4 Adder

B4 Co

An 8-bit parallel adder is constructed using two 7483 ICs. The Cout of the
first IC is connected to the Cin of the preceding IC.

74LS83A
A4
Cin = 0 A3
A2
A1 s4
A8 A7 A6 A5 A 4 A3 A 2 A1 B4
B3
s3
s2
B2 s1
B8 B7 B6 B5 B4 B3 B2 B1 B1

Cout S8 S7 S6 S4 S4 S3 S2 S1 Cin Cout

74LS83A
A4
A3
A2
A1 s4
B4 s3
B3 s2
B2 s1
B1
Cin Cout
 Arithmetic Circuits 71

5.4 Signed Numbers

A binary number can be represented as either a positive or a negative
value. The common representation of signed numbers is either in the form
of sign-magnitude or in the form of 2’s complement.

In a sign-magnitude system, a number consists of two parts, the

magnitude and the sign. A 0 signifies a positive number and a 1 signifies
a negative number. An n bit sign-magnitude number could represent
integers ranging from –(2n-1-1) to +(2n-1-1). A 4 bit sign-magnitude ranges
from -7 to +7. Note that, there two possible representations of zero: -0 and
+0. Thus +6 (0110) and -6 (1110) differ only in the sign bit.

The sign-magnitude representation is not commonly used in practice for

representing integer numbers. It requires arithmetic circuit that are most
costly and slower computation time. The addition and subtraction of sign-
magnitude numbers requires the comparison of signs and magnitude.

Signed Decimal Sign-magnitude

+7 0111
+6 0110
Sign bit magnitude +5 0101
+4 0100
+3 0011
+2 0010
+1 0001
+0 0000
-0 1000
-1 1001
-2 1010
-3 1011
-4 1100
-5 1101
-6 1110
-7 1111
72 Arithmetic Circuits

5.5 Two’s Complement Number

The complement number system was invented to make addition and

subtraction faster and easier, by omitting the need for compare sign and
magnitude comparison. Instead it requires complementation which can be
performed quite efficiently on binary numbers.

In 2’s complement number system, a positive number is represented in

the same fashion as in a sign-magnitude number. For example, + 6 = 0110 .
A negative number is represented in its 2’s complement form. For
example, − 6 = 1010 .

An n bit 2’s complement number could represent integers ranging from

− 2 n −1 to + 2 n −1 − 1 . A four bit 2’s complement number ranges from -8 to +7.

0 1 1 0 Signed Decimal 2's complement

+6 =
+7 0111
+6 0110
Sign bit magnitude +5 0101
+4 0100
+3 0011
+2 0010
-6 = 1 0 1 0 +1 0001
+0 0000
Sign bit 2's complement -8 1000
-7 1001
-6 1010
-5 1011
-4 1100
-3 1101
-2 1110
-1 1111

A negative number in 2’s complement is obtained from a positive number

by complementing each bit including the sign bit and then adding 1 to it.
The carry that occurs out of the MSB is discarded. As an example, the 2s
complement for -6 is illustrated below:
Arithmetic Circuits 73

0110 Binary equivalent of +6

1001 Complement each bit to form 1's complement
+1 Add 1 to form 2's complement
1010 2's complement for -6

Example 1: Find the 2’s complement number for +30 and -30.

a. The magnitude for +30 is 10110. Attach sign bit = 0

2s complement for + 30 = 010110

b. 2s complement for -30 = 101010

010110 Binary equivalent of +30
101001 1's compelement
+1 add 1
101010 2's complement

Example 2: Show how an 8-bit computer would represent a 2’s

complement number for +30 and -30.

a. 2s complement for + 30 using 8 bit = 00010110

b. 2s complement for -30 = 11101010

00010110 Binary equivalent of +30
11101001 1's compelement
+1 add 1
11101010 2's complement

Example 3: Determine the decimal value for the following 2’s complement
number: a. 00100010 b. 00100010 c. 11111111

a. From the sign bit, 00100010 is a positive number. The decimal value is
+34.

b. From the sign bit, 10100010 is a negative number. Complement each

bit and add 1. The decimal value is -94.
74 Arithmetic Circuits

10100010
01011101 Complement each bit
+1
01011110 Decimal value = -94

c. From the sign bit, 11111111 is a negative number. Complement each

bit and add 1. The decimal value is -1.

11111111
00000000 Complement each bit
+1
00000001 Decimal value = -1

The number of bits available in the computer’s arithmetic unit, limits the
range of numbers that can be represented in the machine. Numbers that
fall outside this range cannot be handled by the system. Machines that
uses 2’s complement number system can represent integers in the range
− 2 n −1 ≤ N ≤ 2 n −1 − 1
where n is the number of bits available for representing N. If an operation
produces a result that falls outside the available range, than an overflow
occurs.

Example 1: Determine the range of integers that can be represented in

the 2’s complement number system having n bits:
a. n= 8 bit b. n=16 bit c. n= 32 bit

a. - 28-1 to + 28-1 -1 : -128 (10000000) to +127 (01111111)

b. - 32,768 to + 32,767
c. – 2,147,483,648 to 2,147,483,647
 Arithmetic Circuits 75

5.6 Two’s Complement Arithmetic

We will now learn how to add and subtract using 2’s complement system.
Four cases will be considered: A+B, A-B, -A+B and –A-B.

Case 1: A+B Two positive numbers.

Since both A and B are positive, the result will also be positive. So, there
is no need to use the 2’s complement.

Example 1: 2+ 4 = +6

sign bit
↓
0 0 1 0
+ 0 1 0 0
0 1 1 0

Example 2: 9+4 = +13

sign bit
↓
0 1 0 0 1
+ 0 0 1 0 0
0 1 1 0 1

There are cases when an operation produces a result that exceeds the
range of the number system, producing a condition known as overflow.
When we add two numbers with the same sign, which produce a sum that
is larger than the largest representable number, we can obtain an
incorrect result. As a rule, addition overflow occurs whenever the sign of
the sum is different from the signs of both addends.

Example 1: 6+3=-7
sign bit
↓
0 1 1 0
+ 0 0 1 1
1 0 0 1
76 Arithmetic Circuits

The result 1001 is interpreted as -7. The sign bit shows that it is a
negative number. The correct answer is +9, which is outside the 4-bit 2’s
complement range [-8,+7]. Hence an overflow condition has occurred. The
sum of the two given numbers requires more than the allotted 4 bits to
represent it.

Example 2: 12+7 = -13

sign bit
↓
0 1 1 0 0
+ 0 0 1 1 1
1 0 0 1 1

The result 10011 is interpreted as -13. The correct answer is +19, which
is outside the 5-bit 2’s complement range [-16,+15]. The sum of the two
given numbers requires more than the allotted 5 bits to represent it.

Example 3: Compute 6+3 using 5 bits.

sign bit
↓
0 0 1 1 0
+ 0 0 0 1 1
0 1 0 0 1

The range for a 5-bit 2’s complement is [-16,+15]. Since the sign bit is 0, it
correctly represents the desired answer which is interpreted as +9.

Example 4: Compute 12+7 using 6 bits.

sign bit
↓
0 0 1 1 0 0
+ 0 0 0 1 1 1
0 1 0 0 1 1
 Arithmetic Circuits 77

The range for a 6-bit 2’s complement is [+32,-31]. Since the sign bit is 0, it
correctly represents the desired answer which is interpreted as +19.

Example 5: Compute 19+27 using 2’s complement system.

The sum is +46 which requires at least 7 bits, where the range for a 7-bit
2’s complement is [-64,+63].

sign bit
↓
0 0 1 0 0 1 1
+ 0 0 1 1 0 1 1
0 1 0 1 1 1 0

Case 2: -A-B Two negative numbers.

Both –A and –B will be represented by the 2’s complement and the

computation will be performed as (-A) + (-B).

Example 1: -3-2 = +6

− 3 = −(0011) → 1100 + 1 = 1101

− 2 = −(0010) → 1101 + 1 = 1110

Adding two negative numbers will generate a negative sum as indicated by

the 1 sign bit. We ignore the carry beyond the sign bit. Therefore, the
result is 1011 = -5.

sign bit
↓
1 1 0 1
+ 1 1 1 0
1/ 1 0 1 1
78 Arithmetic Circuits

Example 2: -12-5
The sum is -17 which requires 6 bits. The range for a 6-bit 2’s
complement is [-32,+31].

− 12 = −(001100) = 110011 + 1 = 110100

− 5 = −(000101) = 111010 + 1 = 111011

The result is 101111 = -17.

1 1 0 1 0 0
+ 1 1 1 0 1 1
1/ 1 0 1 1 1 1

Suppose we use 5 bits to compute -12-5, the answer is 01111 = +15. Note
that the sign bit (0) is incorrect, indicating an overflow. The desired result
(-17) exceeds the number range for a 5-bit 2’s complement [-16,+15].

− 12 = −(01100) = 10011 + 1 = 10100

− 5 = −(00101) = 11010 + 1 = 11011

1 0 1 0 0
+ 1 1 0 1 1
1/ 0 1 1 1 1

Case 3: A-B

The positive number A is unchanged, however B is represented in 2’s

complement form.

Example 1: 3-2 =

+ 3 = 0011
− 2 = −(0010) → 1101 + 1 = 1110

Add the two numbers. Ignore the carry beyond the sign bit. The result is
0001 = +1.
sign bit
↓
0 0 1 1
+ 1 1 1 0
1/ 0 0 0 1
Arithmetic Circuits 79

Example 2: 12-5

+ 12 = 01100
− 5 = −(00101) → 11010 + 1 = 11011

The answer is 00111 = +7.

sign bit
↓
0 1 1 0 0
+ 1 1 0 1 1
1/ 0 0 1 1 1

Example 3: 5-12

+ 5 = 00101
− 12 = −(01100) → 10011 + 1 = 10100

The answer is 11001 = -7.

sign bit
↓
0 0 1 0 1
+ 1 0 1 0 0
1 1 0 0 1

Case 3: -A+B

− 3 = −(0011) → 1100 + 1 = 1101

+ 2 = 0010

Add the two numbers. Ignore the carry beyond the sign bit. The result is
1111 = -1.
sign bit
↓
1 1 0 1
+ 0 0 1 0
1 1 1 1
80 Arithmetic Circuits

5.7 Subtractor Circuit

The 4-bit parallel adder can be modified slightly to form a subtractor

circuit. Subtraction S= A-B in the 2’s complement number system is
performed as follows:
S=A−B
= A + B +1

The 2’s complement for B is obtained by complementing each bit and then
adding 1 to the LSB.

A 4 A3 A 2 A1
B4 B3 B2 B1
+ 1
S4 S3 S2 S1

A 4-bit subtractor circuit is shown below. The 2’s complement is formed

by the inverters on the B input and adding Cin = 1 to the LSB. The MSB
(A4, B4 and S4) is used for the sign bit and the C4 output is not used.

Cin= 1 S1
Full
A1 Adder Co
B1

Cin
S2
A2 Full
Co
B2 Adder

Cin
Full S3
A3 Adder Co
B3

Cin
Full S4
A4 Adder
B4
Arithmetic Circuits 81

The diagram shown below is a 4-bit subtractor circuit using a 7483 adder
and NOT gates.

Sign Bit
1 7 4 2 1
4321 4321
74LS83A
A4
A3
A2
A1 s4
B4 s3
B3 s2
B2 s1
B1
Cin Cout Ignore C4

5V

This circuit can only accept values between -7 (1001) and +7 (0111), and
the result is also limited to values between -7 to +7. Some arithmetic
operation can result in an overflow condition if the output result is
beyond the range of valid numbers.

Example 1: 7-1=6

A=7 → 0 1 1 1 → 0 1 1 1
B =1 → 0 0 0 1 → 1 1 1 0
Cin = 1 → + 1 → + 1
0 1 1 0

Example 2: 7-0=7

A=7 → 0 1 1 1 → 0 1 1 1
B=0 → 0 0 0 0 → 1 1 1 1
Cin = 1 → + 1 → + 1
0 1 1 1
82 Arithmetic Circuits

An 8-bit subtractor circuit is constructed by connecting two 4-bit

subtractor circuit. The output of C4 is connected to the Cin of the
preceding subtractor. This circuit can compute values between -127 to
+127.

74LS83A
A4
A4..A1 A3
A2
A1 s4
B4 s3 S4..S1
B3 s2
B2 s1
B1
B4..B1
Cin Cout

5V 74LS83A
A4 S8:Bit tanda
A3
A8..A5 A2
A1 s4
B4 s3 S8..S5
B3 s2
B2 s1
B1
B8..B5
Cin Cout Abaikan

This circuit can accept values between -127 (10000001) and +127
(01111111), and the result is also limited to values between -127 to +127.

Example 1: 127-0=127

A = 127 → 0 1 1 1 1 1 1 1
B=0 → 0 0 0 0 0 0 0 0
Cin = 1 → + 1

0 1 1 1 1 1 1 1
→ 1 1 1 1 1 1 1 1
+ 1
0 1 1 1 1 1 1 1
 Arithmetic Circuits 83

Example 2: 7-1=6

A=7 → 0 0 0 0 0 1 1 1
B =1 → 0 0 0 0 0 0 0 1
Cin = 1 → + 1

0 1 1 1 1 1 1 1
→ 1 1 1 1 1 1 1 0
+ 1
0 0 0 0 0 1 1 0

5.8 Adder-Subtractor Circuit

The 4-bit adder and subtractor circuits are almost identical. These
circuits can be combined to form an adder-subtractor circuit. The circuit
has an additional input called the control input. If the control input is 0,
the circuit performs addition, A + B + 0 , where Cin=0. If the control input
is 1, the circuit performs subtraction A + B + 1 , where Cin=1.

Cin
S1
Full
A1 Adder Co
B1 ?

Cin
Full
S2
A2 Adder Co
B2 ?

Cin
S3
Full
A3 Co
Adder
B3 ?

Cin
Full
S4
A4
Adder
B4 ?

Control
84 Arithmetic Circuits

Control Y
B ?
Y
Add 0 B
Subtract 1 B
Control

From the truth table, we can write the expression as:

Y = B.Control + B.Control = B ⊕ Control

B
Y

Control

The 4 bit adder-subtractor circuit is shown below. When the control input
is 1, the input Cin=1 and the XOR gate will act as inverter to perform
subtraction. When the control input is 0, the input Cin=0 and the XOR
gate has no effect on B.

Cin
S1
Full
A1 Adder Co
B1

Cin
Full
S2
A2 Adder Co
B2

Cin
Full
S3
A3 Adder Co
B3

Cin
Full S4
A4 Adder
B4

Control
 Arithmetic Circuits 85

Exercises

1. Simplify the full adder expressions using Karnaugh Map.

S=A⊕B⊕C
Co = Cin (A ⊕ B) + AB

2. Convert the decimal numbers to an 8-bit 2’s complement number.

a. 7 b. -7 c. 36 d. -48

3. Convert the 2’s complement numbers to a decimal.

a. 0001 0110 b. 0000 1111 c. 1110 1110 d. 1111 1111

4. What is the range for a 32-bit 2’s complement number?

5. Perform the arithmetic operation using a 4-bit 2’s complement

number.

a. 3+1 b. 7 - 6 c. 6 - 7 d. –3 –2

6. Perform the arithmetic operation using an 8-bit 2’s complement

number.
a. 3+1 b. 7 – 6 c. 6 –7 d. 20 – 12 d. –3-2

7. Perform arithmetic addition for 112 + 32 using an 8-bit 2’s

complement number Why is the answer wrong?

8. Which if the following does not represent an 8-bit 2’s complement

number.
a. 89 b. 135 c. -107 d. -144

9. Represent each of the following decimal numbers in 2’s complement.

Use 8 bits including the sign bit.
a. +32 b. +127 c. -14 d. 0 e. -3