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Design and Analysis of Two-Stage Operational Transconductance Amplifier

(OTA) using Cadence tool

Article · April 2008

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 International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 4, April 2014)

Design and Analysis of Two-Stage Operational

Transconductance Amplifier (OTA) using Cadence tool
O. M. Saravanakumar1, N. Kaleeswari2, K. Rajendran3
1,2
Department of ECE, Karpagam University, Coimbatore
3
Departments of Electronics, Government Arts College, Kulithalai
Abstract - This paper presents the design and analysis
two-stage operational transconductance amplifier (OTA)
for use in switched-capacitor (SC) circuits. The existing
design methods for two-stage OTAs often lead to sub
optimal solutions because they decouple inter-related
metrics like noise and settling performance. In our
approach, the cadence tool is used to analysis the transient
response, AC response and phase plot of the OTA and
settling time has been observed on the simulation. For the
optimization routine, there is no need to interface with a
circuit simulator because all significant devices parasitic are
included in the tool. The simulation results show that a 90-
nm prototype amplifier achieves the settling time of 1.6 ns
with reduced integrated noise while consuming 2.4 mW
Fig.1 Ideal OTA
from a 1.2V power supply with phase plot for 175 degree.
The ideal transfer characteristic is therefore
Index terms: - Two stage OTA, transient response, 90nm,
power, cadence tool Iout = gm (Vin+ − Vin−) (1)
Or, by taking the pre-computed difference as the input,
I. INTROUDUCTION
Due to recent development in VLSI technology the Iout = gm * Vin (2)
size of CMOS decreases and power supply also With the ideally constant transconductance gm as the
decreases. The OTA is a basic building block in most of proportionality factor between the two. In reality the
analogue circuit with linear input-output characteristics. transconductance1 is also a function of the input
The OTA is popular for implementing voltage controlled differential voltage and dependent on temperature. To
oscillators (VCO) and filters (VCF) for analog music summarize, an ideal OTA has two voltage inputs with
synthesizers, neural networks and instrumentation infinite impedance (i.e. there is no input current). The
amplifier because it can act as a two-quadrant multiplier common mode input range is also infinite, while the
[1]. Fast, high gain operational-transconductance- differential signal between these two inputs is used to
amplifiers (OTAs) are an integral part of switched- control an ideal current source (i.e. the output current
capacitor (SC) circuits [2]. The primary application for does not depend on the output voltage) that functions as
an OTA is however to drive low-impedance sinks such as an output. The proportionality factor between output
coaxial cable with low distortion at high bandwidth. The current and input differential voltage is called
OTA has been traditionally implemented using a cascade transconductance [5].
of two stages to provide a high gain. Scaling dimensions The paper is organized as follows. In Section II, we
in CMOS technology requires proportional scaling in start by discussing why closed form symbolic
supply voltage as well. Though lower supply voltages expressions are important for analog design automation
result in lower power consumption, as the supply currents and optimization. In Section III, we describe the two-
[3]. Improving the settling performance by Phase-margin stage OTA specifications, schematic, and behavioral
adjustments has been proposed in the literature. model. Conclusions are provided in Section VI.
However, for two-stage amplifiers, better phase margin
does not always imply faster settling [4]. An OTA is a II. ANALOG DESIGN AND OPTIMIZATION USING
voltage controlled current source, more specifically the C ADENCE T OOL
term ―operational‖ comes from the fact that it takes the
For larger circuits, symbolic analyzers and/or
difference of two voltages as the input for the current
simulators can be used to perform the automated design
conversion.
and optimization.

192
 International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 4, April 2014)
The gradients and Hessian matrices can be found by III. T WO-STAGE OTA DESIGN AND OPTIMIZATION—
two methods. The optimization algorithm can perturb MODEL DESCRIPTION
each variable and use the simulator to evaluate the In this section, we describe the model used for the
objective and constraints and then compute the gradients design and optimization two-stage OTA using cadence
and Hessians using finite differences (a slow process), or tool. The CMOS level implementation of the OTA is
simply use the symbolic model to find the gradients shown in Fig. 3.
directly by differentiation over the closed form
expressions of the objective and constraints (a fast
process).

Fig.2. Analog design automation and optimization.

Sometimes, the optimizer can reach a design point that

is feasible, but finite differences around lead to an Fig. 3. Design of two stage OTA using cadence
infeasible point, causing the optimizer to diverge or halt We start with a list of specifications summarized in
prematurely. In such cases, providing gradients and Table I. These assumed values are for a typical 3 stage
Hessians directly from closed form expressions allows OTA gain stage clocked at 1Hz to 125 MHz, which finds
the optimizer to converge to a solution [6], [7]. applications in pipelined ADCs and SC delta-sigma
A typical design optimization loop is shown in Fig. 2. modulators. The dynamic error specification of 0.1
The design starts with a certain set of specifications and a implies that the output should settle to within± 0.1% of
starting point. The performance metrics are evaluated at the final steady state value within 1.6 ns (1/2 clock cycle)
the current design point. This can be done by going back when the supply voltage is given as 1.2V.
to the simulator, which is a very slow process. By using
CMOS M1: The lowest common-mode input voltage,
a complete symbolic model in cadence tool, which is
Vcm; min imposes the toughest constraint on CMOS M1
faster than the previous. The optimization algorithm then
remaining in saturation. CMOS M2: The systematic
changes the design point to make sure that the objective
offset condition makes the drain voltage of M1 equal to
converges to the optimum and the constraints are met.
the drain voltage of M2. Therefore, the condition for M2
We thus conclude that finding the gradient using finite
being saturated is the same as the condition for M1 being
differences can be time consuming, can lead to inaccurate
saturated. Note that the minimum allowable value Vcm;
results, and may even cause the optimizer to fail. This
min is determined by M1 and M2 entering the linear
can be especially problematic when the optimizer needs
region. CMOS M3: Since Vgd3=0 CMOS M3 is always in
to be run multiple times with new starting points, in order
saturation and no additional constraint is necessary.
to find the globally optimal design point. Each optimizer
CMOS M4: The systematic offset condition also implies
run itself involves multiple transient, noise, and ac
that the drain voltage of M4 is equal to the drain voltage
simulations. This leads to impractically long run times if
of M3. Thus M4 will be saturated as well. CMOS M5:
a circuit simulator is used, even for small and medium
The highest common-mode input voltage, Vcm; max,
sized circuits. All these problems can be overcome if
imposes the tightest constraint on CMOS M5 being in
closed form symbolic expressions are available and are
saturation the maximum allowable value of Vcm; min is
used for generating the gradients and Hessians. Such
determined by M5 entering the linear region. CMOS M6:
expressions speed up computer-based optimizations, and
The most stringent condition occurs when the output
can sometimes provide designers with design in-sights
voltage is at its minimum value Vout; min. CMOS M7:
and trade-offs, letting them make intelligent design
For M7, the most stringent condition occurs when the
choices. Designers can use closed form equations to
output voltage is at its maximum value Vout; max. CMOS
analyze a circuit and prepare a fixed design plan that can
M8: Since Vgd8=0, CMOS M8 is always in saturation
be used for the knowledge-based approach to analog
[9].The amplfied output (Vout) on the final stage is shown
design automation [8].
in the Fig.4.
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 International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 4, April 2014)
The output voltage is lies between the 1.0725V and In addition, due to voltage headroom constraints, it has
1.0825V. So that the low power is consumed while apply become increasingly difficult to use cascoding as a
the frequency 31.974KHz The transient response and the solution to this problem. Thus, as an alternative, it is
phase shift on the different node is clearly shown on the attractive to consider cascades of more than two
netlist files respectively. common-source stages to achieve high dc gain [10].

Fig.6. CMOS intrinsic gain on various size nm

Fig.4. Amplified output on cadence tool

Since the AC frequency response is an important

factor for any amplifier which helps to calculate the
bandwidth and the gain. The AC frequency response is
remaining constant up to the 10MHz and the maximum
voltage on the frequency response is about 5.03mV. By
operating all CMOS in to saturation region power
consumption and slew rate is reduced but GBW product
remains constant. The simulated output frequency
response is shown in Fig.5. If the OTA is designed on the
130nm and 180nm level the intrinsic gain has been
increased 30 and nearby 50 respectively. In this approach Fig.7. Phase plot AC response for 2 stage OTA
the OTA is designed in the level of 90nm on cadence The AC response phase plot of the designed OTA is
tool. shows in the Fig.7 which deals with the degree of 175
while applying the input voltage as DC 2V. The phase
can be decayed while it reaches the frequency is about
the 10MHz.

IV. CONCLUSION
TABLE I
Comparison of Parameters

Parameters Existing Proposed

(cadence)
Technology 350nm 90nm
Number of
CMOS used 9 9

Settling time <2.5ns Around 1.6ns

Fig.5. AC response of two stage OTA
Power 3.4mW 2.4mW
The intrinsic gain of the CMOS used in these AC response Gain plot
Gain plot constant
amplifiers has reduced dramatically due to technology constant
up to 10MHz
scaling (gm*r0 >15 for 90-nm CMOS). The VDS is up to 1MHz
reduced when the OTA is designed on the 90nm level is Phase - Shows 175 deg
shown on the Fig.6.

194
 International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 4, April 2014)
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