COA_ESE Question Bank

Module_1
1. Explain any 2 addressing modes in 8086 Microprocessor.(2m)

 Immediate Addressing Mode: In this mode, the operand is specified explicitly in the
instruction itself. For example, in the instruction MOV AX, 1234H, the value 1234H is the
immediate data that will be moved to the AX register.

 Register Addressing Mode: This mode involves the operand being located in a register.
The instruction specifies the register in which the operand is located. For example, in the
instruction MOV AX, BX, the content of the BX register is moved to the AX register.

2. Compare the Computer organization and architecture(4m)

S.
No. Computer Architecture Computer Organization

Architecture describes what the The Organization describes how it

1. computer does. does it.

Computer Architecture deals

Computer Organization deals with a
with the functional behavior of
structural relationship.
2. computer systems.

In the above figure, it’s clear In the above figure, it’s also clear
that it deals with high-level that it deals with low-level design
3. design issues. issues.

Architecture indicates its Whereas Organization indicates its

4. hardware. performance.

As a programmer, you can view

architecture as a series of The implementation of the
instructions, addressing modes, architecture is called organization.
5. and registers.

For designing a computer, an

For designing a computer, its
organization is decided after its
architecture is fixed first.
6. architecture.

Computer Architecture is also

Computer Organization is frequently
called Instruction Set
called microarchitecture.
7. Architecture (ISA).
S.
No. Computer Architecture Computer Organization

Computer Architecture
comprises logical functions such Computer Organization consists of
as instruction sets, registers, physical units like circuit designs,
data types, and addressing peripherals, and adders.
8. modes.

The different architectural

categories found in our CPU organization is classified into
computer systems are as three categories based on the
follows: number of address fields:
1. Von-Neumann Architecture 1. Organization of a single
2. Harvard Architecture Accumulator.
3. Instruction Set Architecture 2. Organization of general registers
4. Micro-architecture 3. Stack organization
9. 5. System Design

It makes the computer’s It offers details on how well the

10. hardware visible. computer performs.

Architecture coordinates the Computer Organization handles the

hardware and software of the segments of the network in a
11. system. system.

The software developer is It escapes the software

12. aware of it. programmer’s detection.

Examples- Intel and AMD Organizational qualities include

created the x86 processor. Sun hardware elements that are invisible
Microsystems and others to the programmer, such as
created the SPARC processor. interfacing of computer and
Apple, IBM, and Motorola peripherals, memory technologies,
13. created the PowerPC. and control signals.

4. Draw and explain the Architecture of 8086 microprocessor. (8m)

 The internal architecture of the Intel 8086 microprocessor is divided into two main
units: the Bus Interface Unit (BIU) and the Execution Unit (EU). These units work
together to ensure efficient processing and execution of instructions. Here is a detailed
explanation of the architecture:
The Bus Interface Unit (BIU)
The BIU provides the interface of the 8086 to external memory and I/O devices via
the System Bus. It performs machine cycles such as memory read, I/O read, etc., to
transfer data between memory and I/O devices.
Components of the BIU:
 Segment Registers:
o Code Segment Register (CS): Holds the base address for the code segment
where program instructions are stored.
o Data Segment Register (DS): Holds the base address for the data segment.
o Stack Segment Register (SS): Holds the base address for the stack segment.
o Extra Segment Register (ES): Holds the base address for the extra segment.
 Instruction Pointer (IP): A 16-bit register that holds the offset of the next instruction
to be executed in the code segment.
 Address Generation Circuit: Uses the formula Physical Address = Segment Address
× 10H + Offset Address to calculate the 20-bit physical address.
 6-Byte Pre-fetch Queue: Stores up to 6 bytes of prefetched instructions to improve
processing speed by overlapping fetching and execution.
2. The Execution Unit (EU)
The EU is responsible for decoding and executing instructions fetched from the pre-
fetch queue by the BIU.
Components of the EU:
 General Purpose Registers:
o AX (Accumulator): Used for arithmetic, logic, and data transfer operations.
 o BX (Base): Used for indexed addressing.
o CX (Count): Used as a counter in loop operations.
o DX (Data): Used for I/O operations and as an extension of AX in some
arithmetic operations.
 Pointer and Index Registers:
o SP (Stack Pointer): Points to the top of the stack.
o BP (Base Pointer): Used to access stack segments.
o SI (Source Index) and DI (Destination Index): Used for indexed addressing
and string operations.
 Arithmetic Logic Unit (ALU): Performs arithmetic and logic operations.
 Flag Register: Contains status flags that reflect the outcome of operations, such as
Zero Flag (ZF), Carry Flag (CF), Sign Flag (SF), and Overflow Flag (OF).
 Instruction Register and Decoder: Holds the current instruction and decodes it into
control signals for execution.
 Control Unit: Directs the operations of the EU and manages the timing and control
signals.
Special Purpose Registers:
 Stack Pointer (SP): Points to the top of the stack, used during instructions like PUSH
and POP.
 Base Pointer (BP): Holds the base address of the stack segment.
 Source Index (SI) and Destination Index (DI): Used for string operations.
3. Decode Unit and Control Unit
Decode Unit:
 The Decode Unit decodes fetched instructions into micro-operations that the
Execution Unit can execute.
 Translates complex instructions into simpler operations.
Control Unit:
 Manages the overall operation of the microprocessor, coordinating the activities of the
BIU and EU.
 Responsible for fetching, decoding, and executing instructions, as well as handling
interrupt requests.
4. Data Buses
Address Bus: 20-bit wide, used to address up to 1MB of memory. Data Bus: 16-bit
wide, used to transfer data between the microprocessor and memory. Control Bus:
Carries control signals such as read, write, and interrupt requests.

5. Explain features 8086 Microprocessor. .(2m)

 It has an instruction queue, which is capable of storing six
instruction bytes from the memory resulting in faster
processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit
registers, internal data bus, and 16-bit external data bus
resulting in faster processing.
 It is available in 3 versions based on the frequency of
operation −
o 8086 → 5MHz
 o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute
Stage, which improves performance.
 Fetch stage can prefetch up to 6 bytes of instructions and
stores them in the queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.

6. Explain The Von Neumann Model in detail. . (4m)

The Von Neumann architecture is a computer design model that uses a single storage
structure to hold both instructions and data. This architecture forms the basis of most
computer systems in use today. It comprises the following main components:
1. Central Processing Unit (CPU)
The CPU is the part of the computer responsible for executing instructions and
performing the bulk of data processing. It consists of three main sub-components:
 Arithmetic and Logic Unit (ALU):
o The ALU performs arithmetic operations (like addition and subtraction) and
logical operations (like AND, OR, and NOT). It is the computational core of
the CPU, enabling the execution of mathematical and logical instructions.
 Control Unit (CU):
o The CU directs the operations of the CPU by controlling the movement of data
and instructions between other components. It interprets the instructions from
memory and initiates the necessary actions to execute them. The CU includes:
  Program Counter (PC): Holds the address of the next instruction to
be executed.
 Instruction Register (IR): Stores the current instruction being
executed.
 Registers:
o Registers are small, fast storage locations within the CPU used to hold
temporary data and instructions. Key registers include:
 Memory Address Register (MAR): Holds the address of the memory
location to be accessed.
 Memory Data Register (MDR): Holds the data being transferred to or
from memory.
 Accumulator (AC): Holds intermediate arithmetic and logic results.
 Program Counter (PC): Contains the address of the next instruction
to be executed.
 Current Instruction Register (CIR): Holds the current instruction
during processing.
2. Buses
Buses are communication pathways that transfer data and signals between different
components of the computer. The Von Neumann architecture uses three types of
buses:
 Address Bus:
o Carries memory addresses from the CPU to other components, indicating
where data should be read from or written to.
 Data Bus:
o Transfers actual data between the CPU, memory, and I/O devices. It is bi-
directional, allowing data to flow in both directions.
 Control Bus:
o Transmits control signals from the CPU to other components. These signals
coordinate and manage the operations of the computer, such as read/write
commands and interrupt requests.
3. Memory Unit
The memory unit stores both instructions and data required by the CPU. It consists of:
 Random Access Memory (RAM):
o Volatile memory used for temporary storage of data and instructions that are
currently being processed. Data is lost when the power is turned off.
 Read-Only Memory (ROM):
o Non-volatile memory used for permanent storage of instructions that are not
intended to be altered, such as the system's firmware.

8. Describe the following performance measures:

1) Cycles Per Instruction(CPI) 2) Efficiency 3) Speed up 4) Throughput (4m)
Module_2
1. Explain Flynn’s Classifications, in details. .(2m)

Flynn's taxonomy is a classification system for computer architectures based on the number
of concurrent instruction streams and data streams they can process. This taxonomy includes
four categories:

1. Single Instruction, Single Data (SISD):

o Description: A single processor executes a single instruction stream to operate
on data stored in a single memory unit.
o Example: Traditional uniprocessor systems like early computers and most
personal computers.
o Use Case: Suitable for simple, sequential tasks.
2. Single Instruction, Multiple Data (SIMD):
o Description: A single instruction stream controls multiple processing
elements simultaneously to execute the same instruction on multiple data
points.
o Example: Vector processors, GPUs (Graphics Processing Units).
o Use Case: Ideal for tasks that require the same operation to be performed on
large data sets, such as image processing and scientific computations.
3. Multiple Instruction, Single Data (MISD):
o Description: Multiple processors execute different instruction streams on the
same data stream.
o Example: Rarely used in practice, but can be found in certain specialized
applications like fault-tolerant systems.
o Use Case: Suitable for applications requiring redundant operations on the
same data, enhancing fault tolerance.
4. Multiple Instruction, Multiple Data (MIMD):
o Description: Multiple processors execute different instruction streams on
different data streams.
o Example: Multiprocessor systems, multicore processors, distributed systems.
o Use Case: Common in general-purpose computing where different processes
or threads can execute independently, suitable for parallel processing of
independent tasks.

2. Explain the Six stage Pipelining in processor. (4m)

3. Explain Basic Instruction Cycle with Interrupt Processing. (8m)
4. Explain Pipelining concept in processor. .(2m)
5. Differentiate Soft wired and Hardwired Control unit. .(8m)
Microprogrammed Control
Hardwired Control Unit Unit

Microprogrammed control unit

Hardwired control unit generates the
generates the control signals with
control signals needed for the
the help of micro instructions stored
processor using logic circuits
in control memory
 Microprogrammed Control
Hardwired Control Unit Unit

Hardwired control unit is faster when

compared to microprogrammed This is slower than the other as
control unit as the required control micro instructions are used for
signals are generated with the help of generating signals here
hardwares

Difficult to modify as the control Easy to modify as the modification

signals that need to be generated are need to be done only at the
hard wired instruction level

Less costlier than hardwired control

More costlier as everything has to be
as only micro instructions are used
realized in terms of logic gates
for generating control signals

It cannot handle complex instructions

as the circuit design for it becomes It can handle complex instructions
complex

Only limited number of instructions

Control signals for many instructions
are used due to the hardware
can be generated
implementation

Used in computer that makes use of Used in computer that makes use of
Reduced Instruction Set Complex Instruction Set
Computers(RISC) Computers(CISC)

9. Explain Flynn’s Classification and describe the Six stage Pipelining in processor.(8m)
Q1,2
Module_3
1. Explain how an EXOR gate function with two input signals. .(2m)
2. Describe the IEEE single-precision floating-point representation or frame format. .(2m)
3. Convert (243.63)8 to decimal, binary and hexadecimal. (4m)
4. Draw flowchart for Booths algorithm. Multiply the (-7) and 4 using booths Algorithm.
(8m)
5. Convert (314)8 to binary and decimal. .(2m)
6. Draw and explain flowchart for Restoring division method. . (4m)
Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A
will contain value 0, register M will contain Divisor, register Q will contain Dividend, and N
is used to specify the number of bits in dividend.
Step 2: In this step, register A and register Q will be treated as a single unit, and the value of
both the registers will be shifted left.
Step 3: After that, the value of register M will be subtracted from register A. The result of
subtraction will be stored in register A.
Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then the
least significant bit of register Q will be set with a value 1. If the most significant bit of A is
1, then the least significant bit of register Q will be set to with value 0, and restore the value
of A that means it will restore the value of register A before subtraction with M.
Step 5: After that, the value of N will be decremented. Here n is used as a counter.
Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to
step 2.
7. Explain IEEE 754 Floating Point (Single Precision) Number Representation. .(2m)
Same as 2
7. Multiply (-2) and (-5) using Booth’s Algorithm and draw the flowchart for booths
algorithm. .(8m)

8. Explain the truth table for EX-OR, EX-NOR gate function with two input signals. .(2m).
10. Convert (314)8 to binary. .(2m).
12. Explain the booths algorithm flowchart and Multiply (4) and (-3) using Booth’s
Algorithm. .(8m)
Module_4
1. Explain Characteristics of memory. .(2m)

 Capacity: Capacity refers to the amount of data that a memory system can store. It is
usually measured in bytes, kilobytes (KB), megabytes (MB), gigabytes (GB), terabytes (TB),
or even petabytes (PB) for large-scale memory systems.

 Volatility: Volatility indicates whether the stored data is retained when the power supply is
turned off. There are two types of memory based on volatility:
  Volatile Memory: Data is lost when power is turned off. Examples include RAM
(Random Access Memory).
 Non-volatile Memory: Data is retained even when power is turned off. Examples
include ROM (Read-Only Memory) and flash memory.

 Speed: Memory speed refers to how quickly data can be accessed or transferred within the
memory system. Faster memory allows for quicker read and write operations, which is
crucial for improving overall system performance.

 Access Time: Access time is the time taken by the memory system to locate and retrieve
data. It includes the time required for addressing, decoding, and accessing the data. Lower
access times result in faster data retrieval.

 Cost: Cost refers to the monetary expense associated with acquiring and maintaining the
memory system. Different types of memory technologies have varying costs based on factors
such as capacity, speed, and volatility.


2. Explain Cache memory and its level(L1,L2,L3). (4m)
Cache memory is a type of high-speed memory that serves as a buffer between the CPU
and main memory (RAM) in a computer system. Its primary function is to store
frequently accessed data and instructions, thereby reducing the average time required to
access memory.

Levels of Cache Memory:

1. Level 1 Cache (L1 Cache):
o L1 cache is the smallest and fastest cache level, located directly on the CPU
chip.
o It stores frequently accessed data and instructions that the CPU is currently
processing.
o Due to its proximity to the CPU, L1 cache has the lowest access latency,
providing extremely fast data retrieval.
o L1 cache is split into separate instruction cache (I-cache) and data cache (D-
cache) to improve performance.
o Typically, modern processors have separate L1 caches for instructions and
data, each with its own dedicated cache lines.
2. Level 2 Cache (L2 Cache):
o L2 cache is larger than L1 cache and is located on the CPU chip or on a
separate chip close to the CPU.
 o It serves as a secondary cache layer, holding additional data and instructions
that cannot fit in the smaller L1 cache.
o Although slower than L1 cache, L2 cache still offers faster access times
compared to main memory (RAM).
o In some processor designs, each core may have its own dedicated L2 cache,
while in others, multiple cores may share a common L2 cache.
3. Level 3 Cache (L3 Cache):
o L3 cache is the largest and slowest of the three cache levels and is typically
shared among multiple CPU cores.
o It serves as a shared cache resource for the entire CPU or a group of CPU
cores, providing a larger pool of cache memory to accommodate more data
and instructions.
o L3 cache helps improve overall system performance by reducing memory
access latency and improving data sharing among CPU cores.
o Unlike L1 and L2 cache, which are often located on the CPU chip itself, L3
cache may be located on a separate chip or shared among multiple CPU
sockets in a multi-processor system.

4. List down memory mapping techniques and Explain Direct Memory mapping
technique in detail. (8m).
Memory mapping techniques are used in computer systems to manage the mapping of
logical addresses (generated by the CPU) to physical addresses (locations in the
memory). There are several memory mapping techniques, including:
1. Direct Mapping
2. Associative Mapping
3. Set-Associative Mapping
Direct Memory Mapping Technique:
Direct memory mapping is a simple and efficient memory mapping technique that
involves a one-to-one mapping between logical addresses and physical addresses. In
this technique, each logical address is mapped directly to a specific location in the
main memory (RAM) using a simple mapping function.
Explanation of Direct Memory Mapping:
1. Address Format:
o In direct memory mapping, the logical address space is divided into multiple
blocks or pages, and the physical memory is divided into corresponding blocks
or frames of the same size.
o Each logical address consists of two parts: a block number (or page number)
and an offset within the block.
o Similarly, each physical address consists of a frame number (corresponding to
the block number) and an offset within the frame.
2. Mapping Function:
o Direct memory mapping uses a simple mapping function to map the block
number from the logical address to the corresponding frame number in the
physical memory.
o The mapping function typically involves using the block number as an index
into a mapping table (often called a page table or page directory) to retrieve
the corresponding frame number.
 3. Page Table:
o A page table is a data structure used to store the mapping information for each
block or page of the logical address space.
o Each entry in the page table contains the frame number corresponding to the
block number, along with additional control bits (such as valid/invalid bits,
protection bits, etc.).
o The page table is maintained by the operating system and is used by the
memory management unit (MMU) to perform address translation during
memory access.
4. Address Translation:
o When a program accesses memory using a logical address, the MMU
translates the logical address to a physical address using the page table.
o The MMU extracts the block number from the logical address, looks up the
corresponding entry in the page table to retrieve the frame number, and
combines the frame number with the offset to form the physical address.
o If the mapping entry is found in the page table, the MMU performs the
translation and allows the memory access to proceed. Otherwise, it raises a
page fault exception, indicating a memory access violation.

4. Compare RAM and ROM. .(2m)

6. Explain Memory Hierarchy Design and its Characteristics in details. .(8m)
6. Explain the types of ROM. .(2m).

ROM, or Read-Only Memory, is a type of non-volatile memory that retains its data even
when the power is turned off. There are several types of ROM, each with its own
characteristics and uses. The main types of ROM include:

1. Mask ROM (MROM):

o Mask ROM is manufactured with predefined data or program stored
permanently during the chip fabrication process.
o The data or program is 'masked' onto the ROM chip using metal layers during
manufacturing, making it unchangeable or "read-only."
o Mask ROM is cost-effective for large production runs but lacks flexibility as
its contents cannot be modified after fabrication.
2. Programmable ROM (PROM):
o PROM allows users to program or write data onto the memory chip after
fabrication using special programming equipment.
o Programming is typically done by blowing fuses or using electrically erasable
programmable read-only memory (EEPROM) cells.
o Once programmed, the data becomes permanent and cannot be changed,
similar to mask ROM.
3. Erasable Programmable ROM (EPROM):
o EPROM allows users to erase and reprogram the memory chip multiple times
using UV light exposure to erase the data.
o EPROM chips have a small window on the top that allows exposure to UV
light, which clears the data stored in the memory cells.
o Once erased, new data can be programmed onto the EPROM chip using
special programming equipment.
 o EPROM provides flexibility for development and testing purposes but requires
UV light exposure for erasure, which can be cumbersome.
4. Electrically Erasable Programmable ROM (EEPROM):
o EEPROM, also known as E²PROM or Flash EEPROM, allows users to erase
and reprogram the memory chip electrically without the need for UV light
exposure.
o EEPROM cells can be individually erased and reprogrammed using electrical
signals, making it more convenient than EPROM.
o EEPROM is widely used in applications where frequent updates or
modifications to the stored data are required, such as firmware updates in
electronic devices.

8. Compare Primary memory and Secondary memory. (4m)

Module_5
1. Describe with the help of a neat diagram I/O Module Structure.(2m)

An I/O module facilitates communication between the CPU (Central Processing Unit) and
peripheral devices such as keyboards, mice, printers, and storage devices. It consists of
several components designed to manage data transfer and control signals between the CPU
and peripherals.

Structure of an I/O Module:

1. Interface Circuits:
o Interface circuits serve as the connection point between the CPU and the
peripheral devices.
 o These circuits translate the electrical signals and data formats used by the CPU
into formats compatible with the peripheral devices, and vice versa.
2. Control Unit:
o The control unit manages the overall operation of the I/O module.
o It generates control signals to coordinate data transfers between the CPU,
memory, and peripheral devices.
o The control unit also handles error detection and recovery mechanisms to
ensure data integrity during I/O operations.
3. Data Buffer:
o The data buffer temporarily stores data being transferred between the CPU and
peripheral devices.
o It helps regulate the flow of data and prevents data loss or corruption by
providing a temporary storage space.
4. Address Decoding Logic:
o Address decoding logic interprets the memory addresses generated by the
CPU to determine the target peripheral device for data transfer.
o It enables the CPU to communicate with specific I/O ports or memory-mapped
I/O addresses associated with each peripheral device.
5. Interrupt Controller:
o The interrupt controller manages interrupt signals generated by peripheral
devices to signal the CPU for attention.
o It prioritizes interrupts and coordinates their handling by the CPU, ensuring
timely responses to critical events from peripheral devices.
6. Status and Control Registers:
o Status registers provide information about the current status of I/O operations,
such as data transfer completion, device readiness, or error conditions.
o Control registers allow the CPU to configure and control the behavior of the
I/O module and connected peripheral devices.
2. Difference between Programmed and Interrupt Driven I/O data transfer(4m)

2. Explain DMA based data transfer technique for I/O devices with neat diagram. (8m)
 Direct Memory Access (DMA) is a data transfer technique that allows peripheral
devices to transfer data directly to or from the main memory (RAM) without
involving the CPU. DMA improves system performance by offloading data transfer
tasks from the CPU, enabling it to focus on other processing tasks. Here's a detailed
explanation along with a diagram illustrating the DMA-based data transfer technique
for I/O devices:
DMA-Based Data Transfer Technique:
1. Initialization:
o The DMA controller is initialized by the CPU, which involves configuring the
DMA controller's registers, including the base address register, count register,
mode register, and status register.
2. Data Transfer Request:
o When an I/O device requires data transfer, it sends a DMA request signal to
the DMA controller.
o The DMA request signal indicates the type of operation (read or write) and the
memory address range involved in the data transfer.
3. DMA Controller Activation:
o Upon receiving the DMA request signal, the DMA controller activates and
gains control of the system bus.
o The CPU is temporarily suspended from accessing the system bus while the
DMA controller performs the data transfer.
4. Address Generation:
o The DMA controller generates memory addresses for data transfer using the
base address register.
o It increments the memory address after each data transfer to access
consecutive memory locations.
5. Data Transfer:
 o The DMA controller transfers data directly between the peripheral device and
the main memory without CPU intervention.
o During data transfer, the CPU remains idle or can execute other tasks,
improving overall system efficiency.
6. Interrupt Generation:
o After completing the data transfer, the DMA controller may generate an
interrupt signal to notify the CPU of the transfer completion.
o The CPU can then handle the interrupt, process the transferred data, or initiate
additional operations as needed.

6. Describe with the help of a neat diagram I/O Module Structure. And list down data transfer
technique.
.(8m)
Data Transfer Techniques:
There are various data transfer techniques used in computer systems to exchange data
between the CPU, memory, and I/O devices. Some common data transfer techniques include:
1. Programmed I/O (PIO): In this technique, the CPU directly controls data transfer
between memory and I/O devices by issuing commands and monitoring the transfer
status.
2. Interrupt-Driven I/O: In this technique, the CPU initiates data transfer between
memory and I/O devices, but the transfer is managed by interrupt signals generated by
the devices. The CPU is notified when data transfer is complete via interrupts.
3. Direct Memory Access (DMA): DMA is a technique where peripheral devices
transfer data directly to or from memory without CPU intervention. A DMA
controller manages the data transfer, allowing the CPU to focus on other tasks.
4. Channel I/O: Channel I/O is a technique similar to DMA but involves the use of
specialized hardware channels to manage data transfer between memory and I/O
devices. Each channel operates independently of the CPU.

Module_6
1. State the Features of 8051 Microcontroller.(2m)

 Features of 8051 Microcontroller:

 8-Bit Architecture: The 8051 microcontroller is based on an 8-bit architecture,

meaning it processes data in 8-bit chunks.
 Harvard Architecture: It follows the Harvard architecture, which separates program
and data memory, allowing simultaneous access to both.
 On-Chip Memory: The 8051 includes on-chip memory elements such as RAM,
ROM, and special function registers (SFRs) for efficient data and program storage.
 Peripheral Integration: It integrates various peripherals such as timers/counters,
serial communication ports (UART), I/O ports, and interrupts, making it suitable for a
wide range of applications.
 Low Power Consumption: The 8051 is designed for low-power applications, making
it suitable for battery-powered devices and other energy-efficient systems.
 Versatility: It supports a variety of programming languages and development
environments, allowing developers to choose the most suitable tools for their projects.
  Flexible I/O Ports: The 8051 provides multiple I/O ports with programmable
input/output configurations, offering flexibility for interfacing with external devices.
 Interrupt Support: It includes interrupt capabilities for handling time-critical events
and asynchronous external signals.
 Serial Communication: The 8051 supports serial communication protocols such as
UART (Universal Asynchronous Receiver/Transmitter), allowing it to communicate
with other devices and peripherals.

2. Describe the Program status word (PSW frame) in 8051.(2m)

 The Program Status Word (PSW) is a special-purpose register in the 8051 microcontroller
that contains various status flags and control bits.
 The PSW frame consists of multiple bits, each serving a specific purpose:

 Carry (CY): Indicates whether a carry occurred during arithmetic operations.

 Auxiliary Carry (AC): Used for binary-coded decimal (BCD) arithmetic operations.
 Parity (P): Indicates the parity of the accumulator register (even or odd).
 Overflow (OV): Indicates overflow during signed arithmetic operations.
 Register Bank Select (RS0, RS1): Selects one of the four register banks in the 8051.
 User-Definable (UD): Two user-definable bits available for custom use.
 Accumulator Bank Select (F0, F1): Selects the register bank for the accumulator.

 The PSW is used by the CPU during arithmetic, logic, and branching instructions to
determine the status of various operations and to control program flow.
 Program execution and decision-making often rely on the status flags contained within the
PSW to handle different conditions and scenarios effectively.

3. Implement embedded C program to transfer of block of data from one memory

location to other memory location. (4m)
4. Difference between Microcontroller and Microprocessor.(8m)

Microcontroller Microprocessor
 A microcontroller is a
The microprocessor is designed to be
specialized form of a
general-purpose.
microprocessor

It is cost-effective. It is a silicon chip

It is self-sufficient. It is a dependent unit

The microcontroller is used to The Microprocessor is

perform a particular tasks. used to perform a certain task.

Its power consumption is low. Its power consumption is high.

It contains CPU, RAM, ROM, It requires a combination of timers,

Registers, Timer and controllers
input/output ports. memory chips.

Its size is smaller. Its size is larger.

It is a chip which is called It is a general purpose device which is

single chip computer. called a CPU.

Microcontroller have no It have advantages of versatility such that

advantage of designing RAM, designer can decide the aount of RAM,
ROM, I/O port. ROM, I/O port as needed.

Its microprocessors processing

power is lower than Its processing power is higher.
microprocessor.

It uses Harvard Architecture. It uses Von Neumann Architecture.

It’s system cost is low. It’s system cost is high.

Each instruction needs an Each instruction needs an external

internal operation. operation.

For Example- Television. For Example- Personal Computers.

 4. Implement embedded C program to perform addition of two 16 bit Number (8051
Microcontroller.(2m)

5. Describe the Addressing mode of 8051 Microcontroller.(2m).

The 8051 microcontroller supports several addressing modes, which allow the programmer
to specify the operand's location. Here are the main addressing modes:

1. Immediate Addressing Mode:

o In this mode, the operand is specified in the instruction itself. The immediate
value follows the opcode.
o Example: MOV A, #25H moves the immediate value 25H into the accumulator
A.
2. Direct Addressing Mode:
o This mode specifies the direct address of the operand in the internal data
memory.
o Example: MOV A, 30H moves the value from the internal RAM location 30H
into the accumulator A.
3. Indirect Addressing Mode:
 o The address of the operand is specified by a register. The registers R0 and R1
are typically used for this mode.
o Example: MOV A, @R0 moves the value from the memory location pointed to
by R0 into the accumulator A.
4. Register Addressing Mode:
o The operand is located in one of the registers (R0 to R7) of the selected
register bank.
o Example: MOV A, R2 moves the value from register R2 into the accumulator A.
5. Register Indirect Addressing Mode:
o The address of the operand is held in the data pointer (DPTR) or the program
counter (PC).
o Example: MOVX A, @DPTR moves the value from the external memory location
pointed to by DPTR into the accumulator A.
6. Indexed Addressing Mode:
o Used for accessing data stored in program memory. The address is calculated
by adding a base register to an offset.
o Example: MOVC A, @A+DPTR moves the value from the program memory
address formed by adding A and DPTR into the accumulator A.

7. Draw and explain Architecture of 8051 Microcontroller.(8m)

Explanation of 8051 Architecture

1. Central Processing Unit (CPU):
o Accumulator (A): The primary register used for arithmetic and logic
operations, data transfer, and I/O operations.
o B Register: Used mainly for multiplication and division operations.
o Program Status Word (PSW): Contains status flags (carry, auxiliary carry,
overflow, parity, etc.) to indicate the outcome of various operations.
o General Purpose Registers (R0-R7): Eight registers used for general data
storage, organized into four banks.
2. Memory:
o 4 KB Program Memory (ROM): Stores the code to be executed by the
microcontroller. This is usually non-volatile memory.
 o 128 Bytes of Internal RAM: Used for data storage, stack operations, and
register banks. The lower 128 bytes are accessible directly, while the upper
128 bytes are used for special function registers (SFRs).
3. Bus System:
o Address Bus: 16-bit wide, used to address memory locations.
o Data Bus: 8-bit wide, used to transfer data between the CPU and other
peripherals.
o Control Bus: Carries control signals to coordinate various activities within the
microcontroller.
4. Timers/Counters:
o Timer 0 and Timer 1: Two 16-bit timers used for timing operations, event
counting, and generating baud rates for serial communication.
5. Serial Port:
o UART (Universal Asynchronous Receiver/Transmitter): Provides serial
communication capabilities, allowing the microcontroller to communicate
with other devices over a serial link.
6. Interrupt Control:
o Interrupt System: Five interrupt sources with two priority levels. The
interrupts can be used to respond to external and internal events, such as timer
overflows or external signals.
o Interrupt Vector Table: Holds the addresses of the interrupt service routines
(ISRs).
7. I/O Ports:
o Port 0 (P0), Port 1 (P1), Port 2 (P2), Port 3 (P3): Four 8-bit parallel I/O
ports used for interfacing external devices. Each port can be configured as
input or output.
8. Oscillator and Clock Circuit:
o Oscillator: Provides the clock signal that drives the CPU and peripherals. The
frequency is typically 12 MHz, but can be configured based on the crystal
used.
o Clock Circuit: Divides the oscillator frequency to generate the necessary
timing signals for different operations within the microcontroller.
9. Bus Control:
o Bus Control Unit: Manages the data flow on the internal and external buses,
ensuring proper synchronization and timing of data transfers.

12. Explain the pin diagram of 8051 microcontroller. State the Features of 8051
Microcontroller.(8m)
Pins 1-8: These pins belongs to Port 1 of microcontroller. Port 1 is used as domestically
pulled up, quasi bi directional input/output port.
Pin 9: It is a RESET pin which is utilized to set the microcontroller 8051 to its primary value.
During the beginning of an application the RESET pin is to be set elevated for two machine
rotations.
Pins 10-17: These pins belong to Port 3 of microcontroller. Port 3 can be used for number of
functions such as timer input, interrupts, serial communication indicator for transmitting
(TxD) and receiving (RxD). It is also known as domestic pull up port with quasi bi direction
port embedded within.
Pins 18 and 19: These pins are generally be used for interfacing outer crystal oscillator with
given system clock.
Pin 20: This pin titled as Vss. It symbolizes ground voltage or 0 V is connected to this pin of
microcontroller.
Pin 21-28: These pins belong to port 2 of microcontroller. Port 2 can be used as Input/output
port, senior order address bus are multiplexed with this quasi bi directional port.
Pin 29: This pin belongs to Program Store Enable or PSEN. It is used for interpreting the sign
from outer program memory.
Pin 30: This pin belongs to External Access or EA input is used for permit or prohibits outer
memory interfacing. If there is no outer memory need, this pin is set to high by linking it with
supply voltage .
Pin 31: This pin belongs to Address Latch Enable or ALE is used for de-multiplexing the
address data indication of port 0 for outer memory interfacing.
Pin 32-39: These pins belong to Port 0 of the microcontroller. Port 0 can be used as
input/output port, lower order address and data bus signals are multiplexed with this port.
This pin act as bi directional Input/output port and outer connected pull up resistors are
necessary for utilizing these ports as Input/output.
Pin 40: This pin is used to provide power supply to the circuit.