UNIT V

Memory and Programmable Logic

RAM – Memory Decoding – Error Detection and Correction – ROM – Programmable Logic
Array – Programmable Array Logic – Sequential Programmable Devices.

INTRODUCTION

Memory Unit
• A memory unit is a device to which binary information is transferred for storage and
from which information is retrieved when needed for processing.
• When data processing takes place, information from memory is transferred to selected
registers in the processing unit.
• Intermediate and final results obtained in the processing unit are transferred back to
be stored in memory.
• Binary information received from an input device is stored in memory, and
information transferred to an output device is taken from memory.
• A memory unit is a collection of cells capable of storing a large quantity of binary
information.

Types of memories
There are two types of memories that are used in digital systems:
• Random‐Access Memory (RAM)
• Read‐Only Memory (ROM)
RAM
• RAM stores new information for later use.
• The process of storing new information into memory is referred to as a memory write
operation.
• The process of transferring the stored information out of memory is referred to as a
memory read operation.
• RAM can perform both write and read operations.
ROM
• ROM can perform only the read operation.
• This means that suitable binary information is already stored inside memory and can
be retrieved or read at any time.
• However, that information cannot be altered by writing.
PLD(Programmable Logic Device)
• A PLD is an integrated circuit with internal logic gates connected through electronic
paths that behave similarly to fuses.
• The binary information that is stored within such a device is specified in some fashion
and then embedded within the hardware in a process is referred to as programming
the device.
• The word “programming” here refers to a hardware procedure which specifies the bits
that are inserted into the hardware configuration of the device.
• In the original state of the device, all the fuses are intact.
• Programming the device involves blowing those fuses along the paths that must be
removed in order to obtain the particular configuration of the desired logic function.
• A typical PLD may have hundreds to millions of gates interconnected through
hundreds to thousands of internal paths.
Examples of PLD
• ROM -OR
 • Programmable Logic Array (PLA) AND - OR
• Programmable Array Logic (PAL) AND
• Field‐Programmable Gate Array (FPGA)
Conventional and array logic diagrams for OR gate

I.RANDOM-ACCESS MEMORY
• A memory unit is a collection of storage cells, together with associated circuits needed
to transfer information into and out of a device.
• The architecture of memory is such that information can be selectively retrieved from
any of its internal locations.
• The time it takes to transfer information to or from any desired random location is
always the same—hence the name random‐access memory, abbreviated RAM.
• In contrast, the time required to retrieve information that is stored on magnetic tape
depends on the location of the data.
• A memory unit stores binary information in groups of bits called words .
• Data is transferred into and out of memory in terms of words.
• A memory word is a group of 1’s and 0’s and may represent a number, an instruction,
one or more alphanumeric characters, or any other binary‐coded information.
• A group of 8 bits is called a byte .
• 16‐bit word contains two bytes,
• 32‐bit word is made up of four bytes.
• The capacity of a memory unit is usually stated as the total number of bytes that the
unit can store.
• Communication between memory and its environment is achieved through data input
and output lines, address selection lines, and control lines that specify the direction of
transfer.

Fig: Block diagram of a memory unit using 2kxn decoder

 The n data input lines provide the information to be stored in memory, and the n data
output lines supply the information coming out of memory.
• The k address lines specify the particular word chosen among the many
available.
• The two control inputs specify the direction of transfer desired:
1. The Write input causes binary data to be transferred into the memory,
and
2. The Read input causes binary data to be transferred out of memory.
 The memory unit is specified by the number of words it contains and the number of
bits in each word.
 The address lines select one particular word.
  Each word in memory is assigned an identification number, called an address, starting
from 0 up to 2k – 1 , where k is the number of address lines.
 An internal decoder accepts this address and opens the paths needed to select the word
specified.
 the number of words (or bytes) in memory with one of the letters K (kilo), M (mega),
and G (giga).
o K is equal to 210 = 1024 bytes
o M is equal to 220
o G is equal to 230
o Thus, 64K = 216, 64x 210 =26 x 210 = 216
o 2M = 221 , and 4G = 232
Consider, for example, a memory unit with a capacity of 1K words of 16 bits each. Find
the number of bytes accommodated by the memory.
1Kx16
1024 bytes x2 bytes
2048 bytes or 2x 1024 bytes = 2K bytes

Write Operations
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data input lines.
3. Activate the write input.
The memory unit will then take the bits from the input data lines and store them in the
word specified by the address lines.
Read Operations
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the
address and apply them to the output data lines.

Commercial memory components available in integrated‐circuit chips

sometimes provide the two control inputs for reading and writing
1. Memory Enable
2. Read/Write

Types of Memories
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
Static RAM (SRAM)
• Static RAM (SRAM) consists essentially of internal latches that store the binary
information.
• The stored information remains valid as long as power is applied to the unit.
Dynamic RAM (DRAM)
• Dynamic RAM (DRAM) stores the binary information in the form of electric charges
on capacitors provided inside the chip by MOS transistors.
 • The stored charge on the capacitors tends to discharge with time, and the capacitors
must be periodically recharged by refreshing the dynamic memory.
• Refreshing is done by cycling through the words every few milliseconds to restore
the decaying charge.

SRAM Vs DRAM
• DRAM offers reduced power consumption and larger storage capacity in a single
memory chip.
• SRAM is easier to use and has shorter read and write cycles.
Volatile Vs Non-volatile memory
• Memory units that lose stored information when power is turned off are said to be
volatile .
• RAM-volatile
• A nonvolatile memory, such as magnetic disk, retains its stored information after the
removal of power.
• ROM – non-volatile
Masked ROM
Programmable ROM
Erasable PROM
Electrically EPROM

II. MEMORY DECODING

Decoding circuits are used to select the memory word specified by the input address
Internal Construction of RAM
• The internal construction of a RAM of m words and n bits per word consists of m * n
binary storage cells and associated decoding circuits for selecting individual words.
• The binary storage cell is the basic building block of a memory unit.
• m = 2 power k

Fig:Logic diagram of memory cell

Storage part of a cell is modeled by a SR latch with associated gates to form a D latch.

Fig:Block Diagram of memory cell

 • A cell is an electronic circuit with four to six transistors.
• A binary storage cell must be very small in order to be able to pack as many cells as
possible in the small area available in the integrated circuit chip.
• The binary cell stores one bit in its internal latch.
• The select input enables the cell for reading or writing, and the read/write input
determines the operation of the cell when it is selected.
• A 1 in the read/write input provides the read operation by forming a path from the
latch to the output terminal.
• A 0 in the read/write input provides the write operation by forming a path from the
input terminal to the latch.
Diagram of a 4 * 4 RAM
2kxn RAM
m= 2k
mxn RAM= m words
Each word contains n bits
requires mxn cells
4x4 RAM= 4 words
Each word contains 4 bits
requires 4x4 cells
Memory with 2k words of n bits per word requires: k address lines that go into a k * 2k
decoder.
Each one of the decoder outputs selects one word of n bits for reading or writing.
4x4 RAM
K=2 address lines-2 Decoder- 2x4

2kxn RAM
Memory with 2k words of n bits per word requires: k address lines that go into a k * 2k
decoder.
4x4 RAM 22x4 RAM
2 address lines that go into a 2* 22 decoder.

Fig: Diagram of a 4 * 4 RAM

Coincident Decoding
• A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate.
• The total number of gates and the number of inputs per gate can be reduced by
employing two decoders in a two‐dimensional selection scheme.
• In this configuration, two k /2‐input decoders are used instead of one k ‐input decoder.
• One decoder performs the row selection and the other the column selection in a two‐
dimensional matrix configuration.
• Decoding Structure for 1K word memory:
1K=1024 bytes=210
Need a kx2K decoder
10x 1024 decoder
Instead of a k input decoder use two k/2 input decoder
K=10,k/2=5
5- input decoder
5x25 decoder
So, we need two 5x25 decoder

Fig: Two‐dimensional decoding structure for a 1K‐word memory

Address Multiplexing
• To build memories with higher density, it is necessary to reduce the number of
transistors in a cell.
• To reduce the number of pins in the IC package, designers utilize address
multiplexing whereby one set of address input pins accommodates the address
components.
• In a two‐dimensional array, the address is applied in two parts at different times, with
the row address first and the column address second.
• Since the same set of pins is used for both parts of the address, the size of the
package is decreased significantly.
 Fig: Address multiplexing for a 64K DRAM
• The memory consists of a two‐dimensional array of cells arranged into 256 rows by
256 columns, for a total of 64K words.
• There is a single data input line, a single data output line, and a read/write control, as
well as an eight‐bit address input and two address strobes, the latter included for
enabling the row and column address into their respective registers.
• The row address strobe (RAS) enables the eight‐bit row register, and the column
address strobe (CAS) enables the eight‐bit column register.
• The bar on top of the name of the strobe symbol indicates that the registers are
enabled on the zero level of the signal.
16‐bit address is applied to the DRAM in two steps using RAS and CAS
• Initially, both strobes are in the 1 state.
• The 8‐bit row address is applied to the address inputs and RAS is changed to 0.
• This loads the row address into the row address register.
• RAS also enables the row decoder so that it can decode the row address and select one
row of the array.
• After a time equivalent to the settling time of the row selection, RAS goes back to the
1 level.
• The 8‐bit column address is then applied to the address inputs, and CAS is driven to
the 0 state.
• This transfers the column address into the column register and enables the column
decoder.
• Now the two parts of the address are in their respective registers, the decoders have
decoded them to select the one cell corresponding to the row and column address, and
a read or write operation can be performed on that cell.
• CAS must go back to the 1 level before initiating another memory operation.

III.ERROR DETECTION AND CORRECTION

• The dynamic physical interaction of the electrical signals affecting the data path of a
memory unit may cause occasional errors in storing and retrieving the binary
information.
• The reliability of a memory unit may be improved by employing error‐detecting and
error‐correcting codes.
 common error detection scheme
• The most common error detection scheme is the parity bit.
• A parity bit is generated and stored along with the data word in memory.
• The parity of the word is checked after reading it from memory.
• The data word is accepted if the parity of the bits read out is correct.
• If the parity checked results in an inversion, an error is detected, but it cannot be
corrected.
error‐correcting code
• An error‐correcting code generates multiple parity check bits that are stored with the
data word in memory.
• Each check bit is a parity over a group of bits in the data word.
• When the word is read back from memory, the associated parity bits are also read
from memory and compared with a new set of check bits generated from the data that
have been read.
• If the check bits are correct, no error has occurred.
• If the check bits do not match the stored parity, they generate a unique pattern, called
a syndrome, that can be used to identify the bit that is in error.
• A single error occurs when a bit changes in value from 1 to 0 or from 0 to 1 during the
write or read operation.
• If the specific bit in error is identified, then the error can be corrected by
complementing the erroneous bit.
Hamming Code
• One of the most common error‐correcting codes used in RAMs was devised by R. W.
Hamming.
• In the Hamming code, k parity bits are added to an n ‐bit data word, forming a new
word of n + k bits.
• The bit positions are numbered in sequence from 1 to n + k.
• Those positions numbered as a power of 2 are reserved for the parity bits.
• The remaining bits are the data bits.
• The code can be used with words of any length.
EXAMPLE
• 8‐bit data word 11000100 (n=8)
• Let k=4(parity bits)
• n+k=8+4=12 bits
• Positions numbered in powers of 2 are left for parity bits. 20,21,22,23,24…. i.e.
1,2,4,8,16…
• In the remaining positions store data bits
1 2 3 4 5 6 7 8 9 10 11 12
P P2 1 P 1 0 0 P 0 1 0 0

0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
 0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12

LSB=1,3,5,7,9,11
Next BIT=2,3,6,7,10,11
Next Bit=4,5,6,7,12
MSB=8,9,10,11,12
P1=XOR(3,5,7,9,11)=XOR(1,1,0,0,0)=0
P2=XOR(3,6,7,10,11)=XOR(1,0,0,1,0)=0
P4=1
P8=1
1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0
• LSB=1,3,5,7,9,11
• Next BIT=2,3,6,7,10,11
• Next Bit=4,5,6,7,12
• MSB=8,9,10,11,12
• After reading 12 bits they are checked for errors
• Check bits:
• C1=XOR(1,3,5,7,9,11)=XOR(0,1,1,0,0,0)=0
• C2=XOR(2,3,6,7,10,11)=0
• C4=XOR(4,5,6,7,12)=0
• C8=XOR(8,9,10,11,12)=0
• c1C2C4C8=0000 no error
• C=C1C2C4C8not equal to 0 ,an error
• If check bit=0 ,designates even parity
• If check bit=1 ,designates odd parity
• If c≠0, The 4-bit binary number gives position of erroneous bit, correct the error by
complementing the corresponding bit.
• C=C1C2C4C8 = 0101=5 error in position 5
Single‐Error Correction, Double‐Error Detection
• The Hamming code can detect and correct only a single error.
• By adding another parity bit to the coded word, the Hamming code can be used to
correct a single error and detect double errors.
• 8‐bit data word 11000100 (n=8)
• Let k=5
• n+k=8+5=13 bits
1 2 3 4 5 6 7 8 9 10 11 12 13

P1 P2 1 P4 1 0 0 P8 0 1 0 0 P13

• Set Even parity

 • P1=XOR(3,5,7,9,11)=XOR(1,1,0,0,0)=0
• P2=XOR(3,6,7,10,11)=XOR(1,0,0,1,0)=0
• P4=XOR(5,6,7,12)=1
• P8=XOR(9,10,11,12)=1
• P13=XOR(1,2,3,4,5,6,7,8,9,10,11,12)=1
• When the 13‐bit word is read from memory, the check bits are evaluated, as is the
parity P over the entire 13 bits.
• If P = 0, the parity is correct (even parity), but if P = 1, then the parity over the 13
bits is incorrect (odd parity). The following four cases can arise:
• If C = 0 and P = 0, no error occurred.
• If C= 0 and P = 1, a single error occurred that can be corrected.
• If C= 1and P =1, a double error occurred that is detected, but that cannot be corrected.
• If C = 0 and P = 1, an error occurred in the P13 bit.
• This scheme may detect more than two errors, but is not guaranteed to detect all such
errors.
• C1=XOR(1,3,5,7,9,11)=XOR(0,1,1,0,0,0)=0
• C2=XOR(2,3,6,7,10,11)=0
• C4=XOR(4,5,6,7,12)=0
• C8=XOR(8,9,10,11,12)=0
• P=XOR(1,2,3,4,5,6,7,8,9,10,11,12,13)
• C=C1C2C4C8
• P

IV. READ‐ONLY MEMORY

• A read‐only memory (ROM) is essentially a memory device in which permanent
binary information is stored.
• The binary information must be specified by the designer and is then embedded in the
unit to form the required interconnection pattern.
• Once the pattern is established, it stays within the unit even when power is turned off
and on again.

• The inputs provide the address for memory, and the outputs give the data bits of the
stored word that is selected by the address.
• The number of words in a ROM is determined from the fact that k address input lines
are needed to specify 2k words.
• In general, a 2k * n ROM will have an internal k * 2k decoder and n OR gates.
• 32x8 ROM
• 25x8 ROM k=5,n=8
• 5x32 Decoder
• 8 OR gates
 • The 256 intersections are programmable.
• A programmable connection between two lines is logically equivalent to a switch that
can be altered to be either closed (meaning that the two lines are connected) or open
(meaning that the two lines are disconnected).
• The programmable intersection between two lines is sometimes called a crosspoint .
• The internal binary storage of a ROM is specified by a truth table .
• The hardware procedure that programs the ROM blows fuse links in
accordance with a given truth table.
• Every 0 listed in the truth table specifies the absence of a connection, and
every 1 listed specifies a path that is obtained by a connection.
Combinational Circuit Implementation
• A ROM has a decoder generates the 2k minterms of the k input variables.
• By inserting OR gates to sum the minterms of Boolean functions, we were able to
generate any desired combinational circuit.
EXAMPLE-1
Design a combinational circuit using a ROM. The circuit accepts a three‐bit number and
outputs a binary number equal to the square of the input number.
Truth Table B1=0,B0=A0 input variables=3,output variables=4
K=3,n=4
2kxn ROM = 2 power 3x4 ROM
A2 A1 A0 B5 B4 B3 B2 B1 B0 decimal

0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1 1

0 1 0 0 0 0 1 0 0 4
 0 1 1 0 0 1 0 0 1 9

1 0 0 0 1 0 0 0 0 16

1 0 1 0 1 1 0 0 1 25

1 1 0 1 0 0 1 0 0 36

1 1 1 1 1 0 0 0 1 49

• 2kxn ROM = kx2k Decoder and n OR gates

• 3x8 Decoder ,4 OR gates

Example 2: Implement Using a ROM

• 2kxn ROM
 • k- number of input variables=3
• n-number of output variables=4
• 8x4 ROM
• 3x8 Decoder 4 OR gates
BLOCK DIAGRAM

x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 0 1
0 1 0 0 0 0 1
0 1 1 1 0 1 0
1 0 0 0 0 0 1
1 0 1 1 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1

Types of ROM
• The required paths in a ROM may be programmed in four different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse /fuse intact
3. Erasable PROM or EPROM: placed under a special ultraviolet light for a given
period of time will erase the pattern in ROM.
4. Electrically-erasable PROM(EEPROM): erased with an electrical signal instead of
ultraviolet light.
Combinational PLDs
• A combinational PLD is an integrated circuit with programmable gates divided into an
AND array and an OR array to provide an AND-OR sum of product implementation.
• PROM: fixed AND array constructed as a decoder and programmable OR array.
• PAL: programmable AND array and fixed OR array.
• PLA: both the AND and OR arrays can be programmed.

V. PLA-PROGRAMMABLE LOGIC ARRAY

• Consists of set of programmable AND gates that generates the product terms.
• Product terms are connected to programmable OR gates to provide SOP
implementation.

PLA program table:

• The fuse map of a PLA can be specified in a tabular form.
• The PLA programming table consists of three sections.
• The first section lists the product terms
• The second section specifies the required paths between inputs and AND
gates.
• The third section specifies the paths between the AND and OR gates.
• For each output variable, we may have a T (for true) or C (for complement) for
programming the XOR gate.
• For each product term, the inputs are marked with 1, 0, or — (dash).
• Normal input- 1
• Complemented- 0
• Absent- -
• If a variable in the product term appears in the form in which it is true, the
corresponding input variable is marked with a 1. If it appears complemented, the
corresponding input variable is marked with a 0. If the variable is absent from the
product term, it is marked with a dash.
3x4x2 PLA
 •A PLA is specified by
• Number of inputs-n
• Number of product terms-k – k AND gates
• Number of outputs-m- m OR gates - m XOR gates
• nxkxm PLA
2x3x4 PLA
• 2 –inputs
• 3-AND gates
• 4 OR gates XOR gates- no of outputs
EXAMPLE 1:Implement the following two Boolean functions with a PLA:
F1(A, B, C) = Σ(0, 1, 2, 4)
F2(A, B, C) = Σ(0, 5, 6, 7)

PLA Program Table

Product Inputs Outputs
Term A B C F1(C) F2(T)
1-BC - 1 1 1 -
2-AC 1 - 1 1 1
3-AB 1 1 - 1 1
4- a'b'c 0 0 1 - 1
EXAMPLE2:

Product Inputs Outputs

Term
A B C F1 F2
VI. PROGRAMMABLE ARRAY LOGIC
• The PAL is a programmable logic device with a fixed OR array and a programmable
AND array.
• Because only the AND gates are programmable, the PAL is easier to program than,
but is not as flexible as, the PLA.
A=xy
B=xy+x’z
B=A+x’z
Product Term Inputs Outputs
x y z
1- x’z 0 - 1 A=x'z+y'z+xyz‘ (3)
2-y’z - 0 1
3-xyz’ 1 1 0
4 - - -
5-x’y’ 0 0 - B=x'y'+xy(2)
6 -xy 1 1 -
7 - - -
8 - - -
9xy’z 1 0 1 C=xy'z+x'yz(2)
10-x’yz 0 1 1
11 - - -
12 - - -
13 xy’ 1 0 - D=xy'+xz+y'z+x'yz‘(4)
14xz 1 - 1
15y’z - 0 1
16x’yz’ 0 1 0

VII.SEQUENTIAL PROGRAMMABLE DEVICES

• Digital systems are designed with flip‐flops and gates.
 • Since the combinational PLD consists of only gates, it is necessary to include
external flip‐flops when they are used in the design.
• Sequential programmable devices include both gates and flip‐flops.
Three major types
1. Sequential (or simple) programmable logic device (SPLD)
2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)
1. Sequential (or simple) programmable logic device (SPLD)
• The sequential PLD is sometimes referred to as a simple PLD.
• The SPLD includes flip‐flops, in addition to the AND–OR array, within the integrated
circuit chip.
• A PAL or PLA is modified by including a number of flip‐flops connected to form a
register.
• The circuit outputs can be taken from the OR gates or from the outputs of the flip‐
• flops.

Field‐programmable logic sequencer (FPLS)

• The first programmable device developed to support sequential circuit
implementation is the field‐programmable logic sequencer (FPLS).
• A typical FPLS is organized around a PLA with several outputs driving flip‐flops.
• The flip‐flops are flexible in that they can be programmed to operate as either the JK
or the D type.
• The FPLS did not succeed commercially, because it has too many programmable
connections.
Registered PAL
• The configuration mostly used in an SPLD is the combinational PAL together with D
flip‐flops.
• A PAL that includes flip‐flops is referred to as a registered PAL, to signify that the
device contains flip‐flops in addition to the AND–OR array.
• Each section of an SPLD is called a macro cell, which is a circuit that contains a sum‐
of‐products combinational logic function and an optional flip‐flop.

Fig: Basic macro cell logic

2. Complex programmable logic device (CPLD)
• CPLD is a collection of individual PLDs on a single integrated circuit.
• A programmable interconnection structure allows the PLDs to be connected to each
other in the same way that can be done with individual PLDs.

Fig: General CPLD configuration

• The device consists of multiple PLDs interconnected through a programmable switch
matrix.
• The input–output (I/O) blocks provide the connections to the IC pins.
• Each I/O pin is driven by a three state buffer and can be programmed to act as input or
output.
• The switch matrix receives inputs from the I/O block and directs them to the
individual macro cells.
• Similarly, selected outputs from macro cells are sent to the outputs as needed.
• Each PLD typically contains from 8 to 16 macro cells, usually fully connected.

3. Field‐programmable gate array (FPGA)

The basic component used in VLSI design is the gate array, which consists of a pattern of
gates, fabricated in an area of silicon that is repeated thousands of times until the entire chip
is covered with gates.
Arrays of one thousand to several hundred thousand gates are fabricated within a single IC
chip, depending on the technology used.
The design with gate arrays requires that the customer provide the manufacturer the desired
interconnection pattern.
• A field‐programmable gate array (FPGA) is a VLSI circuit that can be
programmed at the user’s location.
• A typical FPGA consists of an array of millions of logic blocks, surrounded by
programmable input and output blocks and connected together via programmable
interconnections.
• A typical FPGA logic block consists of lookup tables, multiplexers, gates, and
flip‐flops.