MULTI-BIT A/D CONVERTERS

WITH HIGH RESOLUTION AND

LOW-POWER
A Ph.D. Thesis

Student: Yao Liu

University of Pavia

Tutor: Franco Maloberti

University of Pavia

UNIVERSITY OF PAVIA, 2013

To Jiannan, Sen and my parents
CONTENTS

List of Figures ix
List of Tables xv
Acknowledgments xvii
Acronyms xix

1 Introduction 1
1.1 Motivation and Objectives 2
1.2 Structure of the Thesis 3
References 4

2 A/D Converters for High Resolution 5

2.1 Background on A/D Converters 5
2.1.1 A Brief History 5
2.1.2 Applications and Categories 6
2.1.3 Specifications 8
2.1.4 State of the Art of ADCs 10
2.2 Σ∆ A/D Converters 10
2.2.1 First-Order Σ∆ A/D Converter 11
2.2.2 High-Order Σ∆ A/D Converter 13
2.2.3 State of the Art of Σ∆Ms 14
v
vi CONTENTS

2.3 Incremental A/D Converters 16

2.3.1 First-Order Incremental Converters 17
2.3.2 High-Order Incremental Modulators 18
2.3.3 Multi-Bit Incremental Converters 20
2.3.4 State of the Art of Incremental Converters 22
References 24

3 Dynamic Conversion of Mismatch 27

3.1 Effect of Mismatch and DEM Methods 27
3.1.1 kT/C Noise Limitation 28
3.1.2 Mismatch Effect for Σ∆ ADCs 28
3.1.3 Mismatch Effect for Incremental Modulators 30
3.1.4 Dynamic-Element-Matching Techniques 31
3.2 Smart-DEM Algorithm 32
3.2.1 Multi-Bit DAC and Mismatch 32
3.2.2 The Weight of Error for Multi-Bit DAC 34
3.2.3 The Principle of Smart-DEM Algorithm 35
3.3 Design Examples and Simulation Results 36
3.3.1 Design Consideration of Employing Smart-DEM Algorithm 36
3.3.2 Second-Order Incremental Modulator Example 36
3.3.3 Third-Order Incremental Modulator Example 38
References 42

4 A 17-bit Incremental A/D Converter: Design Considerations 43

4.1 General Considerations for Incremental Schemes 43
4.1.1 Second-Order or Higher-Order 44
4.1.2 Comparator or Multi-Bit Quantization 46
4.1.3 Design Strategies for Target Specifications 48
4.2 Non Conventional Incremental Structures 49
4.2.1 Second-Order Architectures 49
4.2.2 Third-Order Architectures 51
4.2.3 Digital Assisted Actions 53
4.3 Algorithmic A/D Conversion 54
4.3.1 Limitations of Algorithmic Architectures 56
4.3.2 Error Correction Methods 60
References 61

5 A 17-bit Incremental A/D Converter: Design and Implementation 63

5.1 Proposed Architecture 63
5.2 Analog Building Blocks 65
 CONTENTS vii

5.2.1 Operational Amplifiers 66

5.2.2 Single Step Chopping Technique 67
5.2.3 Bipolar DAC and Controls 68
5.2.4 Low-Power Comparator 69
5.3 Digital Building Blocks 70
5.3.1 Smart-DEM Block 71
5.3.2 Multi-Phase Clock generator 74
5.4 Experimental Results 75
5.4.1 Test Setup 75
5.4.2 Measurement Results 78
5.4.3 Performance Comparison 80
References 82

6 A 12-bit Single Op-Amp 0+2 Σ∆ A/D Converter 83

6.1 General Considerations 83
6.2 Proposed Scheme 89
6.3 Building Blocks 94
6.3.1 Gain-Boost Operational Amplifier 94
6.3.2 Low-Power Comparator 95
6.3.3 Non-Overlap Clock with Three Phases 95
6.4 Simulation Results and Performance Comparison 98
References 99

7 Conclusions and Future Work 101

7.1 Summary 101
7.2 Contributions 102
7.2.1 High-Order Smart-DEM Algorithm 102
7.2.2 Non-conventional Incremental Architectures 102
7.2.3 Single Op-Amp Second-Order Σ∆ Architecture 102
7.3 Future Directions 102
7.3.1 Multi-Bit Incremental ADC aiming for 20-Bit 102
7.3.2 Multi-Bit CT Incremental Modulator 103
7.3.3 ADCs Utilizing Nanometer CMOS Technologies 103
References 104
A kT/C Noise of Incremental ADCs 105
A.1 kT/C Limitation of Second-Order Incremental ADCs 105
A.2 kT/C Limitation of Third-Order Incremental ADCs 106
A.3 kT/C Limitation of Lth-Order Incremental ADCs 107
B List of Publications 109
LIST OF FIGURES

2.1 ADC architectures for typical resolution and bandwidth requirements. 7

2.2 Offset and gain error of ADCs. 8
2.3 DNL and INL of analog-to-digital converters. 9
2.4 Power efficiency of ADCs with respect to SNDR. 10
2.5 Conversion bandwidth of ADCs versus SNDR. 11
2.6 First-order Σ∆ ADC block diagram. 11
2.7 PSD (8096-point FFT) of Dout of the first-order Σ∆ ADC with -3 dBF S sinusoid
waveform input at normalized frequency 0.0016. The OSR is 16. 12
2.8 Second-order Σ∆ ADC block diagram. 13
2.9 PSD (8096-point FFT) of Dout of the second-order Σ∆ ADC with -3 dBF S
sinusoid waveform input at normalized frequency 0.0016. The OSR is 16. 13
2.10 Schematic of a double sampling integrator implemented with SC circuits. 15
2.11 Nth-order Σ∆M with multiple feedback paths block diagram. 15
2.12 Nth-order Σ∆M without intermediate feedback paths block diagram. 15
2.13 First-order incremental ADC block diagram. 17
2.14 Second-order feed-forward incremental modulator block diagram. 18
ix
x LIST OF FIGURES

2.15 Lth-order incremental ADC architecture. 19

2.16 The equivalent model of Lth-order incremental ADC. 20
2.17 Second-order feed-forward multi-bit incremental ADC block diagram. 21
3.1 Second-order 5-bit feed-forward Σ∆ ADC block diagram. 29
3.2 PSD (8096-point FFT) with σ=1.0% mismatch for 32 unity elements of DAC. The
input signal is a sinusoid waveform at normalized frequency 8.54 · 10−4 whose
amplitude is -3 dBF S . The OSR is 16. 29
3.3 PSD (8096-point FFT) with σ=0.1% mismatch for 32 unity elements of DAC. The
input signal is a sinusoid waveform at normalized frequency 8.54 · 10−4 whose
amplitude is -3 dBF S . The OSR is 16. 30
3.4 Equivalent model of second-order incremental ADC with non-ideal multi-bit DAC. 30
3.5 Conventional implementation of the first integrator and 3-bit DAC (11 levels). 33
3.6 First integrator and 11-level bipolar DAC implementation. 34
3.7 The status of the weights in Smart-DEM with Vin = 0.305Vref . 35
3.8 Second-order 3-bit feed-forward incremental architecture with Smart-DEM block. 37
3.9 Resolution comparison for second-order incremental converter without DEM (top),
with DWA (middle) and with Smart-DEM (bottom). The mismatch of unity
elements obeys normal distribution with µ = 0 and σ = 0.08%. 38
3.10 Resolution comparison for second-order incremental converter without DEM (top),
with DWA (middle) and with Smart-DEM (bottom). The mismatch of unity
elements obeys normal distribution with µ = 0 and σ = 0.8%. 39
3.11 Accumulated weights of mismatch of 10 unity elements for second-order 3-bit
feed-forward architecture with constant Vin = 0.123Vref . 39
3.12 Third-order 3-bit feed-forward incremental architecture with Smart-DEM block. 40
3.13 Resolution comparison for third-order incremental converter without DEM (top),
with DWA (middle) and with Smart-DEM (bottom). The mismatch of unity
elements obeys normal distribution with µ = 0 and σ = 0.035%. 40
3.14 Resolution comparison for third-order incremental converter without DEM (top),
with DWA (middle) and with Smart-DEM (bottom). The mismatch of unity
elements obeys normal distribution with µ = 0 and σ = 0.35%. 41
4.1 Resolution versus clock periods for different order incremental structures. 44
4.2 The coefficient α1 with respect to clock periods. 45
4.3 INL versus the gain of the first op-amp. 46
4.4 Output swing of the first op-amp utilizing 2-level or 3-bit quantization with
Vin = 0.707 V. 47
 LIST OF FIGURES xi

4.5 Second-order incremental scheme with two feedback paths. 49

4.6 Second-order incremental scheme with one feedback path. 50

4.7 Second-order incremental scheme with two quantizers. 50

4.8 Output swing of op-amps for second-order scheme with two quantizers with
0.707Vref input. 51

4.9 Third-order incremental ADC with one feedback path. 52

4.10 Third-order incremental ADC with three quantizers. 52

4.11 Third-order incremental ADC with three quantizers and input level shift. 53

4.12 Conceptual block diagram of algorithmic converter. The quantizer can be a simple
comparator or a multi-bit scheme. 54

4.13 Possible circuit implementation of a fully-differential algorithmic converter. The

DAC establishes a C3 load from virtual grounds to ground. 55

4.14 Equivalent number of bit versus the finite gain of the op-amp used in an algorithmic
converter. 57

4.15 Spectrum of an algorithmic converter with a 3-level quantizer. 57

4.16 Output spectrum with zero offset and 4 mV offset, showing an increase of the noise
floor. 58

4.17 Equivalent number of bit at output of a 16-bit an 18-bit algorithmic cover for
different offset values. 59

4.18 Error caused by capacitor mismatch for a 12-bit ADC. 59

5.1 Proposed second-order incremental ADC block diagram. 64

5.2 Swing of the first-integrator under constant input 0.707Vref . 64

5.3 Proposed second-order incremental ADC schematic diagram. 65

5.4 Recycling operational amplifier schematic diagram. 66

5.5 (a) Single step chopping clock; (b) The value of α1 with respect to kth clock period
for chopping. 68

5.6 Low-power comparator schematic diagram. 70

5.7 The block diagram of Smart-DEM implementation. 70

5.8 Clock phases used in Smart-DEM block. 71

5.9 State transition diagram of SDEM finite state machine. 72

5.10 The status of the weights in SDEM block with Vin = 0.926Vref . The range of
Dout is from 0 to 12 and the common mode level is 6. 72
xii LIST OF FIGURES

5.11 Insert-sorting algorithm example for the proposed second-order incremental ADC
(Vin = 0.926Vref and T = 2). 73
5.12 Multi-phase clock generator block diagram. 74
5.13 PVSMARTDEM chip microphotograph. 76
5.14 (a) Top layer of the mother board in Altium; (b) Fabricated 4-layer test board with
components soldered. 76
5.15 (a) Top layer of the daughter board in Altium; (b) Fabricated daughter board with
48-pin socket. 77
5.16 Measurement setup block diagram. 77
5.17 Measurement setup in laboratory. 78
5.18 Histograms of repeated measures with shorted inputs. 78
5.19 Measured output spectra. 79
5.20 Measured DNL. 80
6.1 First-order Σ∆ ADC block diagram. 85
6.2 Second-order Σ∆ ADC block diagram. 86
6.3 PSD (8096-point FFT) of Dout of the second-order Σ∆ ADC with ideal 5-bit DAC.
The input signal is a sinusoid waveform at normalized frequency 0.0021 whose
amplitude is -3 dBF S . The OSR is 16. 86
6.4 Third-order Σ∆ ADC block diagram. 87
6.5 Typical OTA-based analog summation block. 88
6.6 PSD (8096-point FFT) with σ = 0.1% mismatch for three 5-bit DACs. The input
signal is a sinusoid waveform at normalized frequency 0.0021 whose amplitude is
-3 dBF S . The OSR is 16. 88
6.7 Proposed 2-stage Σ∆ ADC block diagram (without integrator). 89
6.8 Voltage swing on VX node when −3dBF S sinusoid input at normalized frequency
0.0021 is given. 90
6.9 Proposed 2-stage Σ∆ ADC block diagram (with integrator). 91
6.10 Proposed 2-stage Σ∆ ADC schematic diagram. 92
6.11 Main operational amplifier schematic diagram. 93
6.12 Gain booster An schematic diagram. 94
6.13 Gain booster Ap schematic diagram. 95
6.14 Two stage comparator schematic diagram. 96
6.15 Three non-overlap clock phases generator. 96
 LIST OF FIGURES xiii

6.16 PVLPSD2 chip layout. 97

6.17 PSD (1024-point FFT) with respect to frequency. The input signal is a sinusoid
waveform at 562.5 kHz whose amplitude is -3 dBF S (BW = 2M Hz). The
sampling frequency is 64 MHz and the OSR is 16. 97

A.1 Second-order incremental ADC equivalent model with kT/C noise as input. 105
A.2 Third-order incremental ADC equivalent model with kT/C noise as input. 106
LIST OF TABLES

1.1 Research Target of Σ∆ and Incremental ADCs. 2

3.1 The relationship between Dout [10 : 1] and Vmis (k) for conventional DAC. 33

3.2 The relationship between Dout [10 : 1] and Vmis (k) for bipolar DAC. 34
4.1 Design parameters of incremental ADCs to achieve 18-bit. 48
5.1 The relationship between Dout [12 : 1] and Vmis (k). 69

5.2 Performance Comparison between proposed incremental ADC with state of the art. 80
6.1 Achievable SNR in terms of L, qb and OSR. 84
6.2 Phases and Operations. 91
6.3 Performance Comparison between proposed Σ∆ ADC with state of the art. 98

xv
ACKNOWLEDGMENTS

I would like to sincerely thank Professor Franco Maloberti for providing me the chance to explore such
an intriguing yet challenging field — the design of data converter and to work on two research projects,
which are PVSMARTDEM (17-bit 5kHz bandwidth incremental ADC) and PVLPSD2 (12-bit 2 MHz
bandwidth Σ∆ modulator). His knowledge and guidance during the past 3 years benefit me greatly, not
only arousing my interest in the study and research on microelectronics, but also nurturing my habit
and ability to think in an independent manner.
I would also like to acknowledge Edoardo Bonizzoni for his help on the PVSMARTDEM project,
in which he provided me with strong and continuous support from behavioural-level simulation to PCB
board and chip measurement. Moreover, I want to thank Alessandro D’Amato from Texas Instruments
(TI), helping me solve lots of problems on the transistor-level design and simulation in my first project.
Furthermore, I would like to thank Zhentao Li for assisting me in finding out the error of the digital
block of PVSMARTDEM project to prevent chip failure. Additionally, I would like to give credit to
my lab mates Marco Grassi, Aldo Peña Perez, Victor Rodolfo Gonzalez-Diaz, Oscar Belotti, Erika
Covi, Da Feng and Hadi Heidari for sharing the valuable knowledge during the past 3 years which
inspired me so much. I gratefully acknowledge Professor Shuming Chen from National University of
Defense Technology (NUDT) for his recommendation to send me abroad to study and also the Chinese
Scholarship Council (CSC) for the financial support.
Finally, I would never complete my doctoral study successfully without the support from my family.
I thank my brother Sen and especially my parents for everything they have done for my education. Most
importantly, I thank my girlfriend Jiannan Zhai who has been with me for almost 2 years and provides
me with encouragement and happiness all the time.

xvii
ACRONYMS

ADC Analog-to-digtal converter

AFF Analog feed-forward
CQFP Ceramic quad flat pack
CT Continuous time
CMOS Complementary metal-oxide-semiconductor
CMFB Common mode feedback
dBc dB to carrier
dBF S dB to full scale voltage
DAC Digital-to-analog converter
DEM Dynamic element matching
DFF Digital feed-forward or D flip-flop
DFM Digital frequency modulation
DSP Digital signal processing
DNL Differential non-linearity
DT Discrete time
DWA Data weighted averaging
ENOB Effective number of bits

Multi-Bit A/D Converters with High Resolution and Low-Power. xix

By Yao Liu
xx ACRONYMS

FCA Folded cascode amplifier

FFT Fast Fourier transform
FOM Figure of merit
FOMS FOM based on Schreier’s definition
FOMW Walden’s FOM
FSM Finite state machine
GBW Gain bandwidth product
GCS Gated current source
I&M Instrumentation and measurement
INL Integral non-linearity
MIM Metal insulator metal
NTF Noise transfer function
OSR Oversampling ratio
OTA Operational transconductance amplifier
PCB Printed circuit board
PCM Pulse code modulation
PSD Power spectrum density
QPSK Quadrature phase shift keying
RFCA Recycling folded cascode amplifier
SAR Successive approximation
SDEM Smart dynamic element matching
SFDR Spurious free dynamic range
SNR Signal to noise ratio
SNDR Signal-to-noise-and-distortion ratio
STF Signal transfer function
THD+N Total harmonic distortion plus noise
TI Time interleaved
VCCS Voltage control current source
VLSI Very large scale integration
ZCD Zero crossing detector
Σ∆M Sigma-Delta modulator
CHAPTER 1

INTRODUCTION

Analog-to-digital (A/D) and digital-to-analog (D/A) conversions are indispensable and ubiquitous in
the digitized world nowadays. The devices which convert a continuous-time continuous-amplitude
signal to the counterpart with discrete-time and discrete-amplitude is called A/D converters (ADCs).
On the contrary, the transformation from a discrete-time discrete-amplitude signal to a continuous-time
continuous-amplitude format is performed by D/A converters (DACs). Both ADC and DAC consist
the term data converter. The scope of this thesis, is to deal with high performance ADCs which are
realized by modern very-large-scale-integration (VLSI) technlogy.
Since the invention of pulse code modulation (PCM) [1], people from both academy and industry
dedicate themselves to the research and development of data converters for over 80 years. The driven
force underlying is the requirement of utilizing an ever-increasing computation capability from digital
computers to process signals in digital domain. However, due to the analog nature of the real world,
the original analog signals should be digitized before being processed in a digital fashion.
Generally, ADCs can be divided in 2 categories: Nyquist-rate type and oversampling modulator.
The Nyquist-rate ADCs is probably named after the famous Nyquist sampling theorem [2][3], which
states that the sampling frequency FS should be at least 2 times of the signal bandwidth BW in order
to keep the original information. For example, architectures such as pipeline and flash can be classified
into Nyquist-rate type ADCs, and the common features are large bandwidth and low-medium (< 12-
bit) resolution [4][5]. On the other hand, ADCs with FS > 2BW belong to oversampling type, which
generally have a better tolerance of circuit imperfections and are able to achieve high resolution (>
12-bit). However, the signal bandwidth of oversampling ADCs is smaller than that of Nyquist-rate
modulators, such as Σ∆ and incremental ADCs reported in [6]-[8].

Multi-Bit A/D Converters with High Resolution and Low-Power. 1

By Yao Liu
2 INTRODUCTION

1.1 Motivation and Objectives

In this thesis, we are focusing on the design of ADCs which are able to achieve high resolution.
In terms of the architectures, two types of ADCs have been selected for our study: the Σ∆ type and
incremental architecture. Since its original patent in [9] and circuit realization [10], Σ∆Ms have been
fully investigated by numerous researchers because they can achieve a high degree of insensitivity to
analog circuit imperfections. For discrete time (DT) Σ∆Ms, the resolution normally ranges from
14-bit to 21-bit with BW from 400 Hz to 2 MHz. While for continuous time (CT) Σ∆Ms, the
obtained resolution spanning from 10-bit to 14-bit, however, with BW from 10 MHz to 150 MHz [11].
Regarding incremental modulators, they share the same schemes with Σ∆Ms, providing a sample-
to-sample conversion. Incremental ADCs are suitable for applications such as instrumentation and
measurement (I&M), which usually require are high resolution, good linearity, low offset and lower
power dissipation [8]. The achieved resolutions for incremental ADCs ranges from 16-bit to 22-bit,
and the BW spans from DC up several kHz at most.
One of the most significant parameters of ADCs is the power efficiency, which is measured
by the figure of merit (FOM) discussed in Chapter 2. The low-power design for ADCs are self
evident, especially for modulators used in portable applications. For example, with modern CMOS
technologies, high speed ADCs can obtain data rates more than 20G SPS with power consumption
from 1.2 W to 10 W [12]. It is impractical to operate such blocks in the battery driven devices, such as
mobile phones and tablets.
For Σ∆Ms and incremental ADCs, one way to reduce to power dissipation is to utilize multi-bit
quantization. In general, modulators use comparator as quantizer and 2-level DAC do not suffer from
non-linearity problem, however, the swing of the op-amps is large and may result in op-amps operating
in slewing mode, leading to high power consumption of these blocks. On the contrary, the adoption
of multi-bit quantization can reduce the output swing of op-amps are thus, giving rise to significant
reduction of power consumption of op-amps. Nevertheless, the non-linearity of multi-bit DAC would
degrade the overall performance of the modulator, if the mismatch between unity element in multi-bit
DAC were not compensated for. The problem can be solved by dynamic or static digital correction
methods, such as the dynamic element matching (DEM) algorithms [13].

Table 1.1 Research Target of Σ∆ and Incremental ADCs.

ADC Type Resolution Bandwidth Power Consumption Technology

DT Σ∆M ≥ 12-bit 2 MHz < 2.0 mW 0.18 µm CMOS

Incremental ADC ≥ 18-bit 5 kHz < 0.5 mW 0.18-0.5 µm CMOS

The motivation of this work is to search for new architectures and circuit techniques to achieve high
resolution ADCs based on multi-bit quantization, which can be divided into 2 parts: 1) For Σ∆Ms,
since the current DEM algorithm is able to compensate for the mismatch, we focus on the architectures
and related circuit techniques for minimizing power consumption (e.g. op-amp reduction [6]). 2)
For incremental ADCs, because the existing DEM algorithms cannot properly compensate for the
mismatch of multi-bit DAC, the motivation is to search for a digital assistance method which is able to
suppress the non-linearity issue.
The aforementioned motivations lead us to the specifications of two ADCs, as shown in Tab. 1.1.
With regard to the DT Σ∆M, we targets at 12-bit resolution over 2 MHz bandwidth using 0.18 µm
CMOS technology. The power consumption should be within 2.0 mW. The incremental modulator,
 STRUCTURE OF THE THESIS 3

however, is expected to achieve 18-bit resolution over 5 kHz bandwidth adopting a mixed 0.18-0.5 µm
CMOS technology. The power dissipation should be less than 0.5 mW.

1.2 Structure of the Thesis

The thesis is organized in the following way: Chapter 2 introduces the background of high resolution
ADCs. The Σ∆ and incremental types are chosen and are investigated in detail. In Chapter 3, the
effects of mismatch between unity element in multi-bit DAC are studied for both Σ∆ and incremental
architectures. Because existing DEM algorithms are not able to fully compensate for the non-linearity
of multi-bit DAC in incremental ADCs, a Smart-DEM algorithm is proposed with simulation results
demonstrating its near-ideal error correction capability. Chapter 4 and 5 explain the design and
implementation of a 17-bit second-order incremental ADC. In order to achieve the target resolution,
Chapter 4 first analyses the key design parameters of incremental ADCs, namely the order of the
architecture, the resolution of quantizer and the number of clock periods per sample. The selection
of optimal incremental architectures with multi-bit quantization is then discussed. Based on Chapter
4, Chapter 5 describes the circuit implementation and measurement results of a 17-bit second-order
incremental ADC, which features with 3-bit DACs assisted by second-order Smart-DEM algorithm.
In Chapter 6, a single op-amp 0+2 second-order 12-bit Σ∆M is discussed. With the help of the first
stage, input swing of the second stage is significantly reduced, which relaxes the requirement of the
op-amp and allows low-power design. With 3-phase non-overlap clocks, the quantization error of the
second stage is shaped by a second-order high pass noise transfer funtion (NTF) while using only one
op-amp. The summary and conclusion of the thesis are given in Chapter 7. Limitations from kT/C
noise for different order incremental ADCs are derived in Appendix A. Finally, Appendix B lists the
author’s publications during his 3-year Ph.D. study.
4 INTRODUCTION

REFERENCES

1. A. H. Reeves, “Electric Signaling System”, U.S. Patent 2272070, Feb. 1942.

2. H. Nyquist, “Certain Factors Affecting Telegraph Speed”, Bell System Technical Journal, vol. 3, pp. 324-
346, Apr. 1924.
3. H. Nyquist, “Certain Topics in Telegraph Transmission Theory,” A.I.E.E. Transactions, vol. 47, pp. 617-644,
Apr. 1928.
4. F. Maloberti, Data Converters. Dordrecht: Springer, 2007.
5. B. Murmann, ADC Performance Survey 1997-2013. [Online]. Available:
http://www.stanford.edu/m̃urmann/adcsurvey.html, 2013.
6. A. Pena-Perez, E. Bonizzoni and F. Maloberti, “A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-
Amp Third-Order Σ∆ Modulator”, IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2107-2118, Sept. 2012.
7. A. Agnes, E. Bonizzoni, and F. Maloberti, “High-resolution multi-bit second-order incremental converter
with 1.5-µV residual offset and 94-dB SFDR”, Analog Integrated Circuits and Signal Processing, Springer,
vol. 72, pp. 531-539, 2012.
8. V. Quiquempoix et al., “A low-power 22-bit incremental ADC”, IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1562-1571, May 2005.
9. C. C. Cutler, “Transmission System Employing Quantization”, U.S. Patent 2927962, Mar. 1960.
10. H. Inose, Y. Yasuda and J. Murakami, “A Telemetering System by Code Modulation - ∆Σ Modulation”,
IRE Transcations on Space Electronics and Telemetry, vol. SET-8, issue 3, pp. 204-209, Sept. 1962.
11. Jose M. de la Rosa, “An Empirical and Statistical Comparison of State-of-the-Art Sigma-Delta Modulators”,
in Proc. 2013 IEEE Int. Symp. Circuits Syst.(ISCAS), pp. 825-828, May 2013.
12. P. Schvan et al., “A 24GS/s 6b ADC in 90nm CMOS”, in IEEE International Solid-State Circuits Conference
Digest of Technical Papers, pp. 544-634, Feb. 2008.
13. R. T. Baird and T. S. Fiez, “Linearity enhancement of multibit A/D and D/A converters using data weighted
averaging”, IEEE Trans. Circuits. Syst. II, vol. 42, pp. 753-762, Dec. 1995.
CHAPTER 2

A/D CONVERTERS FOR HIGH RESOLUTION

This chapter deals with the background of ADCs aiming for high resolution (≥12-bit). To start with, a
general introduction about ADCs’ history and current status is given. Since Σ∆ and incremental ADCs
are particularly suitable for achieving high resolution, they are selected and are detailed investigated,
spanning from basic ideas to state-of-the-art information. For Σ∆Ms, we focus on the architectures
and design techniques which can achieve more than 12-bit resolution and low-power dissipation,
such as op-amps reduction technique proposed in [1][2]. Due to the nature of high resolution of
incremental ADCs, we concentrate on structures and methods for attaining more than 18-bit and low-
power consumption. In particular, multi-bit quantization such as the one reported in [3] is a promising
method and is detailed analysed in this chapter.

2.1 Background on A/D Converters

2.1.1 A Brief History

Probably nowadays it is difficult to determine exactly when the first data converter was invented.
According to a survey on data converter history written by W. Kester, the earliest recorded data
converter can date back to the 18th century, and is not an electronic system at all, but hydraulic [4].
At that time, this system was built to meter the water and functions as an 8-bit DAC. Later, when the
Multi-Bit A/D Converters with High Resolution and Low-Power. 5
By Yao Liu
6 A/D CONVERTERS FOR HIGH RESOLUTION

telegraph and telephone were created, the requirement of increasing communication capability through
a single wire led to the invention of pulse code modulation (PCM) and consequently, pushed data
converters into the history. In 1937, Reeves designed one of the earliest all electronic data converters
which includes a 5-bit ADC and DAC [5]. It is worthy to point out that the 5-bit ADC provides a 6k
SPS output data rate by using vacuum tube technology.
In 1946, the first computer ENIAC was born and an increasing requirement of digital signal process
(DSP) demands for various ADCs for different applications. In 1954, an 11-bit 50k SPS ADC based on
vacuum tube technology was developed by B. M. Gordon, which is believed to be the first commercial
product of ADCs. However, the vacuum tube based data converters at that time are very bulky and
consume plenty of power. The inventions of transistor and later integrated circuit gradually change this
situation. These new technologies give rise to reduction on both the size and power dissipation of data
converters between 1950s to 1970s. In 1970s, the first generation of monolithic data converters were
born. For instance, the first complete monolithic ADC is AD571 based on successive approximation
(SAR) architecture in 1978, which achieved 10-bit resolution with 25 µs conversion time [6].
It is interesting to point out that almost all the basic architectures of data converters were invented
by 1960s, to name a few, flash, SAR, pipeline, Σ∆, incremental, etc. Perhaps the most well known
architecture is Σ∆ type. However, the basic idea underlying Σ∆ was first patented in 1960, [7], and
first implemented in 1962, [8], which are more than 50 years up to now.
The most significant driving force behind data converters since 1970s, however, is the continuous
development of transistor technologies. The complementary metal oxide semi-conductor (CMOS)
technology, because of its low static power, became dominant in late 1970s. The feature size of CMOS
transistors, decreased from around 125 µm in 1950s to less than 22 nm up to date, which means that
more transistors or functionality can be integrated on a single chip. This phenomenon is well described
in the famous Moore’s law which says that the number of transistors integrated on single chip doubles
every 18 months [9]. The continuously increased digital computation capability and the analog nature
of the world determine the widely usage of data converters. To date, data converters are used almost
everywhere, including sensor applications, wireless communication infrastructure, health care and life
science and so on. With regard to ADCs, the achieved resolutions range from 3-24 bits, while the
bandwidth spans from DC to more than 10 GHz [10]. According to the expectations reported in [11],
ADCs would be implemented in 10-11 nm CMOS technology with 40 mV power supply by 2020. The
expected F OMS is approximately 0.2 fJ/conv-step, while the state-of-the-art value was 2.2 fF/conv-
step [12].

2.1.2 Applications and Categories

As mentioned above, data converters are necessary components for the modern electric systems.
According to a market survey reported by [13], data converters are becoming the second largest analog
component after power management circuits, with unit shipments about 2.9 billion units in 2010 to an
expected quantity of around 4.7 billion units by 2015 (stand-alone data converters). Regarding ADCs,
the starting point of our study is however, to get familiar with the applications in which ADCs are used.
Moreover, for each type of application, corresponding ADC architectures and specifications should be
investigated. The typical applications for ADCs are listed as follows
I Instrumentation and Measurement Applications: includes applications such as digital
multimeter and portable weight scale [15]. The bandwidth of ADCs used in these applications is
limited from DC to few kHz, while the resolution requirement is generally more than 16-bit to even
24-bit. Moreover, these ADCs needs to achieve good linearity and low offset. Low-power consumption
is also an important factor especially for portable applications. ADCs based on incremental and dual-
 BACKGROUND ON A/D CONVERTERS 7

22

20
Incremental
18

Sigma-
Resolution (Bits)

16
Delta (DT)
14
Sigma-
12 Delta Pipeline
(CT)
10
SAR
8

Flash
6

4
10 100 1k 10k 100k 1M 10M 100M 1G 10G
Bandwidth (Hz)

Figure 2.1 ADC architectures for typical resolution and bandwidth requirements.

slope architectures are well suitable to meet these requirements, such as an third-order incremental
ADC which attained 22-bit [16].
I Biomedical and Health Care Applications: demand for low-power ADCs with low bandwidth
and low-moderate resolutions. For example, EEG, ECG and bioimplantable systems require ADCs
with data rate less than 200k SPS, and the resolution is between 6-10 bits [17]. In this case, ADCs
based on SAR architecture are good choices, such as a 9.1-bit 1k SPS SAR ADC consuming only 53
nW [18].
I Audio Applications: generally require ADCs with bandwidth from kHz to few hundreds kHz
and THD+N ranging from 60 dB to more than 100 dB. For instance, the voice communication
through telephone needs 4 kHz bandwidth and 60-70 dB THD+N. However, high quality DVD audio
requires 16-bit to 24-bit resolutions with a sampling rate from 44.1k SPS to 192k SPS. To meet these
requirements, Σ∆ ADCs are appropriate candidates. One example is a multi-bit Σ∆ ADC which can
obtain 24-bit resolution with 216k SPS output data rate [19].
I Wireless and Wireline Applications: demand for modulators with low-medium resolution and
large bandwidth. For instance, digital FM (DFM) and LTE-advanced require ADCs with banwidth
spanning from 20 MHz to 100 MHz with more than 10-bit resolution. In this case, continuous Σ∆
modulators are appropriate candidates to meet the specification [20]. However, applications such
as radar, software-defined radio and multi-channel satellite reception require 2.5-3.0G SPS data rate.
One solution is to use the time-interleaved (TI) SAR ADC with 3.6G SPS and 11-bit resolution [21].
Moreover, the 40Gb/s optical QPSK systems require sampling rate more than 24G SPS with 6-bit
resolution. In this case, a TI SAR ADC reported in [22] is a good choice which obtained 40G SPS
sampling rate and 6-bit resolution with a power consumption less than 1.5 W.
Fig. 2.1 illustrated conventional ADC architectures for typical resolution and bandwidth. It can be
seen that DT Σ∆ and incremental types dominate the region when 12-bit or more resolution and less
than 2 MHz bandwidth are required.
8 A/D CONVERTERS FOR HIGH RESOLUTION

2.1.3 Specifications
The performance of ADCs is determined by a large set of parameters. Readers may refer to more
detailed literature such as [23], to have a better understanding of the full set of specifications.
Nonetheless, the items listed below are of the most importance and are used in the overall thesis.

Digital Digital
Output Output

Gain
Error

Offset

Analog Input Analog Input

(a) (b)

Figure 2.2 Offset and gain error of ADCs.

I Resolution: determines the minimum quantity of analog signal which can be detected by ADCs.
For example, a 14-bit ADC with a full scale voltage (VF S ) of 2V can differentiate the minimum voltage
122.1µV . √
I Bandwidth: specifies the maximum frequency of input sinusoid signal which leads to a 2/2
attenuation of the amplitude after the A/D conversion.
I Signal-to-noise-ratio (SNR): indicates the ratio between signal power (PS ) and noise power
(PN ), which is always expressed in dB format as follows
PS
SN R = 10 × log10 (2.1)
PN
I Signal-to-noise-and-distortion ratio (SNDR): is similarly to the definition of SNR, except the
non-linear distortion term. The SNDR can be estimated as
PS
SN DR = 10 × log10 (2.2)
PN + PH
where PH refers to the total harmonic distortion generated by circuits or systems.
I Spurious free dynamic range (SFDR): is defined as the ratio of power between fundamental
signal to the power of largest harmonic distortion. SFDR is usually measured in dBc (dB to carrier) or
in dBF S (dB to full scale range).
I Offset: quantifies the amount by which the actual characteristic is linearly shifted from its ideal
position. Fig. 2.2 (b) illustrates the real characteristic, which is shifted up with an offset compared
with the ideal curve shown in Fig. 2.2 (a).
I Gain Error: is defined as the different slopes between the real characteristic curve and the ideal
transfer function, which can be seen in Fig. 2.2 (b).
I Differential non-linearity (DNL): is a term describing the deviation between 2 analog quantities
corresponding to adjacent input digital codes. Ideally, analog voltages corresponding to 2 adjacent
 BACKGROUND ON A/D CONVERTERS 9

Digital Digital
Output Output
DNL
+1LSB
INL

Analog Input Analog Input

(a) (b)

Figure 2.3 DNL and INL of analog-to-digital converters.

digital codes are exactly one least significant bit LSB apart. DNL is measured as the largest deviation
in terms of 1 LSB step, which is shown in Fig. 2.3 (b).
I Integral non-linearity (INL): is described as the deviation of an actual transfer function from
the ideal characteristic, which is represented in LSB or percent of full-scale range. The INL magnitude
depends on the position chosen for ideal characteristic. Here, we use end-point INL as illustrated in
2.3 (b).
I Effective number of bits (ENOB): measures the signal-to-noise and distortion ratio with bits.
SNDR in dB and ENOB are linked by

SN DR − 1.76
EN OB = (2.3)
6.02

I Figure of merit (FoM): is introduced in order to compare the performances between various
ADCs which may differ widely in architectures and specifications. One of the most commonly used
figure of merit is known as “Walden’s” FOM [24] which is defined as

P
F OMW = (2.4)
2BW × 2EN OB

where P is the power consumption of the ADC. F OMW is an key parameter to measure ADC’s power
efficiency and it is expressed in pico-joules per conversion step (pJ/conv-step). Another popular figure
of merit is Schreier’s definition which can be described as

BW
F OMS = SN DR + 10log10 (2.5)
P

F OMS is expressed in dB and its value increases for better performing modulators. According to [10],
both F OMW and F OMS work well only across a limited range of SNDR. For low-resolution ADCs,
evaluation based on F OMW is more suitable, whereas F OMS is more appropriate for modulators
targeting at high resolutions.
10 A/D CONVERTERS FOR HIGH RESOLUTION

1.E+07

1.E+06

1.E+05

1.E+04
P/fsnyq [pJ]

1.E+03

1.E+02
ISSCC 2013
VLSI 2013
1.E+01
ISSCC 1997-2012
VLSI 1997-2012
1.E+00
FOMW=10fJ/conv-step
FOMS=170dB
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR @ Nyquist [dB]

Figure 2.4 Power efficiency of ADCs with respect to SNDR.

2.1.4 State of the Art of ADCs

In this subsection, we use the data reported in [10] to investigate state of the art ADCs. The sources of
the data are from the results published at IEEE International Solid-State Circuits Conference (ISSCC)
and the VLSI Circuit Symposium since 1997. Fig. 2.4 plots the power per Nyquist sample with respect
to the obtained SNDR. As seen in Fig. 2.4, several ADCs with the best power efficiency in terms of
F OMW were published in ISSCC 2013, such as a 10/12-bit 40k SPS SAR ADC with F OMW 2.2/2.7
fJ/conv-step [12]. Regarding high resolution ADCs, a 6.3 µW 20-bit incremental ADC was proposed
in [25] with a F OMS of 182.7 dB.
Besides the power efficiency, the achievable bandwidth is also a key parameter. This is because
that, in general, when a design is pushed toward the speed limits under a certain technology, the
power efficiency is always sacrificed [26]. Fig. 2.5 illustrates the obtained ADCs’ bandwidth in terms
of SNDR. The dash line represents the performance of an ideal sampler with sinusoid input and a
sampling clock with 100 fsRMS jitter. It can be noticed that ADCs with highest bandwidth over all the
resolutions should use a sampling clock with jitter less than 1 psRMS . However, in order to attain an
ADC comparable with state of the art, a better sampling clock with jitter lower than 100 fsRMS should
be adopted. For instant, the TI pipeline ADC proposed in [27] uses a sampling clock with measured
jitter 70 fsRMS , which achieved 14-bit resolution with a 2.5 GSPS output data rate.

2.2 Σ∆ A/D Converters

As mentioned before, one of the most significant breakthroughs in the field of data conversion is Σ∆
modulation. On the basis of oversampling and quantization noise shaping, Σ∆Ms are able to tolerate
circuit imperfections and thus, the strict requirements of the analog components can be relaxed. In this
section, we shall starts from the first-order Σ∆M to explain the underlying theory. Moreover, high-
order structures are investigated to show the tradeoff between different sets of design parameters. The
 Σ∆ A/D CONVERTERS 11

1.E+11
ISSCC 2013
VLSI 2013
1.E+10
ISSCC 1997-2012
VLSI 1997-2012
1.E+09
Jitter=1psrms
Jitter=0.1psrms
1.E+08
fin,hf [Hz]

1.E+07

1.E+06

1.E+05

1.E+04

1.E+03
10 20 30 40 50 60 70 80 90 100 110 120

SNDR [dB]

Figure 2.5 Conversion bandwidth of ADCs versus SNDR.

third part will discuss state of the art Σ∆Ms architectures and circuit techniques in terms of low-power
dissipation.

2.2.1 First-Order Σ∆ A/D Converter

ɛq
Vin Z-1 Dout
 -1
1̶Z

DAC

Figure 2.6 First-order Σ∆ ADC block diagram.

A conventional Σ∆ ADC consists of a delayed integrator, a multi-bit quantizer and corresponding

DAC, as depicted in Fig. 2.6. The study in z domain gives rise to the transfer function as below

Dout (z) = Vin (z)z −1 + (1 − z −1 )q (z) (2.6)

As seen in (2.6), both input signal Vin (z) and quantization error q (z) contribute to digital output
Dout (z), by multiplying different transfer functions. For Vin (z), the transfer function is called signal
12 A/D CONVERTERS FOR HIGH RESOLUTION

transfer function (STF). The transfer function of q (z), however, can be known as noise transfer
function (NTF). Thus, using these terms, (2.6) can be rewritten as

Dout (z) = Vin ST F (z) + q (z)N T F (z) (2.7)

where ST F (z) = z −1 and N T F (z) = 1 − z −1 . Since z = ejω (FS normalized to 1 Hz) and by
mathematical calculations, the NTF of first-order Σ∆M can be represented by

N T F (jw) = 1 − e−jω (2.8)

Thus,
ω
|N T F (w)|2 = 4sin2 ( ) (2.9)
2
The result shows that the quantization error q is high-pass shaped by |N T F (w)|2 . Fig. 2.7 plots the
power spectrum density (PSD) of Dout of first-order Σ∆ ADC. The input signal is -3 dBF S sinusoid
waveform at normalized frequency 0.0016. A 2-bit quantizer is used and the DAC has 5 levels. The 2
reference voltages are Vref and -Vref . The full scale voltage VF S is thus equal to 2Vref . As noticed
in Fig. 2.7, the PSD of original q is supposed to be white, is high-pass shaped with 20 dB/dec. The
achieved SNR is 42.6 dB, which is equivalent to 6.78-bit.

0
-1 0 S N R = 4 2 .6 d B
-2 0 E N O B = 6 .7 8 b its
-3 0
-4 0
-5 0
(d B )

-6 0
-7 0
P S D

-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 2.7 PSD (8096-point FFT) of Dout of the first-order Σ∆ ADC with -3 dBF S sinusoid waveform input
at normalized frequency 0.0016. The OSR is 16.

Besides noise shaping, the second key element of Σ∆ modulation is oversampling. In order to
quantitatively describe it, the oversampling ratio (OSR) is defined as FS /(2 × BW ). For a fixed BW ,
a higher OSR can be obtained by increasing FS . Consequently, the SNR of Σ∆Ms is improved. The
reason is that, considering a unilateral representation of the PSD, the power of quantization error is
distributed over the first-Nyquist zone. The SNR is calculated by the ration between the power of
signal and the power of the noise within BW . Thus, larger OSR gives rise to reduction of power of
quantization error in the band of interest. In this case, the SNR of the corresponding Σ∆M is improved.
The resolution of quantizer bq can also affect the performance of Σ∆Ms, where bq is defined as
log2 (VF S /VLSB ). Generally, the quantization error can be regarded as white noise, whose power can
 Σ∆ A/D CONVERTERS 13

be estimated by
2
VLSB
PN Q = (2.10)
12
As seen in (2.10), by increasing bq , the quantization interval VLSB can be smaller, leading to a
reduction of the power of quantization error PN Q .

ɛq
Vin 0.5Z-1 2Z-1 Dout
 -1
 -1
1̶Z 1̶Z

DAC1 DAC2

Figure 2.8 Second-order Σ∆ ADC block diagram.

0
-1 0 S N R = 5 8 .7 d B
-2 0 E N O B = 9 .4 5 b its
-3 0
-4 0
-5 0
P S D (d B )

-6 0
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 2.9 PSD (8096-point FFT) of Dout of the second-order Σ∆ ADC with -3 dBF S sinusoid waveform
input at normalized frequency 0.0016. The OSR is 16.

With the previous discussion, the resolution of first-order Σ∆M is determined by OSR and bq . The
relationship between SNR and those design parameters can be expressed as
SN R1ord,Σ∆ = 6.02bq + 1.76 − 5.17 + 9.03 × log2 (OSR) (2.11)

2.2.2 High-Order Σ∆ A/D Converter

The performance of first-order Σ∆ ADC is limited. One method of boost the performance is increase
the order of the structure. Fig. 2.8 shows a second-order Σ∆M which consists of 2 delayed integrators
14 A/D CONVERTERS FOR HIGH RESOLUTION

with different coefficients, a multi-bit quantizer and DAC. The study in z domain leads to the transfer
function as below

Dout (z) = Vin (z)z −2 + q (z)(1 − z −1 )2 (2.12)

where q is high-pass shaped by a second-order NTF. The benefit of second-order structure against
first-order scheme is obvious: the power of quantization error within the band of interest experiences
a larger suppression because of a second-order NTF. To compare the performance with the first-order
architecture, same design parameter are chosen bq = 2 and OSR = 16. As noticed in Fig. 2.9, the
PSD of q is shaped with 40 dB/dec due to the second-order high-pass NTF. The achieved SDR is 58.7
dB, which is equivalent to 9.45-bit.
For a Nth-order Σ∆ ADC whose NTF and STF has a denominator equal to 1, the SNR can be
estimated as follows
π2 L
SN RLord,Σ∆ = 1.78 + 6.02qb − 10log2 + 3.01(2L + 1)log2 (OSR) (2.13)
2L + 1
where L, qb and OSR are the 3 key parameters when designing Σ∆Ms. The optimum designs
of Σ∆ ADCs are attained by a good tradeoff between these parameters. In general, high-order
modulators guarantee high resolution, but a large number of op-amps are needed, which means the
power dissipation will be increased. Moreover, high OSR grants good resolution at the cost of increased
FS , which leads to high power consumption in the overall circuit. The use of multi-bit architectures
benefits the modulator with extra resolution, however, it increases the design complexity with more
comparators required in the quantizer. Another issue comes from the non-linearity of the multi-bit
DAC, which should be carefully compensated for in order to prevent performance degradation.

2.2.3 State of the Art of Σ∆Ms

According to previous subsections, we know that the selection of 3 parameters: the order of the
modulator L, the resolution of the quantizer bq and the oversampling ratio OSR affects the modulator’s
performance. Here, we analyse the architectures and design techniques of state of the art Σ∆Ms based
on these 3 parameters, in order to achieve highest power efficiency (FOM).
For a fixed sampling frequency FS , double sampling is a very attractive technique to obtain an
equivalent sampling frequency 2FS . This solution boosts the operation speed of SC based integrators
because op-amps are integrating charge on both phases [28]. Fig. 2.10 illustrates a double sampling
integrator with 2 non-overlap clocks φ1 and φ2 . It can be noticed that 2 groups of input sampling
capacitors allows charge injection in both phases and keep op-amp busy all the time. Further, ADC
architectures on the basis of doubling sampling methods increase the resolution, without consuming
extra power. Unfortunately, several drawbacks limit the use of double sampling techniques. The first
is that, considering the simplest implementation of double sampling integrator shown in Fig. 2.10, any
mismatch between the 2 sampling capacitors gives rise to the folding of the power around FS /2 on
spectrum to the band of interest. This problem can be solved by adding an SC integrator with a fully
floating input branch [29] or with a modified version reported in [30]. The other limitation is due to
the timing constraint. Since the integrator uses both clock phases for charge injection, the quantization
operation and the DEM technique should be performed between the gap of the non-overlap clocks.
A good solution to solve this issue is to add 2 branches with one-unit-time delay in the modulator’s
architecture, as reported in [31].
The aforementioned double sampling techniques increase the OSR with a fixed L and qb . The
other way of enhancing ADCs performance is enlarge L with minimum number of op-amps, such as
 Σ∆ A/D CONVERTERS 15

Φ 1 C1 Φ 2
Vin C3
Φ2 Φ1
Vout
A0
Φ2 C2 Φ1

Φ1 Φ2

Φ1
Φ2
nT (n+1)T

Figure 2.10 Schematic of a double sampling integrator implemented with SC circuits.

ɛq
Vin Dout
 H1(z)  H2(z)  HN(z)

b1 b2 bN

DAC1 DAC2 DACN

Figure 2.11 Nth-order Σ∆M with multiple feedback paths block diagram.

ɛq
Vin Dout
 H1(z) H2(z) HN(z)

bT

DAC

Figure 2.12 Nth-order Σ∆M without intermediate feedback paths block diagram.
16 A/D CONVERTERS FOR HIGH RESOLUTION

the solution reported in [2]. Fig. 2.11 illustrated the block diagram of a general Nth-order Σ∆M with
multiple feedback paths. Using the method proposed in [2], it is possible to remove all the intermediate
feedback paths, giving rise to the scheme plotted in Fig. 2.12, where

b2 bN
bT = b1 + + ... + (2.14)
H1 (z) H1 (z)H2 (z)...HN −1 (z)

After removing the intermediate feedback paths, it is possible to combine N integrators to a single
block, which can be expressed as
z −p
HT = (2.15)
(1 − z −1 )N
where N is the number of integrators and p is the number of delays along the signal path. With this
technique, a second-order Σ∆M using single op-amp was proposed in [32], which achieved a peak
SNDR 63 dB over 1.94 MHz bandwidth. Recently, another op-amp reduction technique was presented
in [1], in which a low-power SC third-order Σ∆ modulator using only one op-amp was proposed. The
scheme employs swing reduction techniques so as to relax the requirements on the swing and slew-rate
of all the internal nodes. Measurement results show that the modulator achieved 84 dB peak SNDR
and 88 dB dynamic range over 100 kHz signal bandwidth. The total power consumption is 140 µW
and corresponding F OMW is 54 fJ/conv-step. In [33], a third-order DT Σ∆ modulator was proposed
which uses two op-amps. The quantizer is realized on the basis of the traditional dual slope ADC,
however, with a small modification in the discharging phase, a first-order quantization noise shaping is
attained. In this case, a second-order loop filter using two op-amps together with a first-order quantizer
forms the third-order Σ∆ architecture.
The resolution of quantizer bq can also be boosted to increase the modulator’s performance. In [34],
a Σ∆ ADC using a noise-shaped two-step integrating quantizer was presented. The quantizer used
in the scheme can attain 8-bit resolution and thus, the OSR is drastically reduced. The measurement
results shows that the prototype achieved 70.7 dB peak SNDR at 80MHz FS (OSR=8) and F OMW is
280 fF/conv-step.
Innovation is in progress not only in architecture level, but also in the field of circuit design. For
instance, the Σ∆M proposed in [35] utilizes class-C inverter instead of op-amp, hence, the required
power consumption is significantly reduced. It was demonstrated that the prototype attained 81 dB
peak SNDR over 20 kHz bandwidth. The power consumption is 36 µW from a 0.7 V supply and the
F OMW is 98 fJ/conv-step. Moreover, when Σ∆ architectures adopt op-amp based integrators, the
output swing of op-amps should be minimized in order to relax the requirements on slew rate and
bandwidth. In this case, the analog feed-foward (AFF) and digital feed-forward (DFF) techniques can
be utilized, such as the Σ∆M reported in [36].

2.3 Incremental A/D Converters

Incremental ADCs are always used in instrumentation and sensing applications, such as readout
of bridge transducers and biomedical acquisition systems [37][38]. The advantages of incremental
ADCs are good linearity, high resolution, low offset and low power dissipation. Although sharing
the same structures of Σ∆ modulators (Σ∆M s), incremental ADCs reset the output of op-amps
every N clock periods and provide a sample-to-sample conversion, thus they can be classified as
Nyquist-rate data converters. This section begins with the basic operation of first-order and high-order
incremental modulators, and then follows the discussion of incremental architectures using comparator
 INCREMENTAL A/D CONVERTERS 17

as quantizer and multi-bit quantization. Finally, state-of-the-art incremental ADCs’ architectures and
circuit techniques are introduced.

2.3.1 First-Order Incremental Converters

Incremental ADC comes from the combination of Σ∆M and dual-slope ADC, which was first
presented by Van De Plassche in 1978 [39]. Fig. 2.13 shows the block diagram of a first-order
incremental ADC. It is constituted of a delayed-integrator, a comparator and a 2-level DAC. The
working principle is as follows: at the beginning of a conversion cycle, the output of the integrator
is reset. For incremental ADCs, the frequency of input signal ranges from DC to few kHz at most,
thus Vin can be regarded as constant Vin . In each clock cycle, Vin subtracts Vout and the difference
is accumulated at the output of integrator, where Vout is the analog version of the digital output Dout .
Since a comparator is used in the modulator, Dout has two possible values. Whenever the input of the
comparator goes above zero, Dout becomes 1, and the corresponding Vout is Vref . Otherwise, Dout
equals to -1 and Vout = −Vref . At the end of the N th clock period, the residue voltage at the output
of integrator is
N
X −1 N
X −1
Vres (N ) = Vin − Dout (i)Vref (2.16)
i=1 i=1
where −Vref < Vres (N ) < Vref holds. This is ensured by the stability of the feedback loop. Thus,
the input signal can be estimated as
PN −1
i=1 Dout (i)Vref Vres (N )
Vin = + (2.17)
N −1 N −1

RESET

Vin Z-1 Vres Dout


1 ̶ Z-1

Vout
DAC

Figure 2.13 First-order incremental ADC block diagram.

As seen in (2.17), the first term of right-hand side is the digital estimation of Vin . The quantization
error is the second term, which is determined by the residue voltage of integrator Vres (N ) and the
number of clock cycles per sample N . Here, q is used to represent the quantization error as below
Vres (N )
q = (2.18)
N −1
The quantization error q should be within half quantization interval VLSB , thus
VLSB VF S
|q | < ; VLSB = R (2.19)
2 2 1ord
18 A/D CONVERTERS FOR HIGH RESOLUTION

where VF S = 2Vref is the full scale voltage and R1ord is the maximum resolution that the first-order
incremental scheme plotted in Fig. 2.13 can achieve. By using (2.16)-(2.20), the resolution of first-
order incremental scheme can be derived as
Vres
R1ord = = log2 (N − 1) (2.20)
max{|q |}

2.3.2 High-Order Incremental Modulators

f1

f2
RESET RESET

Vin Z-1 Z-1 Vres Dout

c1  c2 
1 ̶ Z-1 1 ̶ Z-1

c1

Vout
DAC

Figure 2.14 Second-order feed-forward incremental modulator block diagram.

Unfortunately, the conversion efficiency of a first-order incremental ADC is low. Methods for
increasing the resolution are augmenting the number of clock periods N and using more effective
schemes with cascaded accumulators. High-order incremental ADCs, therefore, contain multiple
integrators with reset. The key point is to increase the accumulation efficiency, maintain the stability
of structure and keep Vres (N ) minimized [16], [40]-[44].
In order to maintain stability of the loop filter, distributed feedback or feed-forward paths are usually
used in incremental ADCs. Although the inaccurate feed-forward coefficients cause error along the
accumulation path, it is just a gain factor since the input signal is almost constant. However, it is quite
difficult to analyse the error due to the inaccurate feedback coefficients. This is because the feedback
signal varies in time and injects signal in different locations. Based on the above analysis, for high-
order incremental ADCs, the recommended way to maintain stability is to use multiple feed-forward
paths and the adoption of more than 1 DAC should be prevented.
A conventional second-order incremental modulator is discussed here to show how the conversion
efficiency changes compared with the first-order structure. As seen in Fig. 2.14, this structure contains
2 delayed-integrators. Along the accumulation path there are 2 coefficients c1 and c2 . In order to
keep the loop stable, two feed-forward paths are included with coefficients f1 and f2 . This scheme
also employs a comparator and 2-level DAC. Using the same method, Vres (N ) for this second-order
architecture can be written as
N
X −1 X
i−1 N
X −1 X
i−1
Vres (N ) = c1 c2 Vin − c1 c2 Dout (i)Vref (2.21)
i=1 j=1 i=1 j=1

Similarly, the input signal can be represented as a digital estimation part and a quantization error as
follows
 INCREMENTAL A/D CONVERTERS 19

f1

f2

f3

fL
RESET RESET RESET

Vin Z-1 Z-1

Z-1 Vres Dout
c1  c2 cL 
1̶Z -1
1̶Z -1
1 ̶ Z-1

c1

Vout
DAC

Figure 2.15 Lth-order incremental ADC architecture.

PN −1 Pi−1
c1 c2 i=1 i=j Dout (i)Vref Vres (N )
Vin = + (2.22)
M M
where M is a constant which can be expressed as

c1 c2 (N − 1)(N − 2)
M= (2.23)
2!
Notice that M is a quadratic function of N . It means that the quantization error of second-order
architecture can be much smaller than the counterpart of first-order scheme, provided a relative large
N is used. The resolution of the second-order structure is derived as

c1 c2 (N − 1)(N − 2)
R2ord = log2 (M ) = log2 (2.24)
2!
To compare the conversion efficiency of first-order and second-order incremental ADCs, (2.20) and
(2.24) are used with N = 1024 and c1,2 = 1. The reason that c1 and c2 are chosen to be 1 is to
simplify the situation. The stability is ensured with proper selection of f1 and f2 . Both calculations
and simulation results show that the first-order structure achieves a maximum resolution 10-bit, while
the second-order architecture can obtain 19-bit.
An Lth-order incremental modulator with multiple feed-forward paths, feedback paths and coefficients
is illustrated in Fig. 2.15. It consists of L delayed integrators, a comparator and a 2-level DAC. Along
the accumulation path, there are L different coefficients c1,2,...,L . Moreover, to maintain the stability of
the loop filter, L feed-forward paths are introduced with coefficients f1,2,...,L . In order to estimate the
resolution of Lth-order incremental ADC, an equivalent model is plotted in Fig. 2.16. In this model,
the feed-forward paths are removed since the purpose of them is to maintain stability and they do not
affect the conversion efficiency. Using this model, it can be seen that during N clock periods, the
difference between c1 Vin and c1 Vout is continuously injected at the input of the first integrator and
20 A/D CONVERTERS FOR HIGH RESOLUTION

RESET RESET RESET

Vin Z-1 Z-1 Z-1 Vres

c1  -1
c2 -1
cL
1̶Z 1̶Z 1 ̶ Z-1

c1

Vout

Figure 2.16 The equivalent model of Lth-order incremental ADC.

then accumulates though L integrators. Hence, at the end of N clock period, the final accumulation
result can be expressed as
N 1 −1
−1 iX iL−1 −1
X X
Vres (N ) = c1 c2 ...cL ... {Vin − Dout (iL )Vref } (2.25)
i1 =1 i2 =1 iL =1

Thus
N 1 −1
−1 iX iL−1 −1
1 X X Vres (N )
Vin = c1 c2 ...cL ... Dout (iL )Vref + (2.26)
M i =1 i =1 i =1
M
1 2 L

where
(N − 1)(N − 2)...(N − L)
M = c1 c2 ...cL (2.27)
L!
By combining (2.25)-(2.27), the resolution of Lth-order incremental converter can be written as

c1 c2 ...cL (N − 1)(N − 2)...(N − L)

RLord = log2 (2.28)
L!

2.3.3 Multi-Bit Incremental Converters

In general, the quantizer adopted in incremental ADCs is 2-level comparator, so as to avoid the non-
linearity of multi-bit DAC due to the mismatch of unity elements. However, the drawback is that the
output swing of integrators is large and may result in op-amps working in slewing mode. When the
order of the scheme L is larger than 2, stability of the loop demands for the use of fractional coefficients
along the accumulation path, which degrades the conversion efficiency. For example, in the third-order
modulator described in [16], c1 = 0.5674, c2 = 0.5126, and c3 = 0.3171. Using (2.28) with N = 128,
the resolution is 14.9-bit, which is 3.4-bit less than the maximum achievable (with c1,2,3 = 1). Another
case is the fourth-order modulator reported in [42]. Coefficients c1 , c2 , c3 and c4 are 0.25, 0.4, 0.22, and
0.11, respectively. With N =128, the achievable resolution is 14.6-bit while the maximum theoretical
resolution is 23.3-bit. The resolution loss in this case is, hence, more than 8.7-bit.
On the contrary, incremental ADCs based on multi-bit quantization and DAC do not suffer from
aforementioned problems. Nonetheless, the non-linearity of multi-bit DAC of incremental ADCs needs
to be properly compensated for. For Σ∆Ms, static or dynamic calibration such as dynamic-element-
matching (DEM) are effective ways to compensated for non-linearity of DAC. However, those methods
are not suitable for incremental ADCs. To our best knowledge, very few papers studied this problem.
As an alternative solution reported in [3], a second-order incremental structure uses a 3-bit intrinsic
linear DAC and achieved 18-bit resolution.
 INCREMENTAL A/D CONVERTERS 21

S1
1

S2
2
RESET RESET

Vin Z-1 Z-1 Vres Dout

1  1 
1 ̶ Z-1 1 ̶ Z-1

Vout
DAC

Figure 2.17 Second-order feed-forward multi-bit incremental ADC block diagram.

To begin with the discussion of multi-bit incremental ADCs, let us consider a second-order structure
shown in Fig. 2.17. Compared with the scheme in Fig. 2.14, it can be noticed that the comparator and
2-level DAC are now replaced with multi-bit counterparts. Moreover, the coefficients are selected
with values c1,2 = f1 = 1 and f2 = 2. To understand how the multi-bit DAC enhances the overall
performance of the modulator, rewrite (2.21) to a multi-bit version
N
X −1 X
i−1 N
X −1 X
i−1
Vres (N ) = Vin − Dout (i)Vref m (2.29)
i=1 j=1 i=1 j=1

VF S
Vref m = (2.30)
2bq
where Dout ∈ [−2bq −1 , 2bq −1 ] and bq is the resolution of the quantizer. Thus, Vin can be described as
PN −1 Pi−1
i=1 j=1 Dout (i)Vref m Vres (N )
Vin = + (2.31)
M M
where

(N − 1)(N − 2)
M= (2.32)
2!
When comparing (2.23) (c1,2 = 1) and (2.32), it can be found that M for second-order structures
with 2-level quantization and multi-bit quantizer are the same. It means that multi-bit quantization
does not contribute extra bits performance, unless the residue voltage Vres (N ) can be further reduced.
This can be solved by introducing 2 switches S1 and S2 in the scheme as plotted in Fig. 2.17. The
operation principle is as follows: during the reset clock period, S1 and S2 are closed while the output
of integrators are reset. From first to (N − 1)th clock period, the modulator works normally with S1
and S2 closed. At N th clock period, S1 and S2 are opened. Vres (N ) is digitized by the multib-bit
quantizer and the generated digital code is Dout (N ). Thus, a reduced version of residue voltage can
be expressed as
Vdres = Vres (N ) − Dout (N )Vref m (2.33)
Using (2.33), (2.31) can be reorganized as
22 A/D CONVERTERS FOR HIGH RESOLUTION

PN −1 Pi−1
i=1 j=1 Dout (i)Vref m Dout (N )Vref m Vd
res
Vin = +( + ) (2.34)
M M M
Since −(1/2)Vref m < Vd res < (1/2)Vref m , by using (2.34), the resolution of the multi-bit second-
order incremental modulator can be estimated as

(N − 1)(N − 2)
R2ord = log2 + bq (2.35)
2!
According to (2.24) and (2.34), the resolution of second-order multi-bit incremental modulator
increases bq -bit with respect to the counterpart using a 2-level quantization and DAC.
In general, for an Lth-order incremental ADC with bq -bit quantization and ideal DAC, the expected
resolution is
c1 c2 ...cL (N − 1)(N − 2)...(N − L)
RLord = log2 + bq (2.36)
L!
The above analysis shows that multi-bit incremental ADCs can boost the resolution with bq -bit.
Other advantages are 1) reduced swing of integrators leading to low-power design; 2) better stability
giving rise to larger coefficients c1,2,...,L along accumulation path, which prevent degradation of
conversion efficiency. Nonetheless, incremental ADCs using multi-bit quantization suffers from the
non-linearity of multi-bit DAC and kT/C noise limitation, which will be discussed later in Chapter 3.

2.3.4 State of the Art of Incremental Converters

In order to obtain high resolution incremental ADCs, the order of the scheme L can be increased and
the residue voltage Vres should be minimized. In 2006, a 22-bit third-order incremental modulator
using 2-level quantization was reported in [16], whose scheme is the same as one plotted in Fig 2.15
with L = 3. To the best of author’s knowledge, it is the incremental modulator which achieved highest
resolution in the open literature up to date. Meanwhile, a fourth-order design was proposed in [42] and
the obtained resolution is 16-bit.
To minimize Vres , a second-order incremental scheme with extended-range was report in [44]. The
second-order architecture is the same as the one plotted in Fig. 2.14, while the second-stage is a 9-bit
SAR modulator. The key point is that after the first-stage generates a coarse residue voltage Vres , the
9-bit SAR stage uses Vres to produce a refined residue voltage Vdres and a digital code. In this case, Vres
is reduced and the performance of the modulator is improved. With the extended-range technique, the
maximum achieved SNDR of the second-order modulator proposed in [44] is 86.3 dB and the F OMW
is 1.46 pJ/conv-step. Another technique which is able to reduce Vres and avoid using extra stage
was reported in [46][47]. For example, the modulator proposed in [46] uses a 2-step conversion: the
first-step is to use a conventional second-order feed-forward structure as illustrated in Fig. 2.14; the
second-step is, however, to reconfigure the hardware to a first-order incremental scheme. Specifically,
the second op-amp is configured as a voltage buffer to maintain Vres and the first op-amp is adopted
to perform a first-order incremental operation. Compared with the aforementioned extended-range
technique, the hardward reconfiguration technique is more efficient in terms of power consumption,
however, at the expense of a lower output data rate.
In recent years, novel incremental architectures base on multi-bit quantization and DAC appear. As
discussed previously, multi-bit incremental architectures benefit from better conversion efficiency and
stability than schemes with 2-level DAC. Nonetheless, the non-linearity of multi-bit DAC needs to be
properly compensated for. In [3], an intrinct 3-bit DAC is adopted to avoid non-linearity problem. The
3-bit DAC, however, uses a single capacitor and jnjects the charge at a speed of 8 times of sampling
 INCREMENTAL A/D CONVERTERS 23

frequency according to the digital output. Although the linearity of 3-bit DAC is guaranteed, the power
dissipation of the second-order modulator is 6 mW. Another example can be seen in [45], where a third-
order incremental architecture with a 5-level DAC was proposed. The modulator uses a foreground
calibration mode to measure the mismatch of 4 unity capacitors. During normal conversion mode, the
digital output is calibrated with the mismatch values in the digital domain. The obtained SNDR is 81.5
dB and the total power consumption is 6.7 mW.
Besides DT incremental ADCs, designs of CT counterparts are also in progress. A first-order CT
incremental modulator is adopted to build a 16-channel neural interface, due to its implicit anti-aliasing
filtering property [37]. Garcia extended the CT incremental converter to a third-order structure, which
greatly enhances the conversion efficiency with respect to the first-order counterpart, giving rise to a
design with peak SNDR 64 dB and 96 µW power consumption over 2 kHz bandwidth [38]. The low-
power consumption is due to the requirement of bandwidth and slew-rate is more relaxed in CT ADCs
than that of DT modulators.
Novelties of the designs mentioned above are mostly from architecture level. Aiming for low-
power dissipation with good F OM , several novel circuit techniques are used in incremental ADCs
published recently [25] [48]. For instance, an incremental modulator based on zoom ADC scheme
was reported in [25], which achieved 20-bit resolution. To reduce the power consumption, traditional
op-amp based integrators are replaced with inverter based counterparts, which gives rise to a total
power consumption of 6.3µW and the best F OMS = 182.7dB up to now. In [48], a conventional
second-order incremental structure is implemented with a self-timed technique instead of traditional
synchronized clock scheme. The charge transfer circuits based on gated current source (GCS) and zero-
crossing detector (ZCD) are utilized to replace the op-amp based integrators. This design obtained
14-bit resolution, which is relatively low compared with the already achieved performance using
conventional schemes and circuit techniques. However, it is still a good trial in order to implement
all digital incremental ADCs, especially with the continuously scaled CMOS technology.
24 A/D CONVERTERS FOR HIGH RESOLUTION

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CHAPTER 3

DYNAMIC CONVERSION OF MISMATCH

The non-linearity of DAC is caused by the mismatch between unity elements, which affects the overall
performance of the modulator. In this chapter, we first discuss the performance degradation of both
incremental and Σ∆ ADCs due to the non-linearity of DAC and then the error correction methods.
Regarding Σ∆ ADCs targeting to more than 12-bit resolution, the existing DEM methods can properly
compensate for the non-linearity, such as data weighted averaging (DWA) [1] and segmented DEM
[2]. In terms of incremental modulators, however, the already published error correction methods
are not suitable when more resolution 18-bit resolution is required. In this chapter, a Smart-DEM
algorithm appropriate for high resolution incremental modulators is presented. Theoretical analysis
and simulation results of design examples demonstrate the effectiveness of the proposed method.

3.1 Effect of Mismatch and DEM Methods

In this section, we start with the study of kT/C noise limitation for both Σ∆ and incremental
modulators, which determines the minimum capacitance of input sampling capacitor of ADCs. With
this value, the matching accuracy of unity elements is estimated and consequently, the effect on the
performance of modulators due to the mismatch in multi-bit DAC is investigated. Existing DEM
methods are introduced in the last part of this section.
Multi-Bit A/D Converters with High Resolution and Low-Power. 27
By Yao Liu
28 DYNAMIC CONVERSION OF MISMATCH

3.1.1 kT/C Noise Limitation

It is known that for DT modulators, the kT/C noise is uniformly distributed in the first Nyquist zone
on the spectrum. With regard to Σ∆Ms, the total power contributed by kT/C noise is significantly
reduced due to a relatively large OSR, since the out-of-band noise does not need to be included. With
mathematical calculation, the minimum input sampling capacitor of Σ∆Ms can be estimated as
8kT EN OB×6.02+1.76
CS = 10 10 (3.1)
VF2S × OSR
where ENOB is the expected resolution of the modulator and VF S is the full scale voltage. The premise
of (3.1) is that the quantization error of the modulator is not included in the total power of noise. For
12-bit Σ∆Ms with VF S =1.8 V and OSR=16, the estimated CS is 16 fF. In such a case, the constraint
of input sampling capacitor mainly comes from the matching accuracy of unity elements in multi-bit
DAC.
Incremental modulators are always used to achieve more than 16-bit resolution. This results in the
thermal noise, or kT /C noise in a discrete-time (DT) system, becomes dominant contributor among
quantization noise and other noise sources in circuits or systems. In this case, CS should be large
enough to suppress kT /C noise. For instance, considering a single-ended implementation of the
second-order incremental modulator as depicted in Fig. 2.17. In each clock cycle, the noise injected
on the input sampling capacitor is 2kT /CS . After N clock periods, the total noise power accumulated
at Vres node can be described as follows
N −2
2 2kT X 2
Vn,tot = i (3.2)
CS i=1
Therefore, the input referred noise of the second-order modulator can be derived as
2
2
Vn,tot
Vn,in = 2 (3.3)
G2ord
where G2ord is the gain for the input signal and can be represented by (N − 1)(N − 2)/2. In order to
achieve R2ord resolution, Vn,in should be less than half VLSB , which gives rise to
PN −2
8kT i=1 i2 VF S
CS > ; VLSB = R (3.4)
G22ord VLSB
2 2 2ord

Following (3.4), R2ord = 18, N = 256, VF S = 3.3V, qb = 3 and corresponding VLSB = 12.6 µV
are chosen as an example. The calculated minimum CS is 1.1 pF. Using this value, we can estimate
the matching accuracy between unity elements in the 3-bit DAC. For the modern 0.18 µm CMOS
technology, the typical 3σ matching accuracy of MIM capacitors is below 1.5% and the capacitance
density is 2f F/um2 . However, to keep some margin when considering the parasitic capacitance in
real circuit implementation, a relatively larger 3σ matching accuracy is chosen which is 2.0%. The
size of unity capacitor in 3-bit DAC is 8.3µm × 8.3µm and thus, the corresponding 3σ matching
accuracy is 0.25%.

3.1.2 Mismatch Effect for Σ∆ ADCs

To study the effect of mismatch for Σ∆Ms, the second-order feed-forward architecture is utilized as
illustrated in Fig. 3.1. This scheme is similar to the one plotted in Fig. 2.17, however, without the reset
 EFFECT OF MISMATCH AND DEM METHODS 29

ɛq
Vin Z -1
Z -1 Dout
1  -1
1 -1 
1̶Z 1̶Z
5-bit
1

DAC

Figure 3.1 Second-order 5-bit feed-forward Σ∆ ADC block diagram.

0
-1 0 S N D R = 6 0 .5 d B
-2 0 E N O B = 9 .7 5 b its
-3 0
-4 0
-5 0
-6 0
P S D (d B )

-7 0
-8 0
-9 0
- 1 0 0
- 1 1 0
- 1 2 0
- 1 3 0
- 1 4 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 3.2 PSD (8096-point FFT) with σ=1.0% mismatch for 32 unity elements of DAC. The input signal is a
sinusoid waveform at normalized frequency 8.54 · 10−4 whose amplitude is -3 dBF S . The OSR is 16.

signal of integrators. The quantizer is 5-bit and thus 32 unity elements are contained in the DAC. The
mismatch between unity elements are modelled as a random variable which obeys normal distribution
with zero mean and variance equal to σ.
Ideally when there is no mismatch between the unity elements, the achieved SNDR with behavioural
simulation is 76.4 dB (ENOB = 12.39-bit). Fig. 3.2 shows the PSD of Dout using 8096 points FFT
with σ = 1.0% mismatch. The achieved SNDR is 60.5 dB which is equal to 9.75-bit resolution. The
resolution loss compared with the ideal case is 2.64-bit. In order to reduce the performance degradation,
the mismatch between unity elements is reduced to σ = 0.1%. The same behavioural simulation is
performed and the the result is illustrated in Fig. 3.3. The attained SNDR is 74.9 dB (12.15-bit) and
the resolution loss compared with that in ideal case is 1.5 dB (0.24-bit).
30 DYNAMIC CONVERSION OF MISMATCH

0
-1 0 S N D R = 7 4 .9 d B
-2 0 E N O B = 1 2 .1 5 b its
-3 0
-4 0
-5 0
-6 0
P S D (d B )

-7 0
-8 0
-9 0
- 1 0 0
- 1 1 0
- 1 2 0
- 1 3 0
- 1 4 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 3.3 PSD (8096-point FFT) with σ=0.1% mismatch for 32 unity elements of DAC. The input signal is a
sinusoid waveform at normalized frequency 8.54 · 10−4 whose amplitude is -3 dBF S . The OSR is 16.

3.1.3 Mismatch Effect for Incremental Modulators

Vin Z-1 Z-1 Vres

 -1 -1
1̶Z 1̶Z

 Vmis(k)
Vout(k)

Figure 3.4 Equivalent model of second-order incremental ADC with non-ideal multi-bit DAC.

To investigate the mismatch effect of incremental modulators, the second-order architec-ture is

adopted as illustrated in Fig. 2.17. Previously, we demonstrated that quantization error can be estimated
with (2.34). However, it is the ideal case. In reality, the mismatch between unity elements in multi-bit
DAC results in a larger INL and DNL than those obtained under the ideal situation. Here, we utilize an
equivalent model of the second-order structure with non-ideal multi-bit DAC, which is shown in Fig.
3.4. Suppose the resolution of DAC is bq -bit, the number of unity elements is therefore Nu = 2qb . As
illustrated in Fig. 3.4, the DAC provides 2 feedback signals in the kth clock period: one is Vout (k),
the ideal analog version of Dout (k); the other one is Vmis (k), which is the total error injected due to
mismatch and can be described as
Nu
X
Vmis (k) = 2Vref m i Dout (i, k) (3.5)
i=1
 EFFECT OF MISMATCH AND DEM METHODS 31

where i (i = 1, 2, ..., Nu ) are the values of mismatch (in percentage) and Dout (i, k)(i = 1, 2, ..., Nu )
is the digital code of ith-bit of Dout (k). Since incremental ADCs use several integrators along the
signal path, an error injected at the beginning of a conversion generally has a larger accumulation
than the error injected near the end of the conversion. Thus, the weights W (k)(k = 1, 2, ..., N ) are
introduced to indicate the amplification of an error injected at kth clock period. Consequently, the total
error appears at Vres at the end of N th clock period is
N
X
Vmis = Vmis (k) × W (k) (3.6)
k=1

Combining (3.5) and (3.6), we have

Nu
X
Vmis = Vref m i W i (3.7)
i=1

where Wi (i = 1, 2, ..., Nu ) are the total accumulated weight corresponding to i (i = 1, 2, ..., Nu ) after
a full conversion cycle (N clock periods). Using (3.7), rewrite (2.34) and Vin can be expressed as
PN −1 Pi−1
i=1 j=1 Dout (i)Vref m Dout (N )Vref m
Vin = +
M M (3.8)
Vdres + V mis
+
M
Consequently, the resolution of second-order incremental converter can be estimated

u N
M Vref X
R2ord = log2 ; tot = i Wi (3.9)
res + Vref m tot }
max{Vd i=1

As seen in (3.9), the achievable resolution of the second-order incremental ADC illustrated in Fig. 2.17
depends on the tot term. In Section 3.3, behavioural simulations will show how this term affects the
modulator’s performance, when different digital error correction methods are utilized.

3.1.4 Dynamic-Element-Matching Techniques

The dynamic-element-matching technique is well known with the function to convert mismatch
associated with multi-bit DAC into shaped noise. As a result, the power of the noise that remains
in the signal band is low. The first DEM technique was reported in [3]. By selecting the DAC elements
randomly, the SFDR is improved. However, the noise introduced by the mismatch of elements is
white and spreads over the entire spectrum. The data weighted averaging (DWA) algorithm was later
presented in [1]. The main operation principle of DWA is to use the elements of DAC with a cyclical
order. In this case, the noise associated with the mismatch is high-pass shaped by a first-order NTF.
Unfortunately, the DWA suffers from in-band tones. Some modified DWA techniques and other DEM
technique such as tree structured DEMs are proposed afterwards [2], [4]-[7]. In summary, most existing
DEM techniques reduce the spurious tones by spreading the power over the spectrum, however, at the
cost of increased noise floor.
For Σ∆Ms aiming for 12-bit or more resolution, the aforementioned methods such as DWA [1] and
segmented DEM [2] are good solutions. However, since incremental modulators belong to Nyquist-rate
data converter, the requirement of achieving good resolution is to provide accurate sample-to-sample
32 DYNAMIC CONVERSION OF MISMATCH

conversion, rather than to obtain good noise shaping. For incremental modulators, the weight of signal
injected at the beginning of the conversion is larger than the weight of that injected close to the end of
the conversion. Thus, conventional DWA algorithm can not properly compensate for the error caused
by mismatch. In the next section, a Smart-DEM algorithm for high-order multi-bit incremental ADCs
is proposed, which is able to achieve a near-ideal compensation even for a large mismatch. Behavioural
simulation results and comparison between conventional DEMs and Smart-DEM are given in Section
3.3.

3.2 Smart-DEM Algorithm

In this section, the working principles of Smart-DEM algorithm are described. Generally, for a qb -
bit DAC without extra levels, the summation of mismatch of all the unity elements is zero (otherwise
it can be regarded as a gain factor), which means
Nu
X
i = 0; Nu = 2qb (3.10)
i=1

According to (3.7) and (3.10), it can be noticed that if the weights of the mismatch were well balanced,
the total error tot could be reduced. The ideal case is that, if all the weights Wi are equal, tot
becomes 0. However, as discussed before, this is not an easy task with conventional DEM techniques.
The weight of error depends on the time when the signal is injected. For second-order structure, the
weight of error is a linear function with respect to the time of signal injection. If the modulator is
third-order scheme, the weight becomes quadratic function versus time so forth.
In order to balance the weights of error, a Smart-DEM algorithm is proposed. The key point of this
algorithm is that, during N clock periods, Smart-DEM algorithm balances the Wi (i = 1, 2, ..., Nu ),
thus minimizing tot (i = 1, 2, ..., Nu ). Before describing the operation principles of Smart-DEM
algorithm, we first introduce the estimation of 2 important parameters — Vmis (k) and W (k).

3.2.1 Multi-Bit DAC and Mismatch

For the sake of simplicity, we begin the discussion with second-order incremental scheme illustrated
in Fig. 2.17. Behavioural simulation results show that with ideal 3-bit quantization, the swing of DAC
is 1.25Vref . It means that 2-extra levels needs to be added, thus, the number of unity elements in DAC
is Nu = 10. According to (2.24), the number of clock periods N is chosen to be 256, so as to obtain
18-bit resolution.
Fig. 3.5 plots the conventional single-ended implementation of the first integrator and 3-bit DAC
with switched-capacitor circuits. Notice the DAC contains 10 capacitors with equal nominal value
Cu and Dout [10 : 1] is the digital output of the modulator in a thermometrical fashion. The
mismatch of unity capacitors in DAC can be represented with i (i = 1, 2, ..., 10). Tab. 3.1 shows
the relationship between Dout [10 : 1] and the corresponding error cause by the mismatch of 10 unity
capacitors. As seen in Tab. 3.1, the first column shows the 11 possible thermometrical codes of
Dout [10 : 1]. The second column illustrates the related error caused by mismatch corresponding to
a certain input code. It can be noticed that i has both positive and negative signs, and it is not good
from circuit implementation point of view. By using (3.10), the negative signs can be transformed to
the complementary counterparts and this is shown in the last column.
For example, when the second-order modulator generates a digital output Dout [10 : 1] =
0000000011, it means that the control signals for 8 capacitors are negative and for the other 2 capacitors
 SMART-DEM ALGORITHM 33

Φ1 8Cu Φ2 8Cu
Vin
Φ2 Φ1

DAC VX
Φ1Dout[i]
Vref
Φ1Dout[i] Cu Φ2 Op-Amp
-Vref
Φ2 Φ1
X10

Figure 3.5 Conventional implementation of the first integrator and 3-bit DAC (11 levels).

Table 3.1 The relationship between Dout [10 : 1] and Vmis (k) for conventional DAC.

Dout [10 : 1] Vmis (k) Vmis (k) with (3.10)

P10
1111111111 Vref m i=1 i 0
Vref m ( 9i=1 i − 10 )
P P9
0111111111 2Vref m i
P8i=1
Vref m ( i=1 i − 10
P8 P
0011111111 i ) 2Vref m i
Pi=9 P7i=1
Vref m ( 7i=1 i − 10
P
0001111111 i=8 i )
 2Vref m i
P6 P10 P6i=1
0000111111 Vref m ( i=1 i − i=7 i ) 2Vref m i=1 i
Vref m ( 5i=1 i − 10 2Vref m 5i=1 i
P P P
0000011111 i=6 i )
P4 P10
2Vref m 4i=1 i
P
0000001111 Vref m ( i=1 i − i=5 i )
Vref m ( 3i=1 i − 10
P P P3
0000000111 i ) 2Vref m i=1 i
Pi=4
Vref m ( 2i=1 i − 10 2Vref m 2i=1 i
P P
0000000011 i)
P10 i=3
0000000001 Vref m (1 − i=2 i ) 2Vref m 1
-Vref m 10
P
0000000000 i=1 i 0

are positive.
P2 For a conventional DAC plotted in Fig. 3.5, P10 the total positive voltage injected is
vref m i=1 (1 + i ) and the negative voltage is −vref m i=3 (1 + i ). With (3.10), the negative
voltage can be converted to positive equivalent, which is shown in the third column in Tab. 3.1. P2Thus,
the total positive voltage injected with Dout [10 : 1] = 0000000011 is −(3/4)Vref + 2Vref m i=1 i .
Fig. 3.6 illustrates the schematic of an integrator with a bipolar DAC. The benefit of a bipolar DAC
is that it can achieve the same function as a conventional DAC does, with only half number of unity
elements. The working principle of the bipolar DAC is as follows: the digital input Dout [10 : 1] is
encoded to generate control signals A[5 : 1] and B[5 : 1], as illustrated in Tab. 3.2. Since the left side
of the capacitor Cu is connected to positive or negative references either during φ1 or φ2 , the digital
controls A[5 : 1] and B[5 : 1] can give rise to positive, negative or null injection. By employing (3.10),
the negative signs can be removed with complementary code and it is shown in the last column in Tab.
3.2.
34 DYNAMIC CONVERSION OF MISMATCH

Φ1 8Cu Φ2
Vin 8Cu
Φ2 Φ1

VX
Φ1A[i] X5
Vref
Φ1A[i] Op-Amp
-Vref Cu Φ2
Φ2B[i]
Vref Φ1
Φ2B[i]
-Vref

Bipolar DAC

Figure 3.6 First integrator and 11-level bipolar DAC implementation.

Table 3.2 The relationship between Dout [10 : 1] and Vmis (k) for bipolar DAC.

Dout [10 : 1] A[5 : 1] B[5 : 1] Vmis (k) Vmis (k) with (3.10)
P5
1111111111 11111 00000 2Vref m i 0
Pi=1
4 P4
0111111111 11111 10000 2Vref m i 2Vref m i
P3i=1 P3i=1
0011111111 11111 11000 2Vref m i 2Vref m i
P2i=1 P2i=1
0001111111 11111 11100 2Vref m i=1 i 2Vref m i=1 i
0000111111 11111 11110 2Vref m 1 2Vref m 1
0000011111 11111 11111 0 0
P5
0000001111 00000 00001 −2Vref m 1 2Vref m i
P5i=2
−2Vref m 2i=1 i
P
0000000111 00000 00011 2Vref m i
P3 P5i=3
0000000011 00000 00111 −2Vref m i=1 i 2Vref m i=4 i
−2Vref m 4i=1 i
P
0000000001 00000 01111 2Vref m 5
−2Vref m 5i=1 i
P
0000000000 00000 11111 0

3.2.2 The Weight of Error for Multi-Bit DAC

In order to compensate for the error generated from multi-bit DAC, the number of its accumulation
for a certain incremental modulator during N clock cycles should be calculated. For second-order
incremental converter, if the error from DAC enters at kth (1 ≤ k ≤ N ) period after the reset, the
error is stored though the first integrator with one clock period delay, then it is accumulated as a linear
function on the second integrator. Thus, the weight of the error caused by mismatch in kth clock period
is

W2ord (k) = N − k − 1 (3.11)

 SMART-DEM ALGORITHM 35

Regarding third-order incremental modulators (3 integrators with unit time delay), if an error from
DAC enters at kth(1 ≤ k ≤ N ) clock period after the reset, the error is stored at the output of the first
integrator. The second integrator accumulates the error linearly. After that, a quadratic accumulation
of this error is achieved with the third integrator. In this case, the weights can be estimated as

(N − k − 1)(N − k − 2)
W3ord (k) = (3.12)
2!
In general, for Lth-order incremental converter described in Fig. 2.15, the weights can be expresse as

(N − k − 1)(N − k − 2)...(N − L)
WLord (k) = (3.13)
L!

3.2.3 The Principle of Smart-DEM Algorithm

The idea of Smart-DEM algorithm is to dynamically balance the weights of error along the data
conversion of N clock periods for one sample. The detailed operation is described below:
I Step 1: before starting a new conversion cycle, reset the total weights of all the elements Wi (i =
1, 2, ..., Nu ) to zero.
I Step 2: in each clock cycle, select the unity elements with the minimum weight. If it is the last
clock period, jump to Step 4.
I Step 3: calculate the weight of current clock period W (k) (k = 1, 2, ..., N ) and update the
weights of the selected elements, then go back to Step 2.
I Step 4: finish the conversion cycle.

RESET k=1 k=1 k=2 k=2 k=2 End of k=256

C10 0 C10 0 C6 254 C6 254 C3 507 C3 253 C7 1
C9 0 C9 0 C5 254 C5 254 C2 507 C2 253 C6 1
C8 0 C8 0 C4 254 C4 254 C1 507 C1 253 C5 1
C7 0 C7 0 C3 254 C3 507 C6 254 C6 1 C4 1
C6 0 C6 254 C2 254 C2 507 C5 254 C5 1 C1 1
C5 0 C5 254 C1 254 C1 507 C4 254 C4 1 C10 0
C4 0 C4 254 C10 0 C10 253 C10 253 C10 0 C9 0
C3 0 C3 254 C9 0 C9 253 C9 253 C9 0 C8 0
C2 0 C2 254 C8 0 C8 253 C8 253 C8 0 C3 0
C1 0 C1 254 C7 0 C7 253 C7 253 C7 0 C2 0

Dout[10:1]=0000111111 Dout[10:1]=0001111111
W(1)=254 W(2)=253

Figure 3.7 The status of the weights in Smart-DEM with Vin = 0.305Vref .

The following is an example to explain how the Smart-DEM algorithm works. Fig. 3.7 shows
accumulated weights of unity elements with respect to clock period. Before the data conversion starts,
the weight of each element is reset to 0. In first clock period, Dout [10 : 1] = 0000111111 and the
decimal value is 6 (the decimal value of Dout [10 : 1] is from 0 to 10, with a common mode value 5).
P6
By using Tab. 3.1, we know that the total error caused by mismatch is 2Vref m i=1 i . According
to the Smart-DEM algorithm, 6 unity elements with the minimum weights should be chosen and the
corresponding weight needs to be updated. Therefore, unity elements C1-C6 are selected. Regarding
to (3.11), the associated weight is calculated as 254. This value is added to the existing weight of
C1-C6. After that, the weight array is sorted and the larger values are moved at the top of the stack.
36 DYNAMIC CONVERSION OF MISMATCH

In second clock period, Vin [10 : 1] = 0001111111 and decimal number is 7. Similarly, 7 elements
with the minimum weight are selected which are C4-C6 and C7-C10. However, the corresponding
weight of this clock period changes to 253. This value is again added to the current weights of these
elements. After sorting algorithm, the minimum weight in the array is subtracted from all weights in
case of hardware overflow. This is because the word length of weights is limited in real circuit. Finally,
after 256 clock periods, the Wi (i = 1, 2, ..., 10) is no more than 1 and the total effect of the mismatch
is negligible.

3.3 Design Examples and Simulation Results

In this section, high-order incremental architectures utilizing Smart-DEM algorithm are discussed.
Design guidelines from circuit implementation point of view are given in order to achieve low power
design and maintain stability of the structure. Two design examples for second-order and third-
order incremental converters are detailed explained and behavioural simulation results demonstrate
the effectiveness of Smart-DEM algorithm.

3.3.1 Design Consideration of Employing Smart-DEM Algorithm

In order to design high-resolution low power incremental converter using Smart-DEM algorithm,
design guidelines are given as below
1. The output swing of integrators should be minimized to improve the linearity of the op-amps, as
well as to reduce the number of comparators in the quantizer.
2. The coefficients along the accumulation path should not degrade the overall performance of the
modulator.
3. The input referred kT/C noise should be suppressed to be comparable with quantization
counterpart. The input sampling capacitance should be affordable, otherwise, increase the number
of clock periods N to lower kT/C noise.
4. There should be only one feedback path in which a DEM algorithm (e.g. Smart-DEM) can be
effectively used.
The guideline 1) considers how to achieve low-power dissipation of the analog circuit. Item 2) results
in easier implementation of the analog coefficients and avoids performance degradation. The guideline
3) explains the limitation due to kT/C noise and the corresponding noise reduction methods. The
purpose of last item is to reduce the complexity of digital block, which is used to compensated for
the mismatch of the multi-bit DAC. By adopting these guidelines, second-order and third-order design
examples are discussed in the following subsections.

3.3.2 Second-Order Incremental Modulator Example

As previously mentioned, the second-order architecture illustrated in Fig. 2.17 is the first design
example, which is plotted again in Fig. 3.8. It can be noticed that Dout is encoded in a Smart-DEM
block and the generated control signals are then used to select proper unity elements in 3-bit DAC. This
structure was previously used in both Σ∆ converter and incremental modulators [8][9]. The advantage
of this structure is that due to the feed-forward paths, the swing of both op-amps are reduced. However,
the incremental converter presented in [9] employs 2-level DAC and an extended stage to reduce the
 DESIGN EXAMPLES AND SIMULATION RESULTS 37

S1
1

S2
2
RESET RESET

Vin Z-1 Z-1 Vres Dout

1  1 
1 ̶ Z-1 1 ̶ Z-1
3-bit
1

Vout SMART
DAC
DEM

11-level

Figure 3.8 Second-order 3-bit feed-forward incremental architecture with Smart-DEM block.

residue voltage Vres . Here, this second-order architecture is used to explain the design of multi-bit
incremental converter assisted by Smart-DEM algorithm.
In Section 3.2, we mentioned that for 3-bit quantization, the swing of DAC is 1.25Vref and thus
10 unity capacitors are used. Moreover, the 3-bit quantizer demands for 10 comparators instead of 8.
With N = 256, the number of levels of digital output is 259080, corresponding to 17.98-bit resolution.
By extensive behavioural level simulations, the swing of the first op-amp is below 0.25Vref . For the
second op-amp, the swing is within 0.125Vref . In this case, the power consumption of op-amps can
be significantly reduced. Regarding to the Smart-DEM realization, the number of standard cells after
synthesis is below 1.5k with Cu = 10 and N = 256. This number can be further reduced when a
bipolar DAC is utilized. With modern CMOS technologies, the power consumption of Smart-DEM
block is insignificant, especially when the power supply of digital block is low.
To demonstrate the effectiveness of Smart-DEM algorithm, 2 groups of simulations are performed.
Design parameters N = 256, bq = 3 and VF S = 3.3 are selected. In the first group, the mismatch
obeys a normal distribution with µ = 0 and σ = 0.08%. Fig. 3.9 illustrates the performance
comparison of the same second-order scheme in three different cases: mismatch of unity elements
not compensated for, assisted with conventional DWA method, and compensated for with the Smart-
DEM algorithm. The input is a constant voltage ranging from -Vref to Vref . As seen in Fig. 3.9,
the maximum INL with no compensation is about 101 LSB. When using DWA, the maximum INL
is reduced to 0.9 LSB. The Smart-DEM is able to keep the error within 0.5 LSB for entire range.
In this case, although DWA can guarantee a good performance if half-bit resolution loss is allowed,
Smart-DEM is able to fully compensate for the mismatch and achieved near-ideal performance.
Moreover, it is useful to compare the performance of different DEMs when a larger mismatch is
given. Fig. 3.10 illustrate the performance comparison when the mismatch obeys µ = 0 and σ = 0.8%.
The maximum INL without DEM algorithm is 1019.6 LSB and for DWA is 4.3 LSB. However, with
the compensation of Smart-DEM algorithm, the maximum INL is still limited within 0.5 LSB over the
entire input range.
Fig. 3.11 shows the weight accumulation of 10 unity elements of 3-bit DAC of the second-order
architecture illustrated in Fig. 3.8. Since 10 curves overlap with each other and the difference is
difficult to observe, only the last 50 clock periods are plotted here. The input signal is 0.123Vref .
At the end of the conversion, the maximum weight is 17786 while the minimum one is 17784. The
38 DYNAMIC CONVERSION OF MISMATCH

N o D E M
2 5
0
-2 5
-5 0
-7 5
-1 0 0
-1 2 5
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I N L ( L S B @ 1 7 .9 8 - b it)

D W A
0 .2 5
0 .0 0
- 0 .2 5
- 0 .5 0
- 0 .7 5
- 1 .0 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
S m a rt-D E M
0 .5 0
0 .2 5
0 .0 0
-0 .2 5
-0 .5 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I n p u t V o lt a g e ( V re f
)

Figure 3.9 Resolution comparison for second-order incremental converter without DEM (top), with DWA
(middle) and with Smart-DEM (bottom). The mismatch of unity elements obeys normal distribution with µ = 0
and σ = 0.08%.

weights for all the elements converge to the same level with a maximum difference of 2, which results
in a negligible residual error.

3.3.3 Third-Order Incremental Modulator Example

The second design example is a third-order incremental converter illustrated in Fig. 3.12. In order
to compare the conversion efficiency between the third-order structure and second-order scheme, the
target resolution is also selected to be 18-bit. This structure is similarly to the architectures published
in [10][11]. None the less, several features are included to convert it into a high-resolution multi-bit
incremental modulator.
Firstly, the use of multi-bit quantizer and DAC benefits the modulator extra bits resolution and
reduces the swing of op-amps. The second point is that several feed-forward paths are added to
maintain the stability of structure while the coefficients along the integration path do not degrade
the overall performance. In order to lower the swing of the first op-amp, coefficient 0.5 and 2 are
introduced at the input of first and second integrators. Finally, a quantized version of Vin is added to
Dout , which means that the amplitude of the real input signal is reduced to less than half quantization
interval of the quantizer. However, this is at the cost of increased swing of multi-bit DAC. According
to (2.28), in order to achieve 18-bit resolution, design parameters N = 61 and qb = 3 and VF S = 3.3V
are selected. The input sampling capacitance is calculated to be 6.37 pF (Appendix A) and the
corresponding matching accuracy is around 3σ = 0.1%. The scheme is simulated on behavioural
level with a full scale 273760, which is equivalent to 18.06-bit resolution. By sweeping the amplitude
of input signal, the swing of all three op-amps is below 0.25Vref . Nevertheless, the output of the DAC
is 75% more than the full scale, thus the DAC needs 6 extra levels and the total levels of DAC is 15.
 DESIGN EXAMPLES AND SIMULATION RESULTS 39

N o D E M
0
-2 0 0
-4 0 0
-6 0 0
-8 0 0
-1 0 0 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I N L ( L S B @ 1 7 .9 8 - b it)

D W A
-2
-3
-4
-5
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
S m a rt-D E M
0 .5 0
0 .2 5
0 .0 0
-0 .2 5
-0 .5 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
In p u t V o lta g e ( V re f
)

Figure 3.10 Resolution comparison for second-order incremental converter without DEM (top), with DWA
(middle) and with Smart-DEM (bottom). The mismatch of unity elements obeys normal distribution with µ = 0
and σ = 0.8%.

1 7 8 0 0

1 7 7 0 0
A c c u m u la te d W e ig h t

1 7 6 0 0 W 1
W 2
1 7 5 0 0 W 3
W 4
W 5
1 7 4 0 0
W 6
W 7
1 7 3 0 0 W 8
W 9
1 7 2 0 0 W 1 0

1 7 1 0 0
2 1 0 2 1 5 2 2 0 2 2 5 2 3 0 2 3 5 2 4 0 2 4 5 2 5 0 2 5 5
C lo c k P e rio d

Figure 3.11 Accumulated weights of mismatch of 10 unity elements for second-order 3-bit feed-forward
architecture with constant Vin = 0.123Vref .
40 DYNAMIC CONVERSION OF MISMATCH

S1
3

S2
3
RESET RESET RESET

Vin Z-1
Z -1
Z-1 Vres Dout
 0.5 2 
1 ̶ Z-1 1 ̶ Z-1 1 ̶ Z-1
3-bit

Vout SMART
DAC 
DEM

15-level

3-bit

Figure 3.12 Third-order 3-bit feed-forward incremental architecture with Smart-DEM block.

N o D E M

1 2 0
1 0 0
8 0
6 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I N L ( L S B @ 1 8 .0 6 - b it)

D W A
4 .5
4 .0
3 .5
3 .0
2 .5
2 .0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
S m a rt-D E M
0 .5 0
0 .2 5
0 .0 0
-0 .2 5
-0 .5 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
In p u t V o lta g e ( V re f
)

Figure 3.13 Resolution comparison for third-order incremental converter without DEM (top), with DWA
(middle) and with Smart-DEM (bottom). The mismatch of unity elements obeys normal distribution with µ = 0
and σ = 0.035%.

The number of unity elements is 14. If the positive-negative DAC is used, the number of unity elements
is can be reduced to 7, resulting in a compact Smart-DEM algorithm implementation.
To demonstrate the Smart-DEM algorithm for third-order incremental architecture, 2 groups of
simulations are also performed. Fig. 3.13 shows the performance comparison of the third-order scheme
 DESIGN EXAMPLES AND SIMULATION RESULTS 41

N o D E M
1 4 0 0
1 2 0 0
1 0 0 0
8 0 0
6 0 0
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I N L ( L S B @ 1 8 .0 6 - b it)

D W A
4 0
3 5
3 0
2 5
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
S m a rt-D E M
0 .6
0 .4
0 .2
0 .0
-0 .2
-0 .4
-0 .6
-1 .0 -0 .8 -0 .6 -0 .4 -0 .2 0 .0 0 .2 0 .4 0 .6 0 .8 1 .0
I n p u t V o lt a g e ( V re f
)

Figure 3.14 Resolution comparison for third-order incremental converter without DEM (top), with DWA
(middle) and with Smart-DEM (bottom). The mismatch of unity elements obeys normal distribution with µ = 0
and σ = 0.35%.

in three different cases. The mismatch for the 14 unity elements obeys normal distribution with zero
mean value and σ = 0.035%. The input is a constant voltage ranging from -Vref to Vref . The
maximum INL without compensation is about 127.8 LSB. When using DWA method, the error is not
linear with a maximum of 3.9 LSB. The Smart-DEM is able to keep the error within 0.5 LSB for entire
range.
For the second group simulation, the mismatch for the 14 unity elements obeys normal distribution
with zero mean value and σ = 0.35%. The input is a constant voltage ranging from -Vref to Vref .
The maximum INL without compensation, however, is 1319.8 LSB. With DWA method, the maximum
error is 38.4 LSB. The Smart-DEM is able to keep the error within 0.53 LSB for entire range. This
value is slightly larger than the expected 0.5 LSB because of the imbalance of the weights at the end
of N th clock period.
42 DYNAMIC CONVERSION OF MISMATCH

REFERENCES

1. R. T. Baird and T. S. Fiez, “Linearity enhancement of multibit A/D and D/A converters using data weighted
averaging”, IEEE Trans. Circuits. Syst. II, vol. 42, pp. 753-762, Dec. 1995.
2. I. Galton, “Spectral shaping of circuit errors in digital-to-Analog converters”, IEEE Trans. Circuits. Syst. II,
vol. 44, no. 10, pp. 808-817, Oct. 1997.
3. L. R. Carley, “A noise-shaping coder topology for 15+ bit converters”, IEEE J. Solid-State Circuits, vol. 28,
no. 2, pp. 267-273, Apr. 1989.
4. I. Fujimori et al., “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation
at 8×oversampling ratio”, IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820-1828, Dec. 2000.
5. M. R. Miller and C. S. Petrie, “A multibit sigma-delta ADC for multimode receivers”, IEEE J. Solid-State
Circuits, vol. 38, no. 3, pp. 475-482, Mar. 2003.
6. T.-H. Kuo, K.-D. Chen, and H.-R. Yeng, “A wideband CMOS sigma delta modulator with incremental data
weighted averaging”, IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 11-17, Jan. 2002.
7. J. Welz, I. Galton, and E. Fogleman, “Simplified logic for first-order and second-order mismatch-shaping
digital-to-analog converters”, IEEE Trans. Circuits. Syst. II, vol. 48, no. 11, pp. 1014-1027, Nov. 2001.
8. KiYoung Nam et al.,“A Low-Voltage Low-Power Sigma-Delta Modulator for Broadband Analog-to-Digital
Conversion”, IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855-1864, Sept. 2005.
9. Ali Agah et al., “A high-resolution low-power incremental Σ∆ ADC with extended range for biosensor
arrays”, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1099-1110, Jun. 2010.
10. V. Quiquempoix et al., “A low-power 22-bit incremental ADC”, IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1562-1571, May 2005.
11. J. Markus, J. Silva, and G. C. Temes, “Theory and applications of incremental ∆Σ converters”, IEEE Trans.
Circuits. Syst. I, vol. 51, no. 4, pp. 678-690, Apr. 2004.
CHAPTER 4

A 17-BIT INCREMENTAL A/D CONVERTER:

DESIGN CONSIDERATIONS

This chapter and Chapter 5 describe the design and implementation of a 17-bit incremental A/D
converter. The focus of this chapter is the design considerations to achieve high resolution incremental
ADCs. Aiming at target specifications, the fundamental design parameters, namely, the order of the
incremental structure, the resolution of quantizer and the number of clock periods per sample are
discussed. The purpose of the second part is to search for optimal architectures based on multi-bit
quantization. Special architecture’s requirements need to be take into consideration in order to utilize
the Smart-DEM algorithm as well as to keep the modulator compact. The third part shows that by
introducing feedback paths in a first-order incremental scheme, the conversion efficiency can increase
exponentially. This structure turns out to be the well-known algorithmic architecture. Study manifests
that with proper calibration techniques, the algorithmic architecture has the potential to achieve more
than 14-bit resolution.

4.1 General Considerations for Incremental Schemes

As already mentioned in Chapter 2, incremental ADCs are always used in instrumentation,

measurement and sensor applications, which requires high resolution, good linearity, low offset and
low-power. The starting point of this research of incremental ADCs is to have an overview of the
specifications, which are listed as follows:
I Resolution: 18-bit
Multi-Bit A/D Converters with High Resolution and Low-Power. 43
By Yao Liu
44 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

I Bandwidth: 5kHz
I Clock Periods: ≤300
I Power Consumption: ≤0.5mW
To accomplish the goal, design strategies on both architecture level and circuit level should be
investigated. Considerations on architecture level are with higher priority with respect to circuit level.
Meanwhile, design strategies on architecture level should be further studied to understand if they are
feasible from circuit implementation point of view.
With regard to incremental converters, the fundamental design parameters are the order of the
structure L, resolution of the quantizer qb , number of clock periods N, as illustrated in (2.36). When L
and qb are chosen, the corresponding N can be estimated. For example, to obtain 16-bit resolution with
L = 2 and qb = 0 (2-level comparator), the required clock period is 364. However, the premise of this
calculation is that the power of kT/C noise introduced by the input stage of the modulator is less than
the power of quantization noise. When the kT/C noise dominants, the maximum achievable resolution
does not obey (2.36). Thus, for the design of incremental converters, L, qb and kT/C noise should be
of the most importance. Detailed discussion about these parameters is in the following subsections.

3 4
3 2
3 0
2 8
2 6
2 4
2 2
R e s o lu tio n (B it)

2 0
1 8
1 6
1 4
1 2
1 0
8 S e c o n d -O rd e r
6 T h ir d - O r d e r
4 F o u rth -O rd e r
2
0
0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0
N (C lo c k C y c le s )

Figure 4.1 Resolution versus clock periods for different order incremental structures.

4.1.1 Second-Order or Higher-Order

To the best of the author’s knowledge, the already published incremental ADCs ranges from first-
order to fourth-order, among which the second-order structure is of the most usage. The benefit
of utilizing high-order structure is the better conversion efficiency. Let us compare the conversion
efficiency between second-order, third-order and fourth-order structures by using the general form of
incremental ADC illustrated in Fig. 2.15. To simplify the situation, the stability of the loop filter is
not taken into consideration and design parameters c1 , c2 , c3 , c4 = 1 and bq = 0 are chosen. Fig. 4.1
shows the maximum achievable resolution with respect to clock period for three different cases. As
can be noticed, in order to achieve 16-bit resolution, 365, 75 and 33 clock periods are required for
second-order, third-order and fourth-order structures, respectively.
 GENERAL CONSIDERATIONS FOR INCREMENTAL SCHEMES 45

0 .6 0
0 .5 5 S e c o n d -O rd e r
0 .5 0 T h ir d - O r d e r
F o u rth -O rd e r
0 .4 5
0 .4 0
0 .3 5
V a lu e o f a 1

0 .3 0
0 .2 5
0 .2 0
0 .1 5
0 .1 0
0 .0 5
0 .0 0
0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0
N (C lo c k C y c le s )

Figure 4.2 The coefficient α1 with respect to clock periods.

Higher-order incremental architectures, however, have several drawbacks which affect the overall
performance. First of all, for incremental schemes more than second-order with comparator as
quantizer, the stability issue of the loop filter requires to use coefficients c1 , c2 , . . . , cL less than 1. For
example, in the third-order modulator described in [1], c1 = 0.5674, c2 = 0.5126, and c3 = 0.3171.
The corresponding full scale value and the resolution can be estimated by

(N − 1)(N − 2)(N − 3)
M = c1 c2 c3 (4.1)
3!
and
c1 c2 c3 (N − 1)(N − 2)(N − 3)
R3ord = log2 (4.2)
3!
with N = 128, the resolution is 14.9-bit, which is 3.4-bit less than the maximum achievable value (with
c1 , c2 , c3 = 1). Another case is the fourth-order modulator reported in [2]. Coefficients c1 , c2 , c3 and
c4 are 0.25, 0.4, 0.22, and 0.11, respectively. With N =128, the achievable resolution is 14.6-bit while
the maximum theoretical resolution is 23.3-bit. The loss of resolution in this case is, hence, around
8.7-bit.
The second limitation comes from the input referred kT/C noise. Generally, for an incremental
ADC, the input referred noise Vn,in should be within half VLSB range, which can be described by
r
2kT 1
Vn,in = α1 ; Vn,in ≤ VLSB (4.3)
C 2
where α1 is a constant coefficient determined by the incremental scheme and the number of clock
periods. Fig. 4.2 plots the value of α1 versus N for different incremental schemes with c1 , c2 , c3 , c4 =
1. As can be noticed, the attenuation of Vn,in is more effective when a larger N is used. Nevertheless,
augment of N means the conversion efficiency decreases. In other words, for a certain incremental
architecture, there is a tradeoff between the input referred kT/C noise and number of clock cycles. The
second observation is that for a fixed N, although high-order schemes benefit from high conversion
efficiency, the input referred kT/C noise is worse. As can be seen from Fig. 4.2, higher-order structure
46 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

leads to larger α1 and hence, larger Vn,in . Fortunately, with a fixed N, the values of α1 are comparable
for different order incremental architectures.
In fact, the limitation due to kT/C noise can be concluded as follows: increasing L can significantly
improve the conversion efficiency and reduce the quantization noise, but Vn,in remains the same or
even worse. When kT/C noise dominates rather than the quantization error, higher-order structures can
not improve the performance and suppression of kT/C noise should be taken into consideration. For
instance, to obtain 16-bit resolution, 365 and 75 clock periods are required for second-order and third-
order architectures. The corresponding α1 are 0.061 and 0.157. Thus, the minimum input capacitance
for third-order structure should be 6.7 times of the counterpart of second-order structure.
Thirdly, the error caused by circuit imperfections has different impact on the performance of
incremental modulators. In general, structures with larger L suffer more than modulators with lower
order. Here we use an example to show how circuit imperfections affect the performance of different
order incremental architectures. For incremental modulators, the basic building block used in the
integrator is op-amp. The circuit imperfections of an op-amp mainly come from limited DC gain, slew
rate and bandwidth. Considering an op-amp with limited DC gain, infinite slew rate and bandwidth,
behavioural-level simulations using the method proposed in [3] are performed for second-order and
third-order structures to achieve 16-bit resolution. Fig. 4.1 plots the INL with respect to the gain of
the op-amp in the first integrator (the rest op-amps are ideal). We notice that with the same DC gain
of op-amp, third-order structure entails larger INL compared with the second-order structure. When a
maximum allowable INL is 0.7 LSB, the DC gain of the first op-amp should be 30 dB and 50 dB for
second-order and third-order schemes, respectively.

2 4
2 2
S e c o n d -O rd e r
2 0 T h ir d - O r d e r
1 8
1 6
IN L (L S B @ 1 6 -b it)

1 4
1 2
1 0
8
6
4
2
0
5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5
G a in (d B )

Figure 4.3 INL versus the gain of the first op-amp.

4.1.2 Comparator or Multi-Bit Quantization

In Chapter 2, we briefly introduced the existing incremental modulators and most of them employ
comparator as quantizer. Incremental architecture based on multi-bit technique is seldom explored,
as already mentioned before. Here, we shall discuss the pros and cons of both techniques in order to
obtain optimal design strategies for the targeting specifications.
 GENERAL CONSIDERATIONS FOR INCREMENTAL SCHEMES 47

Utilizing multi-bit quantization can reduce the output swing of integrators, leading to low-power
design. While a 2-level quantizer may result in the op-amps working in the slewing mode and thus,
the power dissipation is higher compared with the former case. For example, the second-order scheme
illustrated in Fig. 2.17 is configured with 2-level or 3-bit quantization. When a constant input signal
Vin = 0.707 V is applied, the output swing of the first op-amp is 4 times of the swing when using 3-bit
quantizer, as plotted in Fig. 4.4. The situation of the swing of the second op-amp is similar and is not
shown here.

C o m p a ra to r
3 -b it q u a n tiz e r
1 .0

0 .8

0 .6
S w in g o f th e firs t o p -a m p (V )

0 .4

0 .2

0 .0

-0 .2

-0 .4

-0 .6

-0 .8

-1 .0
0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0
N (C lo c k C y c le s )

Figure 4.4 Output swing of the first op-amp utilizing 2-level or 3-bit quantization with Vin = 0.707 V.

The second advantage of using multi-bit quantizer is that the coefficients along the accumulation
path c1 , c2 , . . . , cL are larger than the counterparts of 2-level quantization scheme. The third-
order example presented in [1] with coefficients c1 = 0.5674, c2 = 0.5126, and c3 = 0.3171
demonstrates this observation. When combining multi-bit quantization with digital assisted techniques,
good stability of the loop filter and reduced amplitude of the input signal allow using coefficients
c1 , c2 , c3 = 1, giving rise to good conversion efficiency.
Thirdly, with qb -bit quantizer, the maximum achievable resolution exceeds qb -bit than the counterpart
using 2-level quantizer. This is evident according to (2.36). For example, a conventional second-order
scheme requires 375 clock periods to achieve 16-bit resolution. Whereas for a 3-bit second-order
structure, the required clock cycles is reduced to only 130.
The drawback of multi-bit quantization is the non-linearity of the multi-bit DAC. The non-linearity
is due to the mismatch between the unity elements of the DAC. In Chapter 3, effects of mismatch
and related DEM techniques are detailed studied for both incremental and Σ∆ ADCs. Regarding
to the design of incremental ADCs, the proposed Smart-DEM algorithm is able to compensate for
the mismatch, achieving a near-ideal multi-bit DAC. To summarize, incremental architectures based
on multi-bit quantization is superior to comparator based structures from both power dissipation and
conversion efficiency point of view. The non-linearity of multi-bit DAC can be properly solved by
digital assisted technique, giving rise to an optimal choice for designing incremental ADCs.
48 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

4.1.3 Design Strategies for Target Specifications

On the basis of previous considerations, optimal design parameters L = 2 ∼ 3, qb = 3 ∼ 5 are chosen
to achieve 18-bit resolution. Using a 0.18 µm CMOS technology with analog power supply 3.3 V,
combinations of different L and qb and other design parameters are listed in Tab. 4.1.

Table 4.1 Design parameters of incremental ADCs to achieve 18-bit.

Nord qb N α1 C

Second-order 3-bit 256 0.0724 1.096 pF

Second-order 4-bit 183 0.0857 1.535 pF
Second-order 5-bit 93 0.1207 3.045 pF
Third-order 3-bit 61 0.1747 6.379 pF
Third-order 4-bit 49 0.1957 8.004 pF
Third-order 5-bit 39 0.2206 10.171 pF

where N is the number of clock cycles, α1 is the coefficient of kT/C noise according to (4.3) and C
is the value of input sampling capacitance. As can be seen in Tab. 4.1, larger L and qb lead to better
conversion efficiency. For example, when L = 3 and qb = 5, the number of required clock periods is
39, which is only 15% of the needed clock periods with L = 2 and qb = 3. However, the reduction of
N worsens the noise performance, resulting in 10 times larger capacitance. Regarding to the design of
18-bit incremental ADC, the preferable choice is to use the second-order structure with qb = 3 ∼ 4,
because of the relative low C and acceptable N. Third-order structures can also be utilized, however,
the kT/C noise needs to be suppressed with a larger N so as to keep the noise level comparable with
the counterpart in the second-order structure. In this case, the good conversion efficiency of third-order
scheme is somehow sacrificed, nonetheless, the resulting architectures can still have better performance
than the second-order structures.
According to these design parameters, now let us consider the specific architecture design. For a
conventional scheme illustrated in Fig. 2.17, a foreseeable problem is the analog summation block,
which gives rise to considerable power consumption to achieve an accurate summation function. One
way to avoid such a block is to implement the summation in digital domain and it will be detailed
discuss in the next section.
Based on above analysis and design strategies in Section 3.2, guidelines for high-order, multi-bit
and low-power incremental ADCs with digital assistance can be concluded as follows
1. The structure does not use analog feedforward paths which lead to extra analog blocks.
2. The output swing of integrators should be minimized to improve the linearity of the op-amps, as
well as to reduce the number of comparators in the quantizer.
3. The coefficients along the accumulation path should not degrade the overall performance of the
modulator.
4. The input referred kT/C noise should be suppressed to be comparable with quantization error.
The value of input sampling capacitance should be affordable, otherwise, increase the number of
clock periods N to lower kT/C noise.
5. There should be only one feedback path in which a DEM algorithm (e. g. Smart-DEM) can be
effectively used.
 NON CONVENTIONAL INCREMENTAL STRUCTURES 49

The guidelines 1) and 2) consider how to achieve low-power dissipation of the analog circuit. Item
3) results in easier implementation of analog coefficients and avoids performance degradation. The
guideline 4) explains the limitation due to kT/C noise and corresponding noise reduction methods. The
purpose of last item is to reduce the complexity of digital block, which is used to compensate for the
non-linearity of multi-bit DAC. By adopting these guidelines, different second-order and third-order
schemes are discussed in the next section.

4.2 Non Conventional Incremental Structures

Following the design strategies in the last section, we shall find out the proper architectures so
as to employ the multi-bit quantization and DEM techniques. This section starts from second-order
structure and then extends to third-order scheme. With digital assisted actions in the last part, the
swing of equivalent input signal is considerably reduced, thus, leading to low-power design of the
analog circuit.
RESET RESET

Vin Z-1 Z-1 Vres Dout

 c1 -1  1/c1
1̶Z 1 ̶ Z-1

DAC1 DAC2

1 c2

Figure 4.5 Second-order incremental scheme with two feedback paths.

4.2.1 Second-Order Architectures

A second-order incremental converter is the cascade of two integrators. As it happens for time-invariant
schemes, it is necessary to control the cascade of more than one integrator for keeping constrained
the output of intermediate nodes. The request is not ensuring stability as needed in filters or Σ∆
architectures; however, since a similar action is required, the designer can take advantage of the method
used in time-invariant schemes.
Second-order Σ∆ architectures use an auxiliary injection at input of the second integrator or employ
feed-forward branches toward the quantizer. The latter solution is not optimal, because for multi-bit
schemes, it is necessary to use extra analog power for adding the feed-forward branches. The use of an
auxiliary injection, as shown in Fig. 4.5, can be used at two purposes: optimize the swing at the op-amp
outputs or improve the feedback factor of integrators. There is an additional degree of freedom on the
choice of the coefficients c1 and c2 . The real benefits are, indeed, limited. The use of c1 = 0.5 and
c2 = 0.75 reduces the maximum swing of the op-amps by 15% and, obviously, improves the feedback
factor of the second integrator, provided that the subtraction is performed with different SC circuits.
Fig. 4.6 shows an alternatively solution that avoids intermediate injection without feed-forward
paths. The use of a transversal filter and the proper choice of coefficients c1 and c2 control the signal
swing of the two integrators. The choice of the coefficients can be done with the help of the z transfer
50 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

RESET RESET

Vin 1 Z-1 Vres

 -1 -1
1̶Z 1̶Z

Vout Dout
DAC  c1

c2 Z-1

Figure 4.6 Second-order incremental scheme with one feedback path.

RESET RESET

Vin 1 Z-1 Vres

 -1
1̶Z 1 ̶ Z-1

c1

Z-1

Vout Dout
DAC  c2

Figure 4.7 Second-order incremental scheme with two quantizers.

function of the time-invariant equivalent. The study in the z-domain gives rise to a denominator in the
noise transfer function (NTF) and signal transfer function (STF), which can be expressed as
D2ord (z) = 1 + (c1 − 2)z −1 + (c2 + 1)z −2 . (4.4)
The position of poles of the time-invariant counterpart inside the unity circle verifies stability.
Moreover, their placement can bring about possible reduction of the op-amp swings. For example,
with c1 = 2, c2 = −1 and qb = 3, D2ord (z) is equal to 1. Simulations show that swings are 0.8Vref ,
1.3Vref and 2Vref for the outputs of first integrator, second integrator and the DAC, respectively.
However, when design parameters c1 = 1, c2 = 0.5 and qb = 3 are chosen, there are two poles
(p1 = 0.5 + 0.5j and p2 = 0.5 − 0.5j) inside the unity cycle. Thus, the stability of loop filter is
ensured. The corresponding swings for the first integrator, second integrator and the DAC are 0.2Vref ,
2.1Vref and 1.2Vref .
 NON CONVENTIONAL INCREMENTAL STRUCTURES 51

Fig. 4.7 shows a third possible architecture. It uses two quantizers at the output of integrators. The
signal fed back at the input is the addition of the two digital outputs. The use of an extra quantizer is
a limited cost because the power consumed by a comparator is much less than the one of an op-amp
with the same speed. Removing the intermediate injection improves the feedback factor of the second
integrator, thus allowing to spare power. The study of the time-invariant equivalent of this second-order
structure shows a denominator in the STF and NTF as follows

D2ord (z) = 1 + (c1 + c2 − 1)z −1 + (c1 − 1)z −2 (4.5)

F irs t O p -A m p
S e c o n d O p -A m p
1 .0
0 .9
0 .8
0 .7
0 .6
O u tp u t S w in g (V )

0 .5
0 .4
0 .3
0 .2
0 .1
0 .0
-0 .1
-0 .2
-0 .3
0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 0 2 2 5 2 5 0
N (C lo c k C y c le s )

Figure 4.8 Output swing of op-amps for second-order scheme with two quantizers with 0.707Vref input.

Simulations show that different set of design parameters c1 , c2 and bq optimize the variation of
output swing at the input of the quantizer. For instance, with c1 , c2 = 1 and bq = 3, the output swing
of two integrators is less than 0.4Vref . Fig. 4.8 shows the waveform of the outputs of op-amps under
these parameters when given 0.707V constant input (Vref = 1). Notice that the waveform of the output
of second op-amp is around the input amplitude, however, simple circuitry enables an amplitude shift
around zero. Therefore, a small swing corresponds to relaxed slewing request, low dynamic range and
reduced number of comparators in the flash.

4.2.2 Third-Order Architectures

Methods similar to the one discussed for the second-order incremental converter can be extended to
higher order. Fig. 4.9 shows a third-order incremental ADC scheme with single digital DAC and FIR
filter along quantizer loop. The digital filter uses three taps with two delays. Parameters c1 , c2 and c3
of the filter can be critical for stability. The z transfer functions of the time-invariant counterpart has a
denominator given by

D3ord (z) = 1 + (c1 − 3) + (c2 + 3)z −2 + (c3 − 1)z −3 (4.6)

52 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

RESET RESET RESET

Vin 1 1 Z-1 Vres


1 ̶ Z-1 1 ̶ Z-1 1 ̶ Z-1

c1

Vout Dout
DAC  c2 Z-1

c3 Z-2

Figure 4.9 Third-order incremental ADC with one feedback path.

whose zeros must be in the unity circle. With c1 = 3, c2 = −3 and c3 = 1, the swings of the outputs
of three integrators and DAC are Vref , 1.2Vref , 0.5Vref and 4Vref , respectively. The benefit of this
structure is that the stability is ensured with compact digital filter. Nonetheless, the DAC dynamic
range must be larger than the input to accommodate the larger error due to the difficulty in controlling
a cascade of three integrators.

RESET RESET RESET

Vin 1 1 Z-1 Vres


1 ̶ Z-1 1 ̶ Z-1 1 ̶ Z-1

c1 c2

Z-1 Z-1

Vout Dout
DAC  c3

Figure 4.10 Third-order incremental ADC with three quantizers.

Fig. 4.10 shows the block diagram of a third-order incremental ADC with multiple quantizers. The
strategy is more effective in controlling the integrator output voltages because there is a monitor of each
of them. The resolution of the three ADCs is supposed to be the same. The choice of the parameters c1 ,
c2 and c3 can give rise to unstable situations or reduce the swing at output of accumulators. The study
of the time-invariant scheme outlines a denominator of the transfer functions, which can be represented
as follows

D3ord (z) = 1 + (c1 + c2 + c3 − 3)z −1 − (2c1 + c2 − 3)z −2 + (c1 − 1)z −3 (4.7)

 NON CONVENTIONAL INCREMENTAL STRUCTURES 53

whose zeros must be inside the unity circle. Simulations that change the parameters within the stability
range identify the optimum set. Notice that different values of the c1,2,3 parameters weight in a different
manner the control of the accumulator outputs. Since a large swing in one of them affects the following,
it is logical to assume c1 = c2 = c3 . Simulations with 3-bit quantizers give rise to minimum swings
with c1,2,3 = 1. In this case, the swings of the outputs of three integrators and DAC are Vref , 0.5Vref ,
0.5Vref and 2Vref . Compared with the conventional third-order incremental structure, the swing of
the first op-amp is at almost the same level. Meanwhile, the waveform of the third op-amp’s output
remains around the value of the input signal. These drawbacks can be solved with the digital assisted
actions in the following subsections, thus, leading to an optimal architecture for third-order multi-bit
incremental ADCs.

4.2.3 Digital Assisted Actions

The operation of the proposed high-order incremental converters, in addition to the foreseen processing,
can be suitably assisted with a number of actions. They concern the digital measure of mismatches,
digital calibration and the shift of signals to keep them in the most effective region.
RESET RESET RESET

Vin 1 1 Z-1 Vres


1 ̶ Z-1 1 ̶ Z-1 1 ̶ Z-1

c1 c2

Z-1 Z-1

Vout Dout Dout2

DAC   c3

Dout1

Figure 4.11 Third-order incremental ADC with three quantizers and input level shift.

An architecture with limited output swing in integrators improves the overall performance. That
result is naturally achieved by multi-bit quantizers that limit the error in the signal estimation. However,
there are two key problems: the linearity of the DAC that must be better than the overall resolution;
the need of shifting signals around the quiescent amplitude. The first issue involves the measure of
the mismatch, possibly done in a foreground fashion using the converter itself. The digital measures
of the mismatch, stored in a memory, are the input of a digital calibration. The method is a good
alternative to the dynamic matching used in multi-bit Σ∆ modulators because the DEM technique is
not for Nyquist-rate converters.
A level shift at the input of the flash results if the input of the DAC is
Dout = Dout1 + Dout2 (4.8)
54 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

where Dout1 is a quantized version of input. This is done with the added summation node in Fig. 4.11.
Since the input is constant for the entire conversion cycle, its quantization can be performed before
starting the conversion cycle. The conversion is done at zero cost by one of the two ADCs used by
the architecture and stored in a temporary memory. Simulations show that the output swings for three
integrators and DAC are 0.5Vref , 0.4Vref , 0.3Vref and 2Vref , which is a significant improvement
compared with the former case when the digital assisted action is not used.

4.3 Algorithmic A/D Conversion

1+k

Vin Vout D
 Z-1

DAC

Figure 4.12 Conceptual block diagram of algorithmic converter. The quantizer can be a simple comparator or
a multi-bit scheme.

Previous study shows that with second-order structure, the accumulation efficiency of the input
signal is proportional to N 2 , while for third-order scheme is proportional to N 3 . From mathematical
point of view, a good way to further enhance the accumulation efficiency is to accumulate the input
exponentially, namely αN (α > 1). This can be implemented by simply introducing a feedback path
with coefficient k to a conventional first-order incremental structure. The conceptual scheme of such a
modulator is illustrated in Fig. 4.12. The input signal enters a loop at the beginning of the conversion
cycle. The use of active devices multiplies the signal by a factor m = (1 + k) every clock period while
±Vref enters the loop under the control of a comparator. The control loop keeps limited the amplitude
of the output voltage Vout . Therefore, the following equation can be derived
n−1
X
Vout (n) = Vin mn − D(n − 1 − i)Vref mn−1−i (4.9)
i=0
where, for single bit, D(i) is ±1 depending on the output of the comparator at the corresponding clock
period. D(n − 1) is the quantization of Vin in the reset clock period.
Interestingly, the structure illustrated in Fig. 4.12 turns out to be the so-called algorithmic ADC.
Algorithmic converters [4] are attractive solutions because they achieve high resolution with a number
of clock periods comparable with the number of bits. They are similar to the SAR converters but
an active multiplication of the signal every clock period keeps the input of the quantizer (typically a
simple comparator or a flash) at a suitable large level. Normal architectures use a multiplication by 2
of the signal around the feedback loop. The input injected at the beginning of the conversion cycle is
enhanced together with the signal of a DAC injected under the control of a DAC and a logic block.
 ALGORITHMIC A/D CONVERSION 55

Possible variants to the basic algorithm are the use of a multi-level quantizer and the pre-conversion
of the input with another conversion method which generates a residual (the incremental, for instance)
and the refinement of the resolution by using the algorithmic method. The latter case is used in [5]: the
algorithmic architecture is configured as a first order incremental and after a number of accumulation
of the input, the scheme becomes algorithmic. The result is that the number of bit determined in the
preliminary phase increases the final resolution. There are many possible schemes which realize the
multiplication by m. One [4] uses a loop with two amplifiers; another follows the scheme of Fig.4.12
with a positive feedback injecting k times the output at the input every conversion period. Obviously
the second solution is more power and area effective as it uses only one active element.

Φrst

Φ1 C2p
Vout+ C1p Φ2
Vin+
Φrst Vout+ Dp
Φ2 Φ1+Φrst 0.5Vos
Φ1 Op-Amp ADC Dn
-0.5Vos
Vout- C1n Φ2
Vin- Vout-
Φrst
Φ2 Φ1+Φrst
C2n

Φrst
DAC
C3n

C3p

Φ1

Φ2

Φrst
N Periods

Figure 4.13 Possible circuit implementation of a fully-differential algorithmic converter. The DAC establishes
a C3 load from virtual grounds to ground.

The limits to the practical implementation come from the error caused by the accuracy of the
multiplying factor and, in case of multi-level DAC the mismatch between the unity elements. The
use of operational amplifiers implies reduction of performance caused by finite gain, offset and limited
speed. Passive components are normally supposed with equal value. The matching accuracy, which
must be better than the inverse of the digital dynamic range of the data converter, depends on the area
of the element. Typical processes and reasonable sizes ensure accuracy between 2−10 to 2−12 range.
Achieving resolutions of more than 12-bit imposes efforts in the active devices design and
corrections of technological inaccuracy. Indeed, experimental results of a previous published solution
[5] showed that it is possible to achieve 12-bit resolution relying on the accuracy normally granted
by available technology. Aiming at more aggressive performance, the following content analyses the
56 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

limits caused by the use of real elements, then methods for compensating for those limits for getting
more than 14-bit are described.

4.3.1 Limitations of Algorithmic Architectures

The implementation limits make the algorithmic method not very attractive. The SAR scheme achieves
10 or more bit without requiring signal amplification. This makes the method superior as far as
the power consumption is concerned. For resolution of 14-bit or more, the SAR technique becomes
problematic and the use of schemes with active functions becomes almost indispensable.
In order to analyse the limits we refer to the possible circuit implementation shown in Fig. 4.13. It
is a fully differential scheme with a single op-amp and a multi-bit quantizer with a charge-generator
DAC. Capacitor C1 (and its complementary counterpart) samples the input during the reset phase.
Then it injects its charge into C2 before starting the conversion algorithm. The same switched capacitor
structure C1 amplifies the output by m = (C1 + C2 )/C2 and the DAC closes the feedback loop with
an equivalent capacitance C3 which loads the differential virtual grounds. Two differential voltage
generators model the op-amp offset. The finite gain of the op-amp is A0 .
Let us consider the limits of finite gain before. The charge conservation during each conversion
period is
1 1
Vout (n)(1 + ) =Vout (n − 1)(1 + )C2
A0 A0
Vout (n)
+Vout (n − 1)C1 − C1 (4.10)
A0
Vout (n)
+D(n − 1)Vref C3 − C3
A0
leading to
a2 Vout (n − 1) + D(n − 1)Vref
Vout (n) = (4.11)
a1
where
C1 1 C3
a1 = + (1 + )C2 +
A0 A0 A0
(4.12)
1
a2 =C1 + (1 + )C2
A0
It is evident that for different input amplitudes the digital data and the feedback give rise to a
sequence of output amplitudes unrelated to the input. The result is a non linear overall error whose
extent is large with low finite gains. Since estimating the effect is difficult, we used the above equation
in a behavioural model to determine errors as shown in Fig. 4.14. The result is that a given target
resolution determines a minimum finite gain. With our best knowledge, it is almost impossible to
correct with digital methods the limit caused by the finite gain of the op-amp. If the loss of 0.5-bit is
admitted, a 16-bit converter requires 100 dB finite gain.
The number of bits of the quantizer augments the resolution of a converter without increasing the
number of clock periods. However, the mismatch between unity elements used in the DAC limits the
linearity and adds an error whose effect is equivalent to noise. A viable solution is to employ a three-
level DAC. That is because with fully differential implementations, it is possible to ensure intrinsic
symmetrical responses. The three-level DAC grants an extra bit of resolution at the expense of two
comparators in the flash. However, a three-level DAC leads to imperceptible non-linearity because of
possible different widths of the quantization intervals representing the three logic levels. Simulation
results show minor harmonic terms as outlined in the output spectrum of Fig. 4.15 (thresholds at
 ALGORITHMIC A/D CONVERSION 57

1 6 .0
1 5 .5 N = 1 2
1 5 .0 N = 1 4
1 4 .5 N = 1 6
1 4 .0
1 3 .5
1 3 .0
E N O B (b it)

1 2 .5
1 2 .0
1 1 .5
1 1 .0
1 0 .5
1 0 .0
9 .5
9 .0
8 .5
5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0
O p - A m p G a in ( d B )

Figure 4.14 Equivalent number of bit versus the finite gain of the op-amp used in an algorithmic converter.

±0.5Vref ). The tones are at around −100 dBF S , denoting a limited distortion contribution normally
below common specifications.

-2 0 S N R = 8 7 .0 d B

-4 0

-6 0
(d B )

-8 0

-1 0 0
P S D

-1 2 0

-1 4 0

-1 6 0

-1 8 0
0 .0 0 0 .0 5 0 .1 0 0 .1 5 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .5 0
F re q u e n c y (H z )

Figure 4.15 Spectrum of an algorithmic converter with a 3-level quantizer.

The offset of the operational amplifier causes a shift in the injection of the signals returning back
from the op-amp output and the one determined by the DAC. Accounting for the offset limit (and
supposing the gain of op-amp is very large) the charge conservation equation leads to

[Vout (n) − Vos ] C2 = [Vout (n − 1) − Vos ] C2 +

[Vout (n − 1) + Vos ] C1 + (4.13)
[−D(n − 1)Vref + Vos ] C3
58 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

supposing C1 = C2 = C3 it results

Vout (n) = 2Vout (n − 1) − D(n − 1)Vref + 2Vos (4.14)

Notice that there are two consequences related to the limit caused by offset. Looking from the
DAC output point of view, offset corresponds to a shift of the input by Vos (1 + C1C+C 2
3
), which is
equivalent to a corresponding input referred offset. The situation is different when looking at the
output multiplication effect. Indeed, since the circuit achieves the multiplication by adding a replica
of the output voltage Vout , the consequence of offset is to alter the multiplication factor. In the special
case that the output equals to the minus offset, the multiplication reduces to 1, and in general is,
Vout + Vos
m=1+ (4.15)
Vout
which changes in an unpredictable, pseudo-random manner, depending on the sequence the output
voltage.
The use of the above equations to build a behavioural model verifies expected result. The output
shows an offset and worsening of the equivalent number of bit because of a pseudo-white noise. Fig.
4.16 compares spectra with a −3 dBF S input sine wave and zero or 4 mV offset. The expected full
scale SNR of the converter is 98 dB. The circuit uses two level quantizer with Vref = ±1V . Result
show that just 4 mV degrade the performance by 33.1 dB corresponding to a loss of 5.5-bit.
Fig. 4.17 plots resolution versus offset with expected 16 and 18-bit and Vref = ±1V . The loss
strongly depends on sine wave amplitude and frequency. However, 0.85 mV and 0.37 mV offset
causes a loss of 1 bit for the two foreseen resolutions. The result shows that in order to ensure high
resolution, the essential range of offset should be sub 1 mV .

0
S N R = 9 4 .9 d B ( Id e a l)
-2 0
S N R = 6 1 .8 d B (V o s = 4 m V )
-4 0

-6 0
(d B )

-8 0
P S D

-1 0 0

-1 2 0

-1 4 0

-1 6 0
0 .0 0 0 .0 5 0 .1 0 0 .1 5 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .5 0
F re q u e n c y (H z )

Figure 4.16 Output spectrum with zero offset and 4 mV offset, showing an increase of the noise floor.

Another important limit is given by the error caused by capacitor mismatch. Even if it is possible
to limit the error, the technique such as the one proposed in [6] works well until 12-bit. Mismatch
determines the accuracy of used base of numbering system, typically 2 when C1 is chosen nominally
equal to C2 . Moreover, the mismatch between capacitors C1 and C2 gives rise to gain error. The
difference between the effective and the expected multiplication factor causes an error which increases
 ALGORITHMIC A/D CONVERSION 59

1 8 .5
1 8 .0
N = 1 6
1 7 .5 N = 1 8
1 7 .0
1 6 .5
1 6 .0
E N O B ( b it)

1 5 .5
1 5 .0
1 4 .5
1 4 .0
1 3 .5
1 3 .0
1 2 .5
1 2 .0
0 .0 0 .2 0 .4 0 .6 0 .8 1 .0 1 .2 1 .4
O ffs e t (m V )

Figure 4.17 Equivalent number of bit at output of a 16-bit an 18-bit algorithmic cover for different offset values.

0
-2 0 .0 2 5 %
-4
0 .0 5 %
-6
1 2 b )

-8
-1 0
0 .1 %
E rro r (L S B @

-1 2
-1 4
-1 6
-1 8
-2 0
-2 2
0 5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0
In p u t (L S B @ 1 2 b )

Figure 4.18 Error caused by capacitor mismatch for a 12-bit ADC.

with the code. Fig. 4.18 shows the error for a 12-bit algorithmic converter with mismatches by 0.1%,
0.05% and 0.025%. Result shows a gain error and a non linear error whose maximum occurs at the
mid-scale. In order to constrain the DNL below 1 LSB, a matching accuracy about 1/2N is necessary,
where N is the number of bit of the converter. Since with modern technologies it is possible to get 1-σ
matching accuracy in the order of 0.05%, designing converters more than 10-12 bit requires actions
capable to correct the mismatch limit.
60 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN CONSIDERATIONS

4.3.2 Error Correction Methods

The correction of static errors in data converters can be done in the background or the foreground [7].
Here we suppose to measure errors using a foreground approach. It is possible to extend the method to
background by interleaving the foreground method with normal operation.
The previous sections outlined two key limits: offset of the op-amp and mismatch between C1
and C2 . In order to achieve good resolution, the measurement of these non-ideal factors is necessary.
Notice that the scheme of Fig. 4.13 can be reconfigured as a first order incremental converter. After the
reset of the capacitor in feedback across the op-amp, it accumulates the input signal for a given number
of clock periods, say N = 2r . The incremental algorithm uses only the DAC feedback. Neglecting
mismatches, the final output of op-amp is
N
X
Vout (N ) = N Vin − Vref D(i) (4.16)
i=1

where D(i) is ±1, denotes the sign of Vout (i) at the i-th clock period. The use of a large number of
clock periods N measures the quantity under calibration with an r-bit resolution.
The use of the scheme of Fig. 4.13 in the incremental converter mode enables us to measure offset
and mismatch by the following configurations:
I Measure of offset: disable SC structure with C1 . According to (8) the digital accumulation
at output determines the offset. The accuracy of the measure is within the matching between the
capacitors C2 and C3 .
I Measure of mismatch between C1 and C2 : inject a fraction α of reference voltage with SC
structure C1 and then disable it (case a). Repeat the measure with the role of C1 and C2 reversed and
same fraction α of reference at input (case b).
After N clock periods the digital outputs in the two cases provide the following measures

Ya = (αVref + Vos )C1 /C3 ; (4.17)

and
Yb = (αVref + Vos )C2 /C3 ; (4.18)
with r bit of accuracy. The ratio between Ya and Yb determines the mismatch.
The measure of offset and mismatch can be done by a specific calibration cycle at the power-
on or during inactivity periods (foreground calibration). Alternatively, it is possible to use an extra
clock period per conversion and use that clock period with the incremental configuration (background
calibration). In the latter case a calibration supplementary capacitor, which is inserted during the extra
phase, should be employed.
The measure of offset enables its correction in the analog domain with different methods. For
instance, it is possible to properly shift reference voltages or to suitably correct offset by an extra
op-amp input pair. The correction of mismatch can be done by digital processing that transforms the
measured result into binary.
 ALGORITHMIC A/D CONVERSION 61

REFERENCES

1. V. Quiquempoix et al., “A low-power 22-bit incremental ADC”, IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1562-1571, May 2005.
2. Colin Lyden et al., “A single shot sigma delta analog to digital converter for multiplexed applications”, in
Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 203-206, May 1995.
3. Colin Lyden et al., “Modeling sigma-delta modulator non-idealities in SIMULINK(R)”, in Proc. IEEE
Custom Integrated Circuits Conf. (CICC), pp. 203-206, May 1995.
4. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A ratio-independent algorithmic analog-to-digital
conversion technique”, IEEE J. Solid State Circuits, vol. SC-19, pp. 828-836, Dec. 1984.
5. Rombouts, P. et al., “A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits”, Proc.
European Solid-State Circuits Conference (ESSCIRC), pp. 213-216, Sept. 2012.
6. Quinn, P. and Pribytko, M., “Capacitor Matching Insensitive 12-bit 3.3MS/s Alogrithmic ADC in 0.25µm
CMOS”, Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 425-428, Sept. 2003.
7. F. Maloberti, Data Converters. Dordrecht: Springer, 2007.
CHAPTER 5

A 17-BIT INCREMENTAL A/D CONVERTER:

DESIGN AND IMPLEMENTATION

This chapter describes a second-order 3-bit incremental converter, which employs a novel Smart-DEM
algorithm to compensate for the mismatch of unity elements of multi-level DAC. The design, which is
fabricated in a mixed 0.18-0.5-µm CMOS technology, obtains more than 17-bit resolution over a 5 kHz
bandwidth by using 256 clock periods per sample. A single-step chopping technique is adopted which
leads to a residual offset of 9.7 µV. The measured power consumption is 280 µW and the achieved
Figure of Merit (F OMS ) is 177.5 dB.

5.1 Proposed Architecture

Based on architecture illustrated in Fig. 4.7 with c1,2 = 1 and bq = 3, the proposed second-
order scheme is derived and shown in Fig. 5.1. It is the cascade of two sampled-data integrators (one
without delay, the other with delay) with three ADCs, which digitize the input signal and the outputs
of the two integrators. The digital output is the addition of the three analog-to-digital conversions. The
quantization step of each ADC is VF S /8. For such a second-order modulator, the maximum achievable
resolution is

N (N − 1)
R2ord = log2 + bq (5.1)
2!
With N = 256 and bq = 3, R2ord is equal to 17.99-bit and the full scale value is 261,120.
Multi-Bit A/D Converters with High Resolution and Low-Power. 63
By Yao Liu
64 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

ADC1

5-level
(3-bit)
ADC2

Z-1
9-level
RESET RESET
(3-bit)

ADC3
Vin 1 Z-1 Vres Dout
 
1 ̶ Z-1 1 ̶ Z-1
5-level
(3-bit)
13-level RESET

(3-bit)
SMART
DAC
DEM

Figure 5.1 Proposed second-order incremental ADC block diagram.

0 .4

0 .3
) R E F

0 .2
S w in g o f F irs t-In te g ra to r (V

0 .1

0 .0

-0 .1

-0 .2

-0 .3

-0 .4
0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 0 2 2 5 2 5 0
K th (C lo c k P e rio d )

Figure 5.2 Swing of the first-integrator under constant input 0.707Vref .

The digital feedforward paths limit the swing at the output of the op-amps. Notice that Fig. 5.1
mimics with digital paths the second-order scheme proposed in [1]. The scheme ensures stability and
limits the op-amp swings. Fig. 5.2 show the swings of the first integrator when a constant signal
Vin = 0.707Vref is applied. With extensive behavioural level and transistor level simulations, the
output swing of both the first and second integrators is within 0.4Vref . This allows the use of only
4 comparators instead of 8 for ADC2 and ADC3. The output swing of DAC is 1.5Vref . This means
that for a 3-bit DAC, 4 extra unity elements should be added to extend the total level of DAC from 9
to 13. However, with a bipolar DAC structure, the number of unity elements is reduced to 6, which is
affordable in terms of both implementation complexity and power dissipation.
 ANALOG BUILDING BLOCKS 65

Finally, in order to compensate for the mismatch of 6 unity elements, a Smart-DEM block is added
to properly select the unity elements in the multi-level DAC in each clock period. The details of
Smart-DEM principle and implementation will be discussed in the following sections.

Φrst Φrst
Cu Cu
Φ1 Cu Φ2 chp Φ2 Cu Φ1
Vin
Φ2 Φ1 chp Φ1 Φ2

Vin

DAC X6 Cu Φ2 Φq Φq Φq

Φq
Φrst
-Vref -Vref
Φq Φ2 A1
Dout
A2 SDEM
A1 A2
A1 A2
Φq Φ2 Φ2 Φq Φsdem
Vref Vref

Φ1
A1 A2
0 0 No Effect Φ2
0 1 Positive Charge
1 0 Negative Charge Φq
1 1 No Effect
Φrst 256 Clock Periods

Figure 5.3 Proposed second-order incremental ADC schematic diagram.

5.2 Analog Building Blocks

Fig. 5.3 shows the schematic of the proposed second-order incremental ADC. The 2 integrators
are implemented with switched capacitor (SC) circuits. By using different clock phases φ1 , φ2 , and
φrst , the integrators can performance charge, injection or reset functions. The different delays of
integrators are realized by proper control of the switches with various clock phases. Notice that the
first op-amp contains a chopper, which is used for the cancellation of offset of the modulator. As
mentioned previously, ADC1 contains 8 comparators, while ADC2 and ADC3 use 4 comparators due
to the reduced output swing of integrators. The 3 quantizers digitize the input signal and the outputs of
2 integrators. A digital summation block uses these 3 digital quantization results to generate the output
of the modulator Dout .
66 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

The most critical parts of this design are the Smart-DEM (SDEM) block and the bipolar DAC. As
seen in Fig. 5.3, the Smart-DEM block is under the control of φq (charge the DAC), φ2 (discharge the
DAC), φrst (reset the Smart-DEM) and φsdem (Smart-DEM internal operations). The output signals of
Smart-DEM block are A1 [6 : 1] and A2 [6 : 1], which are used to properly select unity elements in the
DAC. In the following subsections, the design and implementation of the analog building blocks and
related techniques are detailed explained, which include op-amp and single-chopping method, bipolar
DAC with controls and low-power comparator.

5.2.1 Operational Amplifiers

VDD

M14 VCMFB VB1 M1 VCMFB M17

VIN+ VIN-
M13 VCM M2 M3 M4 M5 VCM M16
VOUT- VOUT+
M12 VCM M6 M7 VCM M15
VB2

M8 M9 M10 M11

VSS

Figure 5.4 Recycling operational amplifier schematic diagram.

The performance of an op-amp is limited by various factors, mainly the DC gain, bandwidth and
slew rate. Ideally, the values of these 3 parameters should be infinite and the op-amp behaves as a
voltage control current source (VCCS). In reality, limited values of these 3 parameters give rise to
circuit imperfections. For the second-order incremental ADC depicted in Fig. 5.3, error caused by
circuit imperfections of the first op-amp is accumulated linearly by the second integrator. Hence,
specifications of the first op-amp are more strict than those of the second op-amp. Besides, in order
to achieve 18-bit resolution, a large CS is required to suppress kT/C noise from the input of the
modulator. In this design, VF S is 3 V under a 3.3 V analog power supply. The Cu is 450 fF and
the total input capacitance for 8 unity elements is 3.6 pF. In such a case, it is very difficult to achieve
sufficient bandwidth and slew rate under a very low power dissipation budget with conventional op-
amps. Special architectures and design techniques on op-amps should be adopted so as to meet the
strict specifications.
The first op-amp scheme, shown in Fig. 5.4, is a fully differential recycling folded cascode amplifier
(RFCA), with discrete-time common mode control (not shown in the figure). VB1 and VB2 are biasing
voltages generated by a bias circuit(not shown in the figure) while VCM is the common mode voltage.
The reason of a utilizing such an op-amp is that, as explained in [2], this structure can boost the gain,
bandwidth and slew-rate without affecting noise performance or introducing additional offset.
Firstly, let us compare the equivalent transconductance Gm of RFCA and traditional folded cascode
amplifier (FCA). As seen in Fig. 5.4, two input PMOS transistors in FCA structure are split to 4 equal
 ANALOG BUILDING BLOCKS 67

transistors in RFCA schematic. When applying a small differential voltage signal 4Vin between Vin+
and Vin− , the generated small current signal 2gm2 4 Vin is amplified (1 + k)/2 times at the outputs
of RFCA because of the current mirrors (M6-M11), where gm2 is the transconductance of M2 (or M3)
and k is the ratio of M9 to M8. With this observation, the equivalent transconductance of RFCA can
be estimated as

GmRF CA = (1 + k) × gm2 (5.2)

while for FCA structure, we have
GmF CA = 2 × gm2 (5.3)
According to [2], the reasonble value of k is between 2 to 4. In this design, k = 3 is chosen and by
using (5.2) and (5.3), GmRF CA = 2 × GmF CA can be achieved. In this case, the RFCA is able to
double the equivalent transconductance with the same power consumption and slightly area cost for 4
additional NMOS transistors (M6, M7, M9 and M10).
The second parameter to be studied here is the output resistance RO. With regard to RFCA, the
output resistance can be derived as
RORF CA ≈ gm12 rds12 (rds8 k rds2 ) k gm13 rds13 rds14 (5.4)
where gm12 and gm13 indicates transconductance of M12 and M13. Moreover, rds2 , rds8 , rds12 ,
rds13 and rds14 mean small drain source resistance of M2, M8, M12, M13 and M14. Using the same
method, ROF CA is also estimated, which has the same representation as (5.5) and it is not shown
here. However, the use of less current in M2, M5, M8 and M11 gives rise to an augment of the
corresponding rds . Since GmRF CA is twice of GmF CA , the gain of RFCA is 6 dB higher than the
gain of FCA considering the same RO. Therefore, an overall DC gain enhancement of 8 ∼ 10 dB can
be observed in the RFCA compared to the FCA [2].
The RFCA illustrated in Fig. 5.4 is implemented with 0.18µm CMOS technology. The simulated
DC gain and gain bandwidth product (GBW) under typical conditions is 95 dB and 19 MHz. The
second op-amp is a conventional fully differential folded cascode amplifier, which obtained 83 dB gain
and 21 MHz GBW.

5.2.2 Single Step Chopping Technique

The accurate sample-to-sample conversion of incremental ADCs demands for low offset. However, if
offset cancellation methods were not properly adopted, the offset of op-amps would result in large
offset at the digital output of the modulator. The reason is that, for a second-order incremental
ADC, the offset of the first op-amp is accumulated parabolically on Vres node, while the offset of
the second op-amp is linearly integrated at Vres . Hence, offset nulling techniques are necessary for
incremental modulators. Several offset cancellation methods were proposed in open literature, such
as a fractal sequence technique reported in [3] for a third-order modulator. However, the drawback of
this technique is its limitation on the number of clock periods per conversion cycle. Another effective
method is the single step chopping technique presented in [4], which is adopted in a second-order
incremental ADC and the measured residual offset is 1.5 µV.
With regard to the second-order modulator illustrated in 5.1, the offset of the first integrator is the
main source of the output offset, but even other contributions affect the overall offset. This circuit
compensates for all the sources by a single chopping of the input stage [4]. If a single chopping occurs
at the Kth clock cycle out of N , the offset of the first op-amp, Vos1 , reverses while the remaining
source, Vos2 , referred to the input of the second op-amp is unchanged. In this case, the input referred
offset becomes
68 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

Φ1

Φrst N Clock Periods

Φchp K Clock Periods

(a)
1 .0
0 .8
0 .6 K = 1 8 1
0 .4 a 1= 5 .1 e -3
V a l u e o f α1

0 .2
0 .0
- 0 .2
- 0 .4
- 0 .6
- 0 .8
- 1 .0
0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 0 2 2 5 2 5 0
K th (C lo c k P e rio d )
(b)

Figure 5.5 (a) Single step chopping clock; (b) The value of α1 with respect to kth clock period for chopping.

 
2(K − 1)(K − 2) 2
Vos,in = 1− Vos1 + Vos2
(N − 1)(N − 2) N −2 (5.5)
=α1 Vos1 + α2 Vos2
Fig. 5.5(a) illustrates the chopping clock phase φchp with respect to φ1 and φrst , which is not shown
in Fig. 5.3. By trimming the value of K, it is possible to obtain a value of α1 which compensates for
both offset sources. Fig. 5.5(b) plots the value of α1 versus K. If N = 256 and K = 181, the offset
of the first op-amp is multiplied by α1 = 5.1 × 10−3 while α2 = 7.9 × 10−3 . Vos1 diminishes by a
factor 196 and Vos2 is naturally reduced by 127.

5.2.3 Bipolar DAC and Controls

As seen in Fig. 5.3, the bipolar DAC contains 6 unity capacitor with nominal value Cu = 0.45 pF.
Rewrite (3.10), we have
1 + 2 + ... + 6 = 0 (5.6)

As discussed in Section 3.2, the left terminal of each capacitors in bipolar DAC can be connected to
Vref or −Vref either during φq or φ2 . With proper control signals A1 [6 : 1] and A2 [6 : 1], the bipolar
DAC can realize positive, negative or null injection. Tab. 5.1 illustrates the relationship between
Dout [12 : 1], A1 [6 : 1], A2 [6 : 1] and Vmis (k). The Dout [12 : 1] has 13 digital codes, with a decimal
 ANALOG BUILDING BLOCKS 69

value from 0 to 12. The digital code corresponding to the common mode level is 6. The output swing
of the 3-bit DAC is 1.5Vref .
The following are several examples to explain the usage of Tab. 5.1. For instance, when a digital
code 6 is the output of the summation block, its thermometric representation is Dout [12 : 1] =
000000111111. Regarding to Tab 5.1, we can find the related control signals are A1 [6 : 1] = 111111
and A2 [6 : 1] = 111111. Hence, The equivalent mismatch Vmis (k) introduced in this clock
period is 0. However, if the digital code is 1, the corresponding thermometric representation is
Dout [12 : 1] = 000000000001. Referring to Tab. 5.1, the control signals are A1 [6 : 1] = 000000
P5
and A2 [6 : 1] = 011111. Thus, the related Vmis (k) is represented by −2Vref m i=1 i . Using (5.6),
the negative sign can be removed and finally Vmis (k) = 2Vref m 6 .

Table 5.1 The relationship between Dout [12 : 1] and Vmis (k).

Vin [12 : 1] A1 [6 : 1] A2 [6 : 1] Vmis (k) Vmis (k) with (5.6)

P6
111111111111 111111 000000 2Vref m i 0
Pi=1
5 P5
011111111111 111111 100000 2Vref m i 2Vref m i
Pi=1
4 Pi=1
4
001111111111 111111 110000 2Vref m i=1 i 2Vref m i
P3 Pi=1
3
000111111111 111111 111000 2Vref m i=1 i 2Vref m i
P2 Pi=1
2
000011111111 111111 111100 2Vref m i=1 i 2Vref m i=1 i
000001111111 111111 111110 2Vref m 1 2Vref m 1
000000111111 111111 111111 0 0
P6
000000011111 000000 000001 −2Vref m 1 2Vref m i
Pi=2
−2Vref m 2i=1 i 6
P
000000001111 000000 000011 2Vref m i
Pi=3
−2Vref m 3i=1 i 6
P
000000000111 000000 000111 2Vref m i
Pi=4
−2Vref m 4i=1 i 6
P
000000000011 000000 001111 2Vref m i=5 i
−2Vref m 5i=1 i
P
000000000001 000000 011111 2Vref m 6
−2Vref m 6i=1 i
P
000000000000 000000 111111 0

5.2.4 Low-Power Comparator

Fig. 5.6 shows the schematic of the fully differential voltage comparator adopted in this second-order
incremental modulator [5][6]. The comparator consists of two stages, namely the pre-amplifier and
the regenerate latch. Transistors M1-M9 forms the pre-amplifier with 9 dB DC gain and the total
biasing current is 0.5 uA with 3.3 V analog power supply. The regenerate latch consists of transistors
M10-M17. When the clock signal VCLK is low, the outputs of the comparator VOU T + and VOU T −
are reset to 3.3 V. Meanwhile, the intermediate nodes VX and VY are connected with a PMOS switch
in order to erase the history information. The outputs of the comparator is generated when VCLK is
high. In this case, the pre-amplifier senses the difference of the 4 input terminals and the outputs of
the pre-amplifier are VX and VY , which drive the input transistors M18 and M19 of the regenerate
latch. With VCLK = 3.3 V, the second stage becomes 2 back-to-back CMOS inverter. The difference
of discharge speed on VOU T + and VOU T − determines the final outputs. Simulation results show that
the typical delay of this comparator is 2 ns and the sensitivity is less than 1 mV. The offset of the
comparators does not affect the performance of the modulator, as demonstrated with simulations on
both behavioural level and transistor level.
70 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

VDD
VB VB
M1 M2 M10 M11
VCLK VCLK
M12 M13
VREF- VREF+
VIN+ VIN-
M3 M4 M5 M6 VOUT+ VOUT-
M14 M15
VX VY VCLK VCLK
M16 M17
VCLK

VX M18 M19 VY
M7 M8 M9

VSS

Figure 5.6 Low-power comparator schematic diagram.

5.3 Digital Building Blocks

AUXILIARY
MEMORY MEMORY ADDER 1
3 6 ADDER 2 CLK and
2 5 ADDER 3 WEIGHTS
RESET
5 4 ADDER 4 GEN
1 3 ADDER 5 GEN
4 2 ADDER 6
6 1

SDEM
SDEM CROSS
FINITE STATES MACHINE NETWORK

5-levels
P1 6 6

ADC2 z-1
SDEM A1 A2
5-levels DECODER
P2
+
+ DOUT
ADC3 ∑
+
9-levels
VIN
ADC1

Figure 5.7 The block diagram of Smart-DEM implementation.

 DIGITAL BUILDING BLOCKS 71

This section discusses about the digital circuits employed in the proposed second-order incremental
ADC. Since the operation principles of Smart-DEM were comprehensively introduced in Chapter 3,
the first part of this section focuses on the implementation of the Smart-DEM algorithm with modern
CMOS technology. Following the Smart-DEM block, we shall briefly introduce the second digital
block — the multi-phase clock generator.

5.3.1 Smart-DEM Block

Φrst

Φ1 16 Tsdem

Φ2 16 Tsdem

Φq 8 Tsdem 8 Tsdem

Φsdem
32 Tsdem

Figure 5.8 Clock phases used in Smart-DEM block.

Fig. 5.7 shows the block diagram of Smart-DEM algorihm implementation in this design. The
working flow is as follows: the summation of the outputs of 3 quantizers Dout is an integer number
ranging from 0 to 12 for 13 levels. The SDEM encoder transform Dout to 2 temporary control signals
A1t [6 : 1] and A2t [6 : 1]. Under the control of SDEM finite state machine (FSM), the weight
corresponding to the current clock period is calculated. Whereafter, it is added to the weights of
the selected unity elements. The insert-sorting algorithm orders the results, temporarily stored in the
auxiliary memory. The minimum of values is subtracted to reduce the required length of registers and
returned back to the primary memory. The cross network uses the new order of elements in the next
clock period to give rise to the A1 [6 : 1] and A2 [6 : 1] output control signals.
As depicted in Fig 5.3, the SDEM FSM block is under the control of clock phases φ2 , φq , φsdem
and φrst . Fig 5.8 illustrates more detailed relationship of these clock phases. The master clock φsdem
runs 32X of the analog sampling clock φ1 . When φq is high, the SDEM FSM uses the current Dout
and internal information and generates correct control signals A1 [6 : 1] and A2 [6 : 1] in 2Tsdem . The
rest 6Tsdem is used for the DAC to charge the unity capacitors. When φ2 becomes high and φq turns
low, A1 [6 : 1] and A2 [6 : 1] control the bipolar DAC to properly inject the charge on the first integrator
for 16Tsdem . Meanwhile, SDEM FSM updates its internal status and prepares a new sorted table of
weights for the operation of the next clock period.
Fig. 5.9 illustrates the transition of state (SF SM ) of SDEM FSM. The operation flow is explained
as follows: when the modulator is reset by φrst , SF SM is set to RST. As seen in Fig. 5.8, a full analog
sampling clock period starts from the positive edge of φ1 to the negative edge of φ2 . During the first
8Tsdem , SF SM is set to START and SDEM FSM does not operate. This period is used by the second
integrator to inject the charge. When the positive edge of the 9th Tsdem arrives, the SDEM block
receives the input signal from the summation node Dout [12 : 1] and transforms it to A1t [6 : 1] and
72 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

Φrst=1
RST

Φrst=0 Φrst=1

30Tsdem
START SCALE
Insert- 29Tsdem
[1-8]Tsdem Sorting
9Tsdem

DECODE SHIFT COMPARE

[11-16]Tsdem 10Tsdem
19Tsdem
17Tsdem 18Tsdem
OUTPUT UPDATE INSERT

DAC Charge DAC Discharge

(Φq =1) (Φ2 =1)

Figure 5.9 State transition diagram of SDEM finite state machine.

A2t [6 : 1] (SF SM = DECODE). In the next Tsdem , the cross network uses A1t [6 : 1], A2t [6 : 1]
and weight table in the primary memory of SDEM to generate the real controls A1 [6 : 1] and A2 [6 : 1]
(SF SM = OU T P U T ). From 11th Tsdem to 16th Tsdem , the bipolar DAC charges the unity capacitors
under the control of A1 [6 : 1] and A2 [6 : 1]. At the same time, the SDEM FSM simply maintain the
status SF SM = OU T P U T .

RESET T=1 T=1 T=2 T=2 T=2 End of T=256

C6 0 C6 0 C4 254 C4 254 C1 507 C1 253 C5 2

C5 0 C5 0 C3 254 C3 254 C4 254 C4 1 C2 1
C4 0 C4 254 C2 254 C2 254 C3 254 C3 1 C3 1
C3 0 C3 254 C1 254 C1 507 C2 254 C2 1 C4 1
C2 0 C2 254 C6 0 C6 253 C6 253 C6 0 C6 1
C1 0 C1 254 C5 0 C5 253 C5 253 C5 0 C1 0
Dout=10 Dout=9
W(1)=254 W(2)=253

Figure 5.10 The status of the weights in SDEM block with Vin = 0.926Vref . The range of Dout is from 0 to
12 and the common mode level is 6.

When the φ2 is high, the DAC starts to inject its charge on the first integrator. When arriving the
positive edge of the first Tsdem (17th Tsdem in the whole analog clock period), SDEM FSM updates the
weights of unity elements selected in 10th Tsdem (SF SM = U P DAT E). Consequently, the weights
 DIGITAL BUILDING BLOCKS 73

of unity elements are no longer in a sorted order. An insert-sorting algorithm is thus performed by
SDEM to order the weights. Before the sorting algorithm starts, it is necessary to copy the weights
in the primary memory to the backup memory and then reset the main memory to 0. After that,
the second step is to insert the weight of the unity elements at the bottom of the backup memory
(SF SM = IN SERT ). At this point, the preparation of the insert-sorting algorithm has been finished.
The SDEM FSM uses the next 10Tsdem to sort the weights in the backup memory and than copy these
values to the primary memory (SF SM = SHIF T, COM P ARE). After the sorting algorithm, an
operation named scale is performed, which requires all the weights subtract the minimum weight in
the primary memory from themselves (SF SM = SCALE). The reason of this operation is to prevent
hardware overflow, since the word length of the weight is limited. After the scale operation, SF SM is
set to START to wait for the operations in the next analog clock period.

T=2 (18TSDEM) T=2 (19TSDEM) T=2 (20TSDEM) T=2 (21TSDEM)

SFSM=INSERT SFSM=COMPARE SFSM=SHIFT SFSM=COMPARE
C4 254 C4 254 C4 254 C4 254
C3 254 C3 254 C3 254 C3 254
C2 254 C2 254 C2 254 C2 254
C1 507 C1 507 C1 507 C1 507
C6 253 C6 253 C6 253 C6 253 C6 253 C6 253
C5 253 C5 253 C5 253 C5 253 C5 253 C5 253 C5 253 C5 253

T=2 (22TSDEM) T=2 (23TSDEM) T=2 (24TSDEM) T=2 (25TSDEM)

SFSM=SHIFT SFSM=COMPARE SFSM=SHIFT SFSM=COMPARE
C4 254 C4 254 C4 254 C4 254
C3 254 C3 254 C3 254 C3 254
C2 254 C2 254 C1 507 C2 254 C1 507 C2 254
C1 507 C1 507 C1 507 C1 507 C2 254 C1 507 C2 254 C1 507
C6 253 C6 253 C6 253 C6 253 C6 253 C6 253 C6 253 C6 253
C5 253 C5 253 C5 253 C5 253 C5 253 C5 253 C5 253 C5 253

T=2 (26TSDEM) T=2 (27TSDEM) T=2 (28TSDEM) T=2 (29TSDEM)

SFSM=SHIFT SFSM=COMPARE SFSM=SHIFT SFSM=SCALE
C4 254 C4 254 C1 507 C4 254 C1 253
C1 507 C3 254 C1 507 C3 254 C4 254 C3 254 C4 1
C3 254 C2 254 C3 254 C2 254 C3 254 C2 254 C3 1
C2 254 C1 507 C2 254 C1 507 C2 254 C1 507 C2 1
C6 253 C6 253 C6 253 C6 253 C6 253 C6 253 C6 0
C5 253 C5 253 C5 253 C5 253 C5 253 C5 253 C5 0

Figure 5.11 Insert-sorting algorithm example for the proposed second-order incremental ADC (Vin =
0.926Vref and T = 2).

An example of the insert-sorting algorithm in illustrated in Fig. 5.11. This example starts from the
18th Tsdem in the second analog clock period (T=2) when a constant Vin = 0.926Vref is applied to
the input of the proposed second-order incremental ADC (Fig. 5.10). As seen in Fig. 5.11, in the
18th Tsdem , the content of the primary memory (solid-line) is copied to the auxiliary memory (dash-
line). Meanwhile, all the weight information in the primary memory is erased except the one at the
bottom of the array. An pointer CUR IDX is set to 253 (C6), which indicates the next weight for insert
operation is 253 (C6). In the next Tsdem , SDEM FSM compares the weight pointed by the CUR IDX
74 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

with all the weights already inserted in the primary memory. Since 253 (C6) is the same with 253 (C5),
SDEM FSM simply insert 253 (C6) at the adjacent position above 253 (C5) in 20th Tsdem and updates
the CUR IDX to point to 507 (C1). Similarly, C1 (507) is inserted into the primary memory at the
adjacent position above 253 (C6) and the CUR IDX points to 254 (C2). However, in the 23rd Tsdem ,
SDEM FSM compares 254 (C2) with 507 (C1), 253 (C6) and 253 (C5) and find out that 507 (C1) is
larger than 254 (C2). Under such a situation, in the next Tsdem , 507 (C1) is shifted up one position,
while 254 (C2) is inserted into the original position occupied by 507 (C1). Following this method,
SDEM FSM uses the insert-sorting algorithm to move the larger value to the top of the weight array
and smaller value to the bottom. At the end of 28th Tsdem , all the weights in the primary memory are
in a sorted order. To prevent hardware overflow, the scale operation is performed in the 29th Tsdem ,
which means all the weights need to subtract the minimum weight 253 (C5) from themselves. As seen
in Fig. 5.11, the largest weight in the primary memory after the scale operation is 253 (C1) while the
minimum one is 0 (C5).
With regard to Smart-DEM implementation, it is firstly described in Verilog-HDL, which is
then transformed to a gate-level netlist (about 1.2k gates) by Design Compiler. For the standalone
Smart-DEM digital block, NC Verilog is used for both behavioural-level and gate-level verification.
Whereafter, a mixed-signal simulator SpectreVeriog is adopted for the full chip verification.

5.3.2 Multi-Phase Clock generator

Φchp_in Φchp
D Q
Clk
BUF DFF Q
Buffer Tree (X4)

Φrst
D Q
Clk
DFF Q
Buffer Tree (X4)
Φ12 Φ1

Φsdem_in Non-Overlap Φ22 Φ2

Φ11

Buffer Tree (X8)

Φcmfb12 Φcmfb1
Phase Φcmfb11
Generator Non-Overlap Φcmfb22 Φcmfb2

Φrst_in Buffer Tree (X4)

Φq1 Φq
Delay

Buffer Tree (X8)

Φsdem1 Φsdem
Delay

Buffer Tree (X2)

Figure 5.12 Multi-phase clock generator block diagram.

 EXPERIMENTAL RESULTS 75

In order to drive the SC circuits and the Smart-DEM block, an on-chip multi-phase clock generator
is included in this design. As seen in Fig. 5.12, the inputs of the clock generator are φchp in , φsdem in
and φrst in . φchp in is the chopping signal used for single-step chopping operation. φsdem in is the
master clock of the whole chip, and φrst in is the reset signal generated manually on the PCB board.
The phase generator, as can be seen in Fig. 5.12, is used to generate the analog sampling phase
φ11 and φq1 (divide-by-32), clock signal for the common mode feedback (CMFB) of the op-amps
φcmf b11 (divide-by-256) and reset signal for both analog and digital circuits φrst1 . Moreover, the
phase generator buffers itself and outputs φsdem1 . Meanwhile, 2 D-flip-flops (DFF) are used to align
φrst1 and φchp in with φ11 . It can be noticed that 2 non-overlap blocks are employed. The first one
generates 2 non-overlap clocks φ12 and φ22 , which are further buffered by X8 buffer trees to become
the main analog sampling clock φ1 and φ2 . Using φcmf b11 , the other non-overlap block generates
φcmf b12 and φcmf b22 . These 2 signals then go though X4 buffer trees and turn into φcmf b1 and φcmf b2
used for the CMFB circuits of op-amps. In order to compensate for the delay due to the non-overlap
blocks, several delays are added to minimize the skew between different clock signal paths. Finally,
it can be noticed that a bank of buffer trees are included with different sizes (X2, X4 and X8). These
buffer trees are used to boost the driving capability for 8 output clocks, depending on the different
loads of various clocks.

5.4 Experimental Results

This section describes the experimental results of the proposed second-order incremental ADC.
To start with, the design of testing board and measurement setup are described. Whereafter the
measurement results are detailed discussed. A comparison of the proposed modulator with state of
the art is given in the last part of this section.

5.4.1 Test Setup

An experimental prototype of the proposed second-order 3-bit incremental ADC is fabricated in
a 0.18-0.5-µm CMOS technology with dual poly and 6 metal layers. Fig. 5.13 shows the chip
microphotograph with main circuital blocks highlighted. The active area is 1270×900 µm2 (the chip
area is 1600×1300 µm2 ). To avoid interferences, a shield of top metal completely covers the capacitive
DAC array. The area of the Smart-DEM block is 260×260 µm2 , only 6% of the active area.
The chip was packaged in a 48-pin ceramic quad flat pack (CQFP). Custom 4-layer printed circuit
boards (PCBs) were designed to measure the 48-pin CQFP prototype, which includes a mother board
and a daughter board. Fig. 5.14 (a) shows the top layer of the mother board designed in Altium
software, while Fig. 5.14 (b) illustrates the fabricated board with components soldered. In order to
minimize interferences, the mother board contains 3 different power supplies, namely VDDA (3.3 V
for analog circuits), VDDD33 (3.3 V for multi-phase clock generator) and VDDD15 (1.5 V for Smart-
DEM block). With regard to the usage of 4 layers on the mother board, signals are routed on the top
layer and bottom layer. The power plane is on the top layer for VDDA. The remaining 3 layers are used
for ground plane. Since there are only serveral connections of the digital power supplies (VDDD33
and VDDD15), they are also routed on the top layer. Meanwhile, the input clocks φsdem in , φrst in and
φchp in are routed on the third layer to reduce the interferences, because the 2 adjacent layers are mostly
covered by ground signal. The main functions of the mother board are listed below: 1) providing 3
different power supplies and ground; 2) generating adjustable voltage references and current sources;
3) provides interfaces for input signals (Vin , φsdem , φrst and φchp ) and digital outputs (Dout ). The
76 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

SDEM CLOCK GEN

LEV SHIFTER
1st OA
2nd OA
+BIAS
+ BIAS
+ DAC

FLASH ADCs

Figure 5.13 PVSMARTDEM chip microphotograph.

(a) (b)

Figure 5.14 (a) Top layer of the mother board in Altium; (b) Fabricated 4-layer test board with components
soldered.

daughter board, however, employs a 48-pin socket to hold the chip, allowing fast replacement of chips
during measurement. Fig. 5.15 (a) shows the top layer of the daughter board in Altium software.
Since the distance between adjacent pins is very small, all the 4 layers are used for routing the signals
 EXPERIMENTAL RESULTS 77

(a) (b)

Figure 5.15 (a) Top layer of the daughter board in Altium; (b) Fabricated daughter board with 48-pin socket.

9V Battery

Logic Analyzer
PCB and Test Chip
Power Supply

Signal Generator

Clock Generator PC (Matlab)

Figure 5.16 Measurement setup block diagram.

(include 3 power supplies and 1 ground). Fig. 5.15 (b) illustrates the fabricated daughter board with
the 48-pin socket.
Fig. 5.16 shows the block diagram of the measurement setup. The PCBs together with the chip are
powered by a 8 V power supply, which is used by the components on the mother board to generate 3
power supplies mentioned previously. Since the analog sampling frequency of the chip is 10 kHz, a
fully differential input signal with a maximum bandwidth 5 kHz is provided by an audio precision
signal generator. Meanwhile, the master clock φsdem which runs 32X of the analong sampling
frequency (2.56 MHz) and chopping clock phase φchp are produced by a clock generator. A 9 V
battery pack is utilized to produce low noise common mode voltage 1.65 V and 2 reference voltages
3.15 V and 0.15 V. The logic analyzer collects the digital output Dout , the main analog sampling clock
78 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

Figure 5.17 Measurement setup in laboratory.

φ1 and the internal reset phase φrst and these signals are then sent to a PC for data processing in Matlab
software. Fig. 5.17 shows the measurement setup with various instruments in laboratory.

5.4.2 Measurement Results

1200
SDEM Enabled and One Step Chopping
Mean = 0.85 LSB
Std Deviation = 0.86 LSB
1000
SDEM Enabled
Mean = 155.7 LSB
Std Deviation = 0.87 LSB
800
Count

600
SDEM Disabled
Mean = 160.8 LSB
Std Deviation = 1.58 LSB
400

200

0
-1 0 1 2 3 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
Output [LSB@18 bit]

Figure 5.18 Histograms of repeated measures with shorted inputs.

 EXPERIMENTAL RESULTS 79

0
Power Spectral Density [dB]
−20
fin = 833.3 Hz With SDEM
Without SDEM
−40 -63 dB FFT with 2048 Points

−60 -83 dB
-92 dB
−80
-115 dB
−100

−120

−140

−160
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
Power Spectral Density [dB]

−20 With SDEM fin = 4.135 kHz

Without SDEM
−40 FFT with 2048 Points -61 dB

−60 -81 dB
-90 dB
−80 -105 dB
−100

−120

−140

−160
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency [Hz]

Figure 5.19 Measured output spectra.

Fig. 5.18 gives histograms of 2048 repeated measurements on the same part with zero input. The
three histograms are for Smart-DEM block disabled, Smart-DEM enabled, and Smart-DEM enabled
plus one step chopping at K = 180. The standard deviation of the histograms measures the input
referred noise voltage. It is 1.58 LSB (18 µV) and 0.87 LSB (10 µV) without and with Smart-DEM.
Indeed, mismatch increases the inaccuracy. The mean of the histogram measures the input offset (160.8
LSB = 1.84 mV and 155.7 LSB = 1.78 mV, respectively). Again, the mismatch causes the difference.
The one step chopping at K = 180 leads to α1 = 16.1 × 103 ; the residual offset becomes 0.85 LSB
(9.7 µV). The result indirectly estimates a -2.42 mV offset for the second op-amp.
Fig. 5.19 shows the converter output spectra (FFT with 2048 points) with 2dBF S sine waves at
833.3 Hz and 4.135 kHz, respectively, with and without SDEM. With SDEM and low frequency, the
measured SNDR is 105 dB, equivalent to 17.15 bit. The SNDR at Nyquist drops by 1.3 dB with a loss
of 0.22 bit. Third harmonic distortion dominates the SFDR: 92 dB with low frequency signal and 90
dB when the signal is close to the Nyquist frequency. The fifth harmonic is well below the third one in
both cases. As Fig. 5.19 shows, the SNDR value drops to 82 dB without Smart-DEM and harmonics
are significant.
Fig. 5.20 illustrates the DNL obtained with the sine wave histogram method and an input sine wave
of 50 − mVpp . The limited explored interval results from the memory of the instrument (8 Mb). The
measured DNL within the [−0.8, 1] LSB range confirms the value of measured SNDR.
The measured power consumption of the modulator is about 200 µW for the analog part and 80 µW
for the digital part. The achieved F OMS is 177.5 dB following the Schreiers formula, while it is equal
to 190 fJ/conv-step when using the Waldens expression (F OMW ).
80 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

Differential Non-Linearity
1
0.8
0.6
0.4
LSB @18 bit

0.2
0
−0.2
−0.4
−0.6
−0.8
−1
-2000 -1500 -1000 -500 0 500 1000 1500 2000
Code

Figure 5.20 Measured DNL.

Table 5.2 Performance Comparison between proposed incremental ADC with state of the art.

This ISSCC2013 ISSCC2013 ANALOG INTEGR JSSC2010 JSSC2005

Work [7] [8] CIRC S.[4] [9] [3]

Year 2013 2013 2013 2012 2010 2006

BW (Hz) 5 · 103 12.5 667 1 · 103 500 · 103 7.5

3 3 3 6
FS (Hz) 10 · 10 25 1.333 · 10 2 · 10 1 · 10 15

SNDR (dB) 105 119.8 81.9 110.7 86.3 123

Power (mW) 0.28 6.3 · 10−3 19.9 · 10−3 6 38.1 0.6

VDD (V) 3.3 1.8 1.0 3.3 1.8 2.7-5.0

Technology (µm) 0.5-0.18 0.16 0.16 0.6-0.18 0.18 0.6

FOMW (fJ/conv-step) 192.6 314.8 1475.7 5722 1460 9537

FOMS (dB) 177.5 182.7 157.1 162.8 160.3 166.4

5.4.3 Performance Comparison

Tab. 5.2 summarizes performances of the proposed second-order incremental ADC and state of the
art counterparts. As seen in Tab. 5.2, the obtained F OMW and F OMS can be ranked among the
best of the selected incremental ADCs. The reason that the proposed modulator achieved good power
efficiency, in the first place, is the significant enhancement of conversion efficiency and the reduction
of analog power dissipation due to multi-bit quantization. Although a Smart-DEM block is introduced,
its power consumption can be quite limited when a low digital power supply is utilized. Secondly, the
17.15-bit resolution over a 5 kHz bandwidth benefits the power efficiency. When targeting to 20-bit
or more resolution, incremental modulators suffer from more stringent requirements on the kT/C noise
limitation and other analog specifications, such as incremental ADCs reported in [7], [4] and [3]. The
 EXPERIMENTAL RESULTS 81

second-order incremental modulator presented in [9], however, achieved 86.3 dB SNDR over a 0.5
MHz bandwidth. According to the best of author’s knowledge, this is the highest bandwidth attained
by incremental modulators. Under such a situation, the power efficiency is degraded and the obtained
F OMW is 1.46 pF/conv-step. Since the proposed modulator aims at 18-bit resolution (measured
17.15-bit) with 5 kHz bandwidth, these specifications are relatively low compared with the values
aforementioned, hence, they are good for incremental modulators to achieve high power efficiency.
82 A 17-BIT INCREMENTAL A/D CONVERTER: DESIGN AND IMPLEMENTATION

REFERENCES

1. J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta-Sigma ADC

Topology”, IET Electronics Letters, vol. 37, issue 12, pp. 737-738, Jun. 2001.
2. R.S. Assaad and J. Silva-Martinez, “The Recycling Folded Cascode: A General Enhancement of the Folded
Cascode Amplifier”, IEEE J. of Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sept. 2009.
3. V. Quiquempoix et al., “A low-power 22-bit incremental ADC”, IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1562-1571, May 2005.
4. A. Agnes, E. Bonizzoni, and F. Maloberti, “High-resolution multi-bit second-order incremental converter
with 1.5-µV residual offset and 94-dB SFDR”, Analog Integrated Circuits and Signal Processing, Springer,
vol. 72, pp. 531-539, 2012.
5. A. Pena-Perez, E. Bonizzoni and F. Maloberti, “A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp
Third-Order Σ∆ Modulator”, IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2107-2118, Sept. 2012.
6. Ivano Galdi et al., “40 MHz IF 1 MHz Bandwidth Two-Path Bandpass Σ∆ Modulator with 72 dB DR
Consuming 16 mW”, IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1648-1656, Jul. 2008.
7. Youngcheol Chae, Kamran Souri and Kofi A.A. Makinwa, “A 6.3µW 20b incremental zoom-ADC with 6ppm
INL and 1µV offset”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.
276-277, Feb. 2013.
8. Chao Chen, Zhichao Tan, Michiel A. P. Pertijs, “A 1V 14b Self-Timed Zero-Crossing-Based Incremental Σ∆
ADC”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 274-275, Feb.
2013.
9. Ali Agah et al., “A high-resolution low-power incremental Σ∆ ADC with extended range for biosensor
arrays”, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1099-1110, Jun. 2010.
CHAPTER 6

A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D

CONVERTER

This chapter describes a 12-bit 2-stage Σ∆ ADC implemented with single op-amp. The first stage
consists of a 3-bit ADC and DAC, which transforms the input to a coarse digital code together with
a quantization error. This quantization error then enters a second-order Σ∆ stage and the output is a
fine digital code. The final digital output is the combination of both the coarse part and the fine digital
code. The structure benefits from the single op-amp implementation which leads to a second-order
noise shaping. The output swing of the op-amp is significantly reduced due to the first-stage, thus,
allowing to spare power. With 0.18 µm CMOS technology, simulation results shows that the proposed
structure obtains more than 12-bit resolution over a 2 MHz bandwidth. The power consumption is 1.7
mW and the corresponding Figure of Merit (FOMW ) is 104 fJ/conv-step.

6.1 General Considerations

As already mentioned in Chapter 2, Σ∆Ms are always used to achieve high resolution A/D
conversion without the need of precisely matched analog components. According to [1] [2], DT
Σ∆Ms are good candidates to attain medium-to-high resolution for a bandwidth less than 2MHz.
While the CT counterparts are more appropriate to obtain low-to-medium resolution with more than
10 MHz bandwidth. Thus, the starting point of the research of Σ∆Ms is to familiarize with the target
specifications, which are listed again as follows:
I Resolution: 12-bit
Multi-Bit A/D Converters with High Resolution and Low-Power. 83
By Yao Liu
84 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

I Bandwidth: 2 MHz
I Power Consumption: ≤2 mW
In order to meet the above specifications, Σ∆ architectures with DT fashion are taken into
consideration. The basic design parameters of Σ∆M s are the order of the structure L, resolution
of the quantizer qb and oversampling ratio (OSR). For stable Σ∆ schemes with denominator equal to 1
in the STF and NFT, the maximum achievable SNR in terms of those parameters can be estimated by
(2.13), which is rewritten here for readers’ convenience
π 2L
SN RLord,Σ∆ = 1.78 + 6.02qb − 10log + 3.01(2L + 1)log2 (OSR) (6.1)
2L + 1
Using (6.1), we can calculate the corresponding design parameters in order to meet the specifications
listed above. Tab. 6.1 shows the possible combinations of design parameters where 2 ≤ L ≤ 3,
3 ≤ bq ≤ 5 and 8 ≤ OSR ≤ 32.

Table 6.1 Achievable SNR in terms of L, qb and OSR.

L qb OSR Fs SNR ENOB

2 3 8 32 MHz 52.09 dB 8.36-bit

2 3 16 64 MHz 67.14 dB 10.86-bit
2 3 32 128 MHz 82.19 dB 13.36-bit
2 4 8 32 MHz 58.11 dB 9.36-bit
2 4 16 64 MHz 73.16 dB 11.86-bit
2 4 32 128 MHz 88.21 dB 14.36-bit
2 5 8 32 MHz 64.13 dB 10.36-bit
2 5 16 64 MHz 79.18 dB 12.86-bit
2 5 32 128 MHz 94.23 dB 15.36-bit
3 3 8 32 MHz 61.67 dB 9.95-bit
3 3 16 64 MHz 82.74 dB 13.45-bit
3 3 32 128 MHz 103.81 dB 16.95-bit
3 4 8 32 MHz 67.69 dB 10.95-bit
3 4 16 64 MHz 88.76 dB 14.45-bit
3 4 32 128 MHz 109.83 dB 17.95-bit
3 5 8 32 MHz 73.71 dB 11.95-bit
3 5 16 64 MHz 94.78 dB 15.45-bit
3 5 32 128 MHz 115.85 dB 18.95-bit

Since the target is to achieve 12-bit resolution with minimum power consumption, the design
strategy is to avoid using high-order Σ∆ structures and to adopt relatively low sampling frequency.
The multi-bit quantization and DAC can be employed. In this case, the chosen architecture should
guarantee a minimum input range of the quantizer in order to reduce the number of comparators.
Another problem related to the multi-bit quantization is the non-linearity of the DAC. Generally for 12-
bit resolution, the non-linearity of multi-bit DAC does not have a significant impact of the modulator’s
performance. However, extensive simulations are still needed to ensure the achievable resolution.
On the basis of above analysis, certain architectures and design parameters can be chosen from Tab.
6.1. The preferable choices are: (1) L = 2, qb = 5 and OSR=16; (2) L = 3, qb = 5 and OSR=8. In
 GENERAL CONSIDERATIONS 85

the former case, the Σ∆M benefits from a low order loop filter and a moderate OSR. The resolution
of quantizer is affordable since the maximum number of comparators used is 2qb = 32. In case 2, the
third-order loop filter benefits the Σ∆M from a low OSR=8, which corresponds to 32 MHz sampling
frequency for BW = 2 MHz. Meanwhile, the resolution of the quantizer is also 5. In both cases, by
using effective Σ∆ architectures, the input range of the quantizer can be significantly reduced, giving
rise to reduction of comparators.

ɛq
Vin Vx Dout


DAC
H(z)

Vout
-1 Z-1 

Figure 6.1 First-order Σ∆ ADC block diagram.

With regard to the selection of Σ∆ architectures, the key point is to reduce the power consumption
while achieve the target performance. One effective way to minimize the power dissipation, as
discussed in Chapter 2, is to reduce the number of op-amps used in the loop-filter. The technique
proposed here is different from the integrator multiplexing [3] or double-sampling [4] and it can
obtain high-order NTF with single op-amp. We begin the discussion with the first-order Σ∆ structure
illustrated in Fig. 6.1, where the quantization error q can be estimated by the difference between Vout
(analog version of Dout ) and VX . After one unit time delay, the quantization error is added with Vin
and the summation result is VX . To have a better understanding of this structure, the transfer function
is expressed in z-domain as follows

Dout (z) = Vin (z) + (1 − z −1 )q (z) (6.2)

−1
where N T F (z) = 1 − z , which is a conventional first-order high-pass filter.
The scheme plotted in Fig. 6.1 can be easily extended to higher-order Σ∆ architectures, by
modifying the transfer function inside the dash box. Using the similar method, a second-order Σ∆
structure is shown in Fig. 6.2. Notice that the difference of this scheme with the one plotted in 6.1 is
H(z), which can be represented by

H(z) = z −2 − 2z −1 (6.3)
Consequently, the transfer function of the second-order Σ∆M can be described as
Dout (z) = Vin (z) + (1 − z −1 )2 q (z) (6.4)
where the quantization error q is shaped by a second-order high-pass NTF. According to the design
parameters chosen before (L = 2, qb = 5 and OSR=16), this second-order Σ∆M should obtain 12.86-
bit resolution. Behavioural-level simulations demonstrate the expected performance as plotted in Fig.
86 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

ɛq
Vin Vx Dout


DAC

-2 Z-1
Vout
 

1 Z-2

Figure 6.2 Second-order Σ∆ ADC block diagram.

6.3. A -3 dBF S sinusoid waveform at normalized frequency 0.0021 is applied at Vin and the PSD of
Dout shows that the achieved SNDR is 76.7 dB. The result is almost ideal compared with the theoretic
value listed in Tab. 6.1.
0
-1 0 S N D R = 7 6 .7 d B
-2 0 E N O B = 1 2 .4 5 b its
-3 0
-4 0
-5 0
-6 0
P S D (d B )

-7 0
-8 0
-9 0
- 1 0 0
- 1 1 0
- 1 2 0
- 1 3 0
- 1 4 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 6.3 PSD (8096-point FFT) of Dout of the second-order Σ∆ ADC with ideal 5-bit DAC. The input signal
is a sinusoid waveform at normalized frequency 0.0021 whose amplitude is -3 dBF S . The OSR is 16.

Similarly, a third-order Σ∆ architecture can be obtained. Fig. 6.4 illustrates the block diagram of a
third-order scheme whose H(z) can be depicted as
H(z) = −z −3 + 3z −2 − 3z −1 (6.5)
It is evident that the quantization noise is shaped by a third-order high-pass NTF, since (6.6) holds
Dout (z) = Vin (z) + (1 − z −1 )3 q (z) (6.6)
 GENERAL CONSIDERATIONS 87

Summation Node ɛq
Vin Vx Dout


DAC
-3 Z-1

Vout
 3 Z-2 

-1 Z-3

Figure 6.4 Third-order Σ∆ ADC block diagram.

In general, the number of integrators inside Σ∆ loop filter determines the order of the scheme.
Nonetheless, architectures shown in Fig. 6.2 and Fig. 6.4 are able to realize second-order and
third-order NTF without integrator. Compared with conventional Σ∆Ms, the aforementioned Σ∆
architectures are of significant advantages. However, there are a few problems which can not be
neglected.
The first issue is the implementation of an accurate summation node. Let us take the third-order
structure plotted in Fig. 6.4 as an example. The main operation performed by this structure is the
summation of Vin with different versions (delay and coefficient) of q . Intuitively, this summation
function should be with high accuracy. Otherwise, NTF may change due to the inaccuracy of
summation and a good third-order noise shaping cannot be guaranteed. One way to realize the add
function is to use op-amp together with SC circuits. Fig. 6.5 shows a conventional OTA-based analog
adder. In phase φ1 , V1 and V2 charges C1 and C2 . Meanwhile, φrst reset the output of op-amp VX .
Then during φ2 , the charge on C1 and C2 is transferred to C3 . According to this operation flow, an
ideal transfer function can be derived
C1 C2
V3 (z) = V1 (z) + V2 (z) (6.7)
C3 C3
Consider the op-amp with finite DC gain A0 while the bandwidth and slew rate are unlimited. With
mathematical calculation, a more precise transfer function is
C1 C2
V3 (z) = 1 V1 (z) + 1 V2 (z) (6.8)
C3 + A0 (C1 + C2 + C3 ) C3 + A0 (C1 + C2 + C3 )
Using (6.8), simulations show that for third-order Σ∆ structure, the required A0 is at least 80 dB. In
reality, because of the limitation on bandwidth and slew rate, the desired A0 may even higher than the
value mentioned above.
To achieve an accurate summation node, the bandwidth of op-amp should also be taken into
consideration. In Fig. 6.5, supposing the branch of V2 is disabled and A0 is infinite, the transfer
function from V1 to V3 in time domain can be expressed as
T −β·T 1
V3 (nT + T ) = V1 (nT + )(1 − e 2·τ0 ); τ0 = (6.9)
2 2 · π · GBW
88 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

Φ1 C1 Φ2
V1 Φrst
Φ2 Φ1
C3
Φ1 C2 Φ2
V2 V3
A0
Φ2 Φ1

Φ1,Φrst
Φ2
nT (n+1)T

Figure 6.5 Typical OTA-based analog summation block.

where β = C3 /(C1 + C3 ) is the feedback factor and GBW is the close loop gain bandwidth product
of the op-amp. As seen in (6.9), when a fixed GBW is given, the operation speed of the circuit is
determined by the feedback factor β. For the first-order structure illustrated in Fig. 6.1, the calculated
β1ord is 1/3. With regard to the second-order and third-order architectures, corresponding feedback
factor reduces to 1/5 and 1/9. Hence, in order to obtain the same accuracy of dynamic response as that
of the first-order architecture, GBW2ord and GBW3ord should be 1.67 and 3 times of GBW1ord .

0
-1 0 S N D R = 7 3 .4 d B
-2 0 E N O B = 1 1 .9 b its
-3 0
-4 0
-5 0
-6 0
P S D (d B )

-7 0
-8 0
-9 0
- 1 0 0
- 1 1 0
- 1 2 0
- 1 3 0
- 1 4 0
1 E -3 0 .0 1 0 .1
N o rm a liz e d F re q u e n c y

Figure 6.6 PSD (8096-point FFT) with σ = 0.1% mismatch for three 5-bit DACs. The input signal is a sinusoid
waveform at normalized frequency 0.0021 whose amplitude is -3 dBF S . The OSR is 16.
 PROPOSED SCHEME 89

Secondly, the voltage swing of VX is large since it contains a component equal to Vin . According
to (6.4) and (6.6), the transfer function from Vin to VX of the second-order architecture is

VX = Vin (z) + (z −2 − 2z −1 )q (z) (6.10)

while for the third-order scheme

VX = Vin (z) − (z −3 − 3z −2 + 3z −1 )q (z) (6.11)

If the summation node were implemented with op-amp, the large output swing would result in
considerable dynamic error due to the limitations on slew rate and bandwidth. Moreover, since VX
is applied directly to the input of the quantizer, larger VX means more comparators should be utilized
in the scheme and thus more power consumption is required.
The third problem, as mentioned before, comes from the non-linearity of the multi-bit DAC. To
demonstrate this point, the third-order Σ∆ scheme illustrated in Fig. 6.4 is selected as our experimental
architecture. Design parameters bq = 5 and OSR=16 are chosen. Ideally, the achievable SNDR is
92.3 dB (ENOB=15.04-bit) when a −3dBF S sinusoid waveform with normalized frequency 0.0021 is
applied to Vin . Fig. 6.6 shows the PSD (8096-point FFT) under σ = 0.1% mismatch of the 5-bit DAC.
The achieved SNDR is 73.4 dB (ENOB=11.9-bit) and the degradation of performance is 3.14-bit.

6.2 Proposed Scheme

Dout
ɛq1 ɛq2 

Vin Vx Dout2
DAC1 
Dout1
3-bit 5-bit

DAC2

-2 Z-1

 

1 Z-2

Figure 6.7 Proposed 2-stage Σ∆ ADC block diagram (without integrator).

Fig. 6.7 illustrates the block diagram of the proposed 2-stage Σ∆ ADC. The first stage uses a 3-
bit quantizer to digitize Vin and generates a coarse digital output Dout1 . The equivalent input of the
second stage, q1 , goes through a second-order Σ∆ structure which is equal to the scheme plotted in
Fig. 6.2. The quantization noise of the second stage q2 is shaped by a second-order NTF and the
digital output is Dout2 . The combination of Dout1 and Dout2 generates the final digital output of the
modulator Dout . According to the operation principles, the ideal transfer function can be derived as
90 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

Dout (z) = Vin (z) − q2 (z)(1 − z −1 )2 (6.12)

To meet target specifications, design parameters qb = 5 and OSR=16 are selected. Based on Tab.
6.1, the proposed 0+2 Σ∆ architecture can obtain an theoretic 12.86-bit resolution. This architecture
avoid using the third-order scheme shown in Fig. 6.4 because the requirement on summation node
is very difficult to achieve. Moreover, the third-order architecture demands for a strict matching
accuracy about σ = 0.05% between unity elements in DAC. With regard to the proposed second-
order architecture illustrated in Fig. 6.7, the input swing of Σ∆ stage is significantly reduced with the
help of the first stage, giving rise to low-power design. The OSR is 16 for a 2 MHz signal bandwidth.
The corresponding sampling frequency FS is 64 MHz, which is quite affordable considering the budget
of the total power consumption of the modulator.

0 .2 5

0 .2 0

0 .1 5

0 .1 0
S w in g o n V x (V re f)

0 .0 5

0 .0 0

-0 .0 5

-0 .1 0

-0 .1 5

-0 .2 0

-0 .2 5
0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 1 8 0 0 2 0 0 0
N (C lo c k C y c le s )

Figure 6.8 Voltage swing on VX node when −3dBF S sinusoid input at normalized frequency 0.0021 is given.

A few practical design issues related to the proposed second-order architecture are discussed below.
Firstly, let us investigate the voltage swing on VX , since it affects both the summation accuracy
and the power consumption. Fig. 6.8 illustrates the waveform on VX given −3dBF S sinusoid input
at normalized frequency 0.0021. It can be noticed that the voltage swing on VX is limited within
0.2Vref . With this value, the number of comparators used in the 5-bit quantizer can be reduced to 8.
Thus, the total number of comparators in the modulator is 16. For the op-amp based summation node,
low swing loosens the requirements on slew rate and bandwidth and benefits the modulator from low
power consumption.
In terms of summation node, we use op-amp based analog adder and related specifica-tions of op-
amp are studied. When an op-amp with DC gain A0 is used, the derived inaccuracy of the summation
node is 5/(A0 + 5). Simulations show that the minimum required DC gain to attain 12-bit resolution
is 80 dB. Since a 0.18 µm CMOS technology is utilized in this design, 80 dB DC gain is not difficult
to achieve. The feedback factor β2ord of the op-amp is 1/5, which still significantly affects the settling
speed of the integrator. As specified later, with certain techniques on circuit implementation, β2ord can
be effectively reduced to 1/3 and thus the settling behavioural of the op-amp is improved.
For the non-linearity of DACs, similar simulations are also performed to explore the feasible range
of mismatch. Simulation results show that for DAC1, the mismatch is not sensitive. Even σ = 1.0%
 PROPOSED SCHEME 91

mismatch can give rise to good conversion result. However, the non-linearity of DAC2 is very critical.
Behavioural level simulation results indicate that the mismatch should be limited within σ = 0.2%.
The circuit level implementation of the proposed second-order Σ∆M starts from the estimation of
the minimum input capacitance. In this design, we use a 0.18µm CMOS technology with 1.8 V analog
power supply. According to Section 3.1, the calculated CS with design parameters VF S = 1.8V ,
OSR=16 and EN OB = 12 is 16 fF, which means that the kT/C noise is not a dominant limitation.

Table 6.2 Phases and Operations.

φ1 φ2 φq

q1 (z) Charge Inject −

z −2 q2 (z) − Inject Charge
−2z −1 q2 (z) Inject − Charge

As mentioned before, the feedback factor is 1/5 for the second-order structure proposed in Fig. 6.7.
Notice the summation operation can be divided into two parts, the first part is q1 (z) and the z −2 q2 (z).
The other part is −2z −1 q2 (z). To improve the feedback factor, the analong sampling clock period is
divided into 3 equal parts, namely φ1 , φ2 and φq . The operations of charge and injection of each branch
are shown in Tab. 6.2. In φ1 , q1 (z) charges the input sampling capacitor while −2z −1 q2 (z) injects
its charge on the op-amp. Then during φ2 , both q1 (z) and z −2 q2 (z) inject the charge on the op-amp.
After φ1 and φ2 , the new summation value VX is ready. In φq , this value is used to charge the 2 analog
delay lines which will be utilized in the next clock period. At the same time, the quantizer compares
VX with references and determines digital output Dout2 . In this case, β2ord can be improved to 1/3.
However, the drawback is the time for each operation is 2/3 of that when only 2 equal clock phases are
used.

Dout


DAC 2 Z-1

 1 Z-1

ɛq1 ɛq2
Vin 1 Vx
DAC1 
Dout1 1 ̶ Z-1 Dout2
3-bit 5-bit

DAC2

Vout2
1 Z-2 

Figure 6.9 Proposed 2-stage Σ∆ ADC block diagram (with integrator).

92 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

D Q Dout1
Φ1 Φ1
Clk

Q
Vinp
D Q D1p
Vinn Clk

ADC1 Φ2 Q D1n
3-bit
D Q D1p
X8 32Cu Clk

Φ1 Q D1n
Φ1 4Cu Φ2 VYp D Q D21p
Vinp VXn Φ1 Clk

A0
VXp Φ21 Q D21n
Φ2 Φ1 Dout2
D Q D22p
VXn Φ22
Clk

D22n
ADC2 Q

D1p 5-bit

VXn
X8 X8 X8
Φq 2Cu Φ1 Φq1 Cu Φ21 Φq2 Cu Φ22

Φ1 Φq VYp Φ21 Φq1 VYn Φ22 Φq2 VYn

D1p D21p D22p

Φq 16Cu Φ1 Φq1 24Cu Φ21 Φq2 24Cu Φ22

Φ1 Φq VYp Φ21 Φq1 VYn Φ22 Φq2 VYn

z-1{VX(z)-2Dout2(z)} z-2ɛq2(z)

Φ1
Φ2
Φq
Φ21
Φ22
Φq1
Φq2

Figure 6.10 Proposed 2-stage Σ∆ ADC schematic diagram.

The other important aspect is that, since an op-amp is used to implement the summation node,
there should be an additional clock phase to reset the output of the op-amp. This extra phase needs
 PROPOSED SCHEME 93

considerable time to discharge completely so that it does not disturb the following operation. Since
FS is 64 MHz and the analog clock period is 15.625 ns. It is not wise to spare a portion of the time
to discharge the op-amp. In order to solve this problem, the branch of −2z −1 q2 (z) is divided into 2
parts, which can be described as

−2z −1 q2 (z) = − 2z −1 {Vout2 (z) − VX (z)}

(6.13)
=VX (z)z −1 + {VX (z)−1 − 2Vout2 (z)}z −1
From (6.13), we can observe that the summation node can be implemented with an integrator
without reset. This is because at the end of nth clock period, VX (n) is calculated. Meanwhile, the
signal −2q2 (n) contains a component equal to VX (n), which will be used by the summation operation
in the (n+1)th clock period. Thus, VX (n) can be reused and does not need to be reset. Meanwhile, the
feedback signal -2q2 (n) can be replaced with VX (n) − 2Vout2 (n). In this case, the transfer function
of the Σ∆M remains the same and the reset issue is solved.
With the above considerations, the modified architecture of the proposed scheme is illustrated in
Fig. 6.9. Interestingly, the op-amp is used as an integrator for −2z −1 q2 (z) branch. While for the
other 2 branches, the op-amp functions as an analog adder. Under such a configuration, the feedback
factor β2ord for the operations in φ1 and φ2 are 1/2 and 1/3, respectively.

VDD
VCMFB
M1 M2
VY1 VY2

M3 M4
An
VOUT- VOUT+
Ap
M5 M6

VX1 VX2
VIN+ M7 M8 VIN-

VB2 M9

VSS

Figure 6.11 Main operational amplifier schematic diagram.

Fig. 6.10 shows the single-ended schematic diagram of the proposed second-order ADC. The circuit
consists of one op-amp, 2 quantizers, 2 DACs and related digital controls. The ADC1 is 3-bit and
contains 8 comparators. The swing of the op-amp is less than 0.2Vref , thus, only 8 comparators are
required in ADC2. The unity capacitor Cu (MIM type) is 7.5 fF. The input sampling capacitor CS is
94 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

32Cu which is equal to 240 fF. The combination of digital output Dout1 and Dout2 generates the final
output Dout , which is not shown in Fig. 6.10. The SC circuits are used to implement the analog delay
lines, which are under the control of various clock phases. As seen in Fig. 6.10, φ1 , φ2 and φq are the
3 clock phases with the equal duty ratio as mentioned before. Meanwhile, φ21 and φ22 are the divided
by 2 clocks of φ2 . Similarly, φq1 and φq2 and the divided by 2 phases of φq . These 4 clock signals,
however, are used to control 2 sets of capacitors in order to generate the z −2 q2 (z) term.

6.3 Building Blocks

In this section, analog and digital building blocks used in the proposed 0+2 Σ∆M are described.
Firstly, a high gain op-amp with large bandwidth is introduced, which is followed by the design of a
low-power comparator. The 3-phase non-overlap clock generator is explained in the last part.

6.3.1 Gain-Boost Operational Amplifier

VDD

VB2
M10 M11

M6 M9
VCM VCM
VOUT- VOUT+
VIN+ VIN-
M4 M1 M2 M8
VCM VCM
M3 VB1 M7
VCMFB VCMFB

VSS

Figure 6.12 Gain booster An schematic diagram.

With less than 0.2Vref output swing, the conventional telescopic op-amp is employed which is
illustrated in Fig. 6.11. As seen in Fig. 6.11, M7-M8 are the NMOS input pair while M1,M2 and M9
form the current sources. Transistors M3-M6 together with An and Ap are adopted to boost DC gain of
the main op-amp. An is a fully differential folded-cascode op-amp with NMOS transistor pair as input,
as illustrated in Fig. 6.12. On the other hand, Ap is a fully differential folded cascode op-amp using
PMOS transistors as input, which is shown in Fig. 6.13. The reason that 2 types of gain boosters are
used is that, the voltages VX1 and VX2 (VDS9 + VDS7 ) are not high enough to drive NMOS transistors
while VY 1 and VY 2 (VDD − VDS1 ) are not low enough to drive PMOS transistors. Hence, gain booster
Ap is used for VX1 and VX2 and regarding VY 1 and VY 2 , gain booster An is adopted.
 BUILDING BLOCKS 95

VDD
VB1
M7 VCMFB M1 VCMFB M10

VIN+ VIN-
M2 M3
M8 VCM VCM M11
VOUT- VOUT+
M9 VCM VCM M12

VB2
M5 M6

VSS

Figure 6.13 Gain booster Ap schematic diagram.

As reported in [5], the restriction on the GBW of gain boosters (GBWA ) in order to ensure fast
settling is
β2ord · GBWM < GBWA < ωp2 (6.14)
where GBWM and ωp2 are the close loop GBW and the position of the second pole of the main
op-amp, respectively.
With above considerations, the telescopic op-amp shown in Fig. 6.11 together with Ap and An is
implemented with 0.18µm CMOS technology using 1.8 V analog power supply. The simulated DC
gain and GBW under typical condition of Ap are 58.6 dB and 520 MHz. In terms of An , the DC
gain and GBW are 56.7 dB and 474 MHz. With the help of the gain boosters, simulation results show
the DC gain and GBW of the main op-amp is 102 dB and 1.2 GHz (480 fF load). The total power
consumption of the op-amp is 1.3 mW (including the gain boosters).

6.3.2 Low-Power Comparator

The structure of the comparator used in this design is the same as that adopted in previous chip, which
is replotted in Fig. 6.14. The total bias current of a comparator is 4 µA. The power consumption of
2 quantizers is around 0.12 mW. Simulation results under typical conditions show that the DC gain of
the pre amplifier stage is 10.2 dB and the delay of the comparator is 350 ps. The sensitivity is less than
1 mV, which is guaranteed by intensive simulations.

6.3.3 Non-Overlap Clock with Three Phases

As mentioned previously, this design employs 3 non-overlap phases with equal occupation, which
are φ1 , φ2 and φq . Fig. 6.15 shows the schematic diagram of the used 3 non-overlap clock phases
generator. The working principles are as below: at the beginning of the circuit startup, D1,2,3 are reset
to 0 (not shown in Fig. 6.15). When the DFFs detect the first positive edge of φin , the outputs of DFFs
are updated which means D1 = 1, D2 = 0 and D3 = 0. Notice that during the normal operation of the
96 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

VDD
VB VB
M1 M2 M10 M11
VCLK VCLK
M12 M13
VREF- VREF+
VIN+ VIN-
M3 M4 M5 M6 VOUT+ VOUT-
M14 M15
VX VY VCLK VCLK
M16 M17
VCLK

VX M18 M19 VY
M7 M8 M9

VSS

Figure 6.14 Two stage comparator schematic diagram.

D1
D Q
D1

D2
Clk

Q
Φ1

D2
Φin D Q
Clk

Q
Φ2
D3
D Q
Clk

Q
Φq

Φin
Φ1
Φ2
Φq

Figure 6.15 Three non-overlap clock phases generator.

phase generator, there is only one high logic in D1,2,3 while the other 2 remain low. In the following
clock periods, the high logic 1 is passed in a cyclic order from D1 to D3 and when D3 is equal to 1,
the high logic will be passed from D3 to D1 again. The non-overlap property of 3 clock phases are
ensured by the logic in the red dash box. For example, suppose in nth clock period, D1 = φ1 = 1 and
D2,3 = φ2,3 = 0. In the (n + 1)th clock period, values of DFFs change to D1,3 = 0 and D2 = 1.
However, when φ1 becomes to 0, φ2 cannot change immediately because there is delay from φ1 to φ2 .
In this case, the non-overlap property of 3 clock phases are guaranteed.
 BUILDING BLOCKS 97

Figure 6.16 PVLPSD2 chip layout.

Using 0.18µm CMOS technology with 1.8 V power supply, simulation results show the transition
time of the clocks is 50 ps and the non-overlap gap between 2 adjacent phases is around 150 ps.
This value, however, is sufficient to tolerate the clock skew due to circuit imperfections in the real
circumstances.

0
-1 0 S N D R = 7 4 .5 d B
-2 0 E N O B = 1 2 .0 8 b its
-3 0
-4 0
-5 0
P S D (d B )

-6 0
-7 0
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
1 0 0 k 1 M 1 0 M
F re q u e n c y (H z )

Figure 6.17 PSD (1024-point FFT) with respect to frequency. The input signal is a sinusoid waveform at 562.5
kHz whose amplitude is -3 dBF S (BW = 2M Hz). The sampling frequency is 64 MHz and the OSR is 16.
98 A 12-BIT SINGLE OP-AMP 0+2 Σ∆ A/D CONVERTER

6.4 Simulation Results and Performance Comparison

The proposed single op-amp 0+2 Σ∆ ADC is designed in a 0.18 µm CMOS technology with 6
metal layers. Fig. 6.16 shows the layout of the full chip. The active area is 860×600 µm2 (the
chip area is 1240×970 µm2 ). The number of pads used in the chip is 32. To avoid interferences,
the power supply and ground signal for analog and digital circuits are separated. Multiple pads for
analog power supply and ground are utilized so as to reduce the related IR drop. Other pads are used
to provide different input signals (voltage and current references, analog inputs, clock and reset) and
digital outputs.

Table 6.3 Performance Comparison between proposed Σ∆ ADC with state of the art.

This ISSCC2006 ISSCC2005 ISSCC2011 ISSCC2008

Work [6] [7] [8] [9]

Year 2013 2006 2005 2011 2008

Technology (µm) 0.18 0.18 0.09 0.18 0.18

VDD (V) 1.8 1.8 1.2 1.5 0.7

Bandwidth 2 MHz 2.2 MHz 1.94 MHz 1.04 MHz 20 kHz

OSR 16 32.7 10 24 100

SNDR (dB) 74 78 63 78.2 81

Power 1.7 mW 5.1 mW 1.2 mW 2.9 mW 3.6 µW

FOMW (fJ/conv-step) 104 178.5 267.9 210 98.1

The performance of the proposed second-order Σ∆M is verified by transistor level simulations in
Cadence software. Fig. 6.17 illustrates the PSD (1024-point FFT) of Dout when a -3 dBF S sinusoid
waveform at 562.5 kHz is applied. The achieved SNDR is 74.5 dB, which is equal to 12.08-bit
resolution. The total power consumption is 1.7 mW and the corresponding F OMW is 104 fJ/conv-step.
In Tab. 6.3, performance comparison between proposed Σ∆ ADC and state of the art modulators is
given. As seen in Tab. 6.3, the Figure of Merit of the proposed modulator (simulation results) is better
than those achieved by the counterparts with comparable signal bandwidth. The ADC presented in [9]
obtained a slightly smaller F OMW which is 98.1 fJ/conv-step, however, with a very narrow bandwidth
(20 kHz) of the input signal.
 SIMULATION RESULTS AND PERFORMANCE COMPARISON 99

REFERENCES

1. Jose M. de la Rosa, “Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art
Survey”, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 58, no. 1, pp. 1-21, Jan. 2011.
2. Jose M. de la Rosa, “An Empirical and Statistical Comparison of State-of-the-Art Sigma-Delta Modulators”,
in Proc. 2013 IEEE Int. Symp. Circuits Syst.(ISCAS), pp. 825-828, May 2013.
3. C. M. Zierhofer, “Analysis of a Switched-Capacitor Second-Order Delta-Sigma Modulator Using Integrator
Multiplexing”, IEEE Transactions on Circuits and Systems-II, vol. 53, no. 8, pp. 787791, Aug. 2006.
4. P. J. Hurst and W. J. McIntyre, “Double Sampling in Switched-Capacitor Delta-Sigma A/D Converters”, in
Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), vol. 2, pp. 902-905, May 1990.
5. K. Bult and Govert J. G. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain”,
IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990.
6. Kwon, S. and Maloberti, F., “A 14mW Multi-Bit Σ∆ Modulator with 82dB SNR and 86dB DR for
ADSL2+”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 161-170,
Feb. 2006.
7. Koh, Jinseok and Choi, Yunyoung and Gomez, G., “A 66dB DR 1.2V 1.2mW single-amplifier double-
sampling Second-Order Sigma Delta ADC for WCDMA in 90nm CMOS”, in IEEE International Solid-
State Circuits Conference Digest of Technical Papers, pp. 170-591 vol. 1, Feb. 2005.
8. Maghari, N. and Moon, Un-Ku, “A third-order DT Sigma Delta modulator using noise-shaped bidirectional
single-slope quantizer”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers,
pp. 474-476, Feb. 2011.
9. Chae, Youngcheol and Lee, Inhee and Han, Gunhee, “A 0.7V 36uW 85dB-DR Audio 85-dB DR Audio
Delta-Sigma Modulator Using Class-C Inverter”, in IEEE International Solid-State Circuits Conference
Digest of Technical Papers, pp. 490-630, Feb. 2008.
CHAPTER 7

CONCLUSIONS AND FUTURE WORK

This chapter concludes the thesis. Firstly, a summary that briefly introduces the motivation and results
of the thesis is presented. Several original contributions are then explained in the next section. Finally
the future directions of incremental and Σ∆ ADCs are shortly discussed.

7.1 Summary

Targeting at high resolution and low power, this thesis explored new architectures and circuits
techniques for multi-bit incremental ADCs and Σ∆Ms. Conventional second-order and third-order
incremental modulators use 2-level quantization, which usually have a long conversion time per
sample and high power consumption due to large output swing of op-amps. Compared with 2-level
quantization, multi-bit quantization is a more convenient technique for incremental ADCs because
it reduces the output swing of op-amps, while keeps the loop stable without fractional coefficients.
The non-linearity due to the mismatch between unity elements in multi-bit DAC can be properly
compensated for with Smart-DEM algorithm. A prototype chip fabricated in a mixed 0.5-0.18 µm
CMOS technology demonstrated the proposed second-order 3-bit architecture, which obtained more
than 17-bit resolution over a 5 kHz bandwidth. For Σ∆M, since the target is to achieve 12-bit resolution
and the existing DEM techniques are able to compensate for the non-linearity of DAC, we focused on
the low-power Σ∆ architectures and design techniques. A 12-bit 0+2 Σ∆ ADC was proposed, which
uses a single op-amp to achieve second-order noise-shaping. A prototype chip was designed in a
Multi-Bit A/D Converters with High Resolution and Low-Power. 101
By Yao Liu
102 CONCLUSIONS AND FUTURE WORK

0.18 µm CMOS technology and simulation results show it can attain 12-bit resolution over 2 MHz
bandwidth.

7.2 Contributions

7.2.1 High-Order Smart-DEM Algorithm

In this thesis, a Smart-DEM algorithm for high-order incremental ADCs was proposed, which is able
to compensate for the mismatch between unity elements of multi-bit DAC. As discussed in Chapter 3,
conventional DEM methods such as DWA can not properly compensate for the mismatch, giving rise
to considerable resolution loss especially when higher order structures are used. However, the Smart-
DEM algorithm can achieve a near-ideal compensation and thus benefit high order incremental ADCs
with better conversion efficiency and reduced swing of op-amps.

7.2.2 Non-conventional Incremental Architectures

In Chapter 4, non-conventional incremental architectures are explored. These incremental ADCs adopt
digital feedforward paths to maintain loop stability as well as reduce the swing of op-amps. The use
of multi-bit quantization and DAC can help achieve high conversion efficiency for the modulators.
The only feedback path allows properly use of Smart-DEM algorithm, giving rise to a near-ideal
mismatch compensation. In this case, the obtained multi-bit incremental architectures can provide
faster conversion and consume less power than conventional modulators utilizing 2-level quantization.

7.2.3 Single Op-Amp Second-Order Σ∆ Architecture

Chapter 7 proposed a 0+2 Σ∆ architecture. The main feature of this modulator is that, the use of
single op-amp achieves second-order noise shaping. A 3-bit flash is introduced to reduce the swing of
the input of the Σ∆ stage. To improve the feedback factor of the op-amp, 3 non-overlap clocks can be
utilized. Simulation results show that the proposed architecture can meet the specifications and achieve
good power efficiency.

7.3 Future Directions

Based on the work of this thesis and recent publications, a few topics are worthy to be investigated
in the near future.

7.3.1 Multi-Bit Incremental ADC aiming for 20-Bit

To the best of the author’s knowledge, very few incremental ADCs obtained 20-bit or more resolution
[1][2]. However, The aforementioned non-conventional architectures and Smart-DEM algorithm can
be extended to achieve more than 20-bit resolution. A good design strategy is to combine second-order
or third-order incremental architecture with 4-6 bits quantizer. With regard to the Smart-DEM block,
an ultra-low power supply can be applied to significantly reduce the power consumption of the digital
 FUTURE DIRECTIONS 103

circuit. In this case, the multi-bit incremental modulator can achieve 20-bit or more resolution with
very low power dissipation.

7.3.2 Multi-Bit CT Incremental Modulator

Incremental ADCs are always implemented in DT fashion. Recently, a few CT incremental modulators
were reported in [3][4]. The benefit of CT modulators stems from relaxed requirements on slew rate
and bandwidth, giving rise to potentially better power efficiency than their counterparts. To date, only
2-level quantization is utilized in CT incremental modulators. The multi-bit CT incremental ADCs
have not been reported in the open literature yet, which is a good direction to further lower the power
dissipation of the modulator.

7.3.3 ADCs Utilizing Nanometer CMOS Technologies

As indicated in Chapter 5 and Chapter 6, op-amps employed in the 2 designs require very high DC
gain (>90 dB). However, in the nanometer CMOS technologies (≤ 65 nm), achieving such a DC
gain is very difficult. Consequently, a few techniques attempted to replace op-amps were reported
recently [5][6]. A second-order incremental ADC was reported in [5], which replaces op-amps with
gated current source (GCS) along with zero-crossing detector (ZCD). The reported resolution is 14-
bit, which is relatively low compared with 20-bit or more resolution. However, this is a good way to
obtain almost all digital incremental ADC, which has significant advantages when the utilized CMOS
technologies are scaled to 32 nm or even less. With regard to Σ∆Ms, a low-power modulator utilizing
Class-C inverters was presented in [6], which achieved very low power dissipation because it does
not consume static biasing current. Both examples discussed above indicate a good research direction
in the near future, because of the continuous scaling of the feature size and power supply of modern
CMOS technologies.
104 CONCLUSIONS AND FUTURE WORK

REFERENCES

1. V. Quiquempoix et al., “A low-power 22-bit incremental ADC”, IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1562-1571, May 2005.
2. Youngcheol Chae, Kamran Souri and Kofi A.A. Makinwa, “A 6.3µW 20b incremental zoom-ADC with 6ppm
INL and 1µV offset”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.
276-277, Feb. 2013.
3. M. Mollazadeh, K. Murari, G. Cauwenberghs, and N. Thakor, “Micropower CMOS integrated low-noise
amplification, filtering, and digitization of multimodal neuropotentials”, IEEE Trans. Biomed. Circuits Syst.,
vol. 3, no. 1, pp. 110, Feb. 2009.
4. Julian Garcia, Saul Rodriguez and Ana Rusu, “A Low-Power CT Incremental 3rd Order Σ∆ ADC for
Biosensor Applications”, IEEE J. Solid-State Circuits, vol. 60, no. 1, pp. 25-36, Jan. 2013.
5. Chao Chen, Zhichao Tan, Michiel A. P. Pertijs, “A 1V 14b Self-Timed Zero-Crossing-Based Incremental Σ∆
ADC”, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 274-275, Feb.
2013.
6. Chae, Youngcheol and Lee, Inhee and Han, Gunhee, “A 0.7V 36uW 85dB-DR Audio 85-dB DR Audio Delta-
Sigma Modulator Using Class-C Inverter”, in IEEE International Solid-State Circuits Conference Digest of
Technical Papers, pp. 490-630, Feb. 2008.
APPENDIX A
KT/C NOISE OF INCREMENTAL ADCS

This appendix derives the input referred thermal noise and limitations on CS for different order
incremental ADCs. In Section 3.1, we briefly introduced the same topic for the second-order
incremental architecture plotted in Fig. 2.17. Here, we derive the equations with more details from
second-order to Lth-order incremental architectures.

A.1 kT/C Limitation of Second-Order Incremental ADCs

2kT Z-1 Z-1 Vres

Cs 1̶Z -1
1̶Z -1

Figure A.1 Second-order incremental ADC equivalent model with kT/C noise as input.

For readers’s convenience, the equivalent model of generalized second-order incremental architecture
is illustrated in Fig. A.1. Notice that the only effective noise term here is the thermal noise generated
by input sampling capacitor CS . For conventional single-ended SC circuits implementation, in the
first clock period, the thermal noise is sampled by the CS and then injected on the delayed integrator.
Consequently, the noise power appeared at the output of the integrator is 2kT /CS . From second to
Multi-Bit A/D Converters with High Resolution and Low-Power. 105
By Yao Liu
106 SHORT APPENDIX TITLE

p
N th clock period, the second integrator accumulates 2kT /CS linearly with one-unit-time delay.
Hence, at the end of N th clock period, the total power can be seen at Vres node due to the kT/C noise
in the first clock cycle is
2kT
Vn2 (1) = (N − 2)2 (A.1)
CS
Similarly, the noise power at Vres node due to kT/C noise injection at ith clock period can be estimated
by

2kT
Vn2 (i) = (N − i − 1)2 (A.2)
CS
Thus, at the end of N th clock period, the total noise power appeared at Vres node is

N −2
2 2kT X 2
Vn,tot = i (A.3)
CS i=1

In order to calculate the input referred kT/C noise, the amplification of the input signal should be
derived. For second-order incremental architectures, we have

(N − 1)(N − 2)
G2ord = (A.4)
2!
Thus, the input referred thermal noise can be derived
2
2
Vn,tot
Vn,in = (A.5)
G22ord

In order to achieve R2ord -bit resolution, Vn,in can not exceed half of VLSB . Consequently, the
minimum CS can be estimated by
PN −2
8kT i=1 i2 VF S
CS > 2 2 ; VLSB = R (A.6)
G2ord VLSB 2 2ord

A.2 kT/C Limitation of Third-Order Incremental ADCs

2kT Z-1 VX Z-1 VY Z-1 Vres

Cs 1̶Z-1
1̶Z -1
1̶Z -1

Figure A.2 Third-order incremental ADC equivalent model with kT/C noise as input.

Similarly, the equivalent model of the third-order incremental architecture is shown in Fig. A.2.
In the first clock period, the thermal noise is sampled by the CS and then injected on the delayed
integrator. From second to N th clock period, the noise appeared at VX is linearly accumulated and
the result is VY . Moreover, the third integrator accumulated VY as a linear function from third to N th
 KT/C LIMITATION OF LTH-ORDER INCREMENTAL ADCS 107

clock period. Based on the above observation, at the end of N th clock period, the total noise power
seen on Vres node due to the kT/C noise injected in the ith clock cycle is

2kT (N − 2 − i)(N − 1 − i) 2
Vn2 (i) = [ ] (A.7)
Cs 2!
Consequently, the total noise power at Vres node at the end of N th clock period is
N −3
2 2kT X (N − 2 − i)(N − 1 − i) 2
Vn,tot (i) = [ ] (A.8)
CS i=1 2!

The amplification from input to Vres at the end of N th clock period is

(N − 1)(N − 2)(N − 3)
G3ord = (A.9)
3!
Thus, the input referred thermal noise of third-order incremental ADCs can be represented by
2
2
Vn,tot
Vn,in = (A.10)
G23ord

In order to achieve R3ord -bit resolution, Vn,in can not exceed half of VLSB . Consequently, the
minimum CS can be estimated by
PN −3
8kT i=1 [(N − 2 − i)(N − 1 − i)]2 VF S
CS > 2 2 ; VLSB = R (A.11)
4G3ord VLSB 2 3ord

A.3 kT/C Limitation of Lth-Order Incremental ADCs

Following the second-order and third-order architectures, the kT/C noise limitation of Lth-order
incremental scheme is also investigated. Using the similar method, when kT/C noise injects at ith
clock period, the consequent noise power appears on Vres at the end of N th clock period is

2kT (N − 1 − i)(N − 2 − i)...(N − L + 1 − i) 2

Vn2 (i) = [ ] (A.12)
CS (L − 1)!
Using (A.12), the total noise power seen at Vres due to noise injection in all N clock periods can be
estimated by
N −L
2 2kT X (N − 1 − i)(N − 2 − i)...(N − L + 1 − i) 2
Vn,tot = [ ] (A.13)
CS i=1 (L − 1)!

However, to calculated the input referred noise, the gain from input to Vres should also be derived,
which is
(N − 1)(N − 2)...(N − L)
GLord = (A.14)
L!
Thus, the input referred noise can be represented by
2
2
Vn,tot
Vn,in = (A.15)
G2Lord
108 SHORT APPENDIX TITLE

Finally, the minimum input sampling capacitance can be estimated as

PN −L
8kT i=1 [(N − 1 − i)(N − 2 − i)...(N − L + 1 − i)]2 VF S
CS > 2 2 2 ; VLSB = R (A.16)
[(L − 1)!] GLord VLSB 2 Lord
APPENDIX B
LIST OF PUBLICATIONS

1. Y. Liu et al., “A 105-dB SNDR, 10 kSps Multi-Level Second-Order Incremental Converter

with Smart-DEM Consuming 280µW and 3.3-V Supply”, in Proc. Eur. Solid-State Circuits Conf.
(ESSCIRC), pp. 371-374, Sept. 2013.

2. Y. Liu and F. Maloberti, “Single Op-Amp Algorithmic Converter and its Offset and Mismatch
Compensation”, in Proc. IEEE Int. Symp. Signals, Circuits and Syst. (ISSCS), pp. 25-28, Jul. 2013.

3. Y. Liu, E. Bonizzoni, and F. Maloberti, “High-order multi-bit incremental converter with Smart-
DEM algorithm”, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 157-160, May 2013.

4. Y. Liu, E. Bonizzoni, and F. Maloberti, “Digital Assisted High-Order Multi-Bit Analog to Digital
Ramp Converters”, in Proc. European Conference on Circuit Theory and Design (ECCTD), pp. 157-
160, Aug. 2011.

Multi-Bit A/D Converters with High Resolution and Low-Power. 109

By Yao Liu