UJ4SC075005L8S Data Sheet-3177181
UJ4SC075005L8S Data Sheet-3177181
UJ4SC075005L8S Data Sheet-3177181
DATASHEET
Description
1
8
Features
G (1)
TAB
w On-resistance RDS(on): 5.4mW (typ)
KS (2)
w Operating temperature: 175°C (max)
S (3-8) w Excellent reverse recovery: Qrr = 440nC
8 w Low body diode VFSD: 1.03V
1
w Low gate charge: QG =164nC
w Threshold voltage VG(th): 4.7V (typ) allowing 0 to 15V drive
w Low intrinsic capacitance
w ESD protected, HBM class 2
Part Number Package Marking w MO-229 package for faster switching, clean gate waveforms
UJ4SC075005L8S MO-229 UJ4SC075005
Typical applications
1. Limited by bondwires
2. Pulse width tp limited by TJ,max
3. Starting TJ = 25°C
4. Short circuit current is independent of the gate voltage VGS>12V
Thermal Characteristics
Value
Parameter Symbol Test Conditions Units
Min Typ Max
Thermal resistance, junction-to-case RqJC 0.10 0.13 °C/W
Value
Parameter Symbol Test Conditions Units
Min Typ Max
Drain-source breakdown voltage BVDS VGS=0V, ID=1mA 750 V
VDS=750V,
6 130
VGS=0V, TJ=25°C
Total drain leakage current IDSS mA
VDS=750V,
45
VGS=0V, TJ=175°C
VDS=0V, TJ=25°C,
Total gate leakage current IGSS 6 20 mA
VGS=-20V / +20V
VGS=12V, ID=80A,
5.4 7.2
TJ=25°C
VGS=12V, ID=80A,
Drain-source on-resistance RDS(on) 9.3 mW
TJ=125°C
VGS=12V, ID=80A,
12.2
TJ=175°C
Gate threshold voltage VG(th) VDS=5V, ID=10mA 4 4.7 6 V
Gate resistance RG f=1MHz, open drain 0.8 1.5 W
Value
Parameter Symbol Test Conditions Units
Min Typ Max
Diode continuous forward current 1 IS TC < 144°C 120 A
Diode pulse current 2 IS,pulse TC=25°C 588 A
VGS=0V, IS=50A,
1.03 1.16
TJ=25°C
Forward voltage VFSD V
VGS=0V, IS=50A,
1.06
TJ=175°C
VDS=400V, IS=80A,
Reverse recovery charge Qrr 440 nC
VGS=0V, RG=20W
di/dt=2800A/ms,
Reverse recovery time trr TJ=25°C 31 ns
Value
Parameter Symbol Test Conditions Units
Min Typ Max
Input capacitance Ciss 8374
VDS=400V, VGS=0V
Output capacitance Coss 362 pF
f=100kHz
Reverse transfer capacitance Crss 4
Effective output capacitance, energy VDS=0V to 400V,
Coss(er) 475 pF
related VGS=0V
Effective output capacitance, time VDS=0V to 400V,
Coss(tr) 950 pF
related VGS=0V
COSS stored energy Eoss VDS=400V, VGS=0V 38 mJ
Total gate charge QG 164
VDS=400V, ID=80A,
Gate-drain charge QGD 24 nC
VGS = 0V to 15V
Gate-source charge QGS 46
Turn-on delay time td(on) 35
Rise time tr Notes 5 and 6, 39
VDS=400V, ID=80A, Gate ns
Turn-off delay time td(off) Driver =0V to +15V, 109
Fall time tf Turn-on RG,EXT=1.5W, 13
Turn-on energy including RS energy EON Turn-off RG,EXT=5W, 766
Turn-off energy including RS energy EOFF inductive Load, FWD: 162
same device with VGS = 0V
Total switching energy ETOTAL 928
and RG = 5W, RC snubber: mJ
Snubber RS energy during turn-on ERS_ON RS=5W and CS=680pF, 17.6
TJ=25°C
Snubber RS energy during turn-off ERS_OFF 7.2
350 350
300 300
250 250
Drain Current, ID (A)
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Drain-Source Voltage, VDS (V) Drain-Source Voltage, VDS (V)
Figure 1. Typical output characteristics at TJ = - 55°C, tp Figure 2. Typical output characteristics at TJ = 25°C, tp <
< 250ms 250ms
350 2.5
300
On Resistance, RDS_ON (P.U.)
2.0
250
Drain Current, ID (A)
Figure 3. Typical output characteristics at TJ = 175°C, tp Figure 4. Normalized on-resistance vs. temperature at
< 250ms VGS = 12V and ID = 80A
Tj = 25°C
Tj = - 55°C Tj = 175°C
4
50
0 0
0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10
Drain Current, ID (A) Gate-Source Voltage, VGS (V)
Figure 5. Typical drain-source on-resistances at VGS = Figure 6. Typical transfer characteristics at VDS = 5V
12V
6 20
Gate-Source Voltage, VGS (V)
5
Threshold Voltage, Vth (V)
15
4
3 10
2
5
1
0 0
-100 -50 0 50 100 150 200 0 50 100 150 200 250
Junction Temperature, TJ (°C) Gate Charge, QG (nC)
Figure 7. Threshold voltage vs. junction temperature at Figure 8. Typical gate charge at VDS = 400V and ID = 80A
VDS = 5V and ID = 10mA
-150 -150
-200 -200
-250 -250
-4 -3 -2 -1 0 -4 -3 -2 -1 0
Drain-Source Voltage, VDS (V) Drain-Source Voltage, VDS (V)
Figure 9. 3rd quadrant characteristics at TJ = -55°C Figure 10. 3rd quadrant characteristics at TJ = 25°C
0 120
Vgs = - 5V
100
-50 Vgs = 0V
Vgs = 5V
Drain Current, ID (A)
80
-100 Vgs = 8V
EOSS (mJ)
60
-150
40
-200
20
-250 0
-4 -3 -2 -1 0 0 100 200 300 400 500 600 700 800
Drain-Source Voltage, VDS (V) Drain-Source Voltage, VDS (V)
Figure 11. 3rd quadrant characteristics at TJ = 175°C Figure 12. Typical stored energy in COSS at VGS = 0V
Ciss 120
1.E+04
100
1.E+03 Coss 80
1.E+02 60
40
1.E+01 Crss
20
1.E+00 0
0 100 200 300 400 500 600 700 800 -75 -50 -25 0 25 50 75 100 125 150 175
Drain-Source Voltage, VDS (V) Case Temperature, TC (°C)
Figure 13. Typical capacitances at f = 100kHz and VGS = Figure 14. DC drain current derating
0V
1400
1200
Thermal Impedance, ZqJC (°C/W)
Power Dissipation, Ptot (W)
0.1
1000
800 D = 0.5
0.01
D = 0.3
600
D = 0.1
D = 0.05
400 0.001 D = 0.02
200 D = 0.01
Single Pulse
0 0.0001
-75 -50 -25 0 25 50 75 100 125 150 175 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
Case Temperature, TC (°C) Pulse Time, tp (s)
Figure 15. Total power dissipation Figure 16. Maximum transient thermal impedance
1ms
500
100
10ms 400
Drain Current, ID (A)
Qrr (nC)
100ms
10 300
1ms 200
DC 10ms IS = 80A,
1 di/dt = 2800A/ms,
100 VGS = 0V, RG =20W
0.1 0
1 10 100 1000 0 25 50 75 100 125 150 175
Drain-Source Voltage, VDS (V) Junction Temperature, TJ (°C)
Figure 17. Safe operation area at TC = 25°C, D = 0, Figure 18. Reverse recovery charge Qrr vs. junction
Parameter tp temperature at VDS = 400V
1600 60
VGS = 0V/15V, RG_ON=1.5W, VGS = 0V/15V, RG_ON=1.5W,
1400 RG_OFF=5W, Device RC snubber: 50 RG_OFF=5W, Device RC snubber:
Snubber RS Energy (mJ)
800 30
Etot
600
Eon 20
400 Eoff Rs_Etot
Rs_Eon
10
200 Rs_Eoff
0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Drain Current, ID (A) Drain Current, ID (A)
Figure 19. Clamped inductive switching energy vs. drain Figure 20. RC snubber energy loss vs. drain current at
current at VDS = 400V and TJ = 25°C VDS = 400V and TJ = 25°C
0 0
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
External RG, RG_EXT (W)
External RG, RG,_EXT (W)
Figure 21. Clamped inductive switching energies vs. Figure 22. RC snubber energy losses vs. RG,EXT at VDS =
RG,EXT at VDS = 400V, ID = 80A, and TJ = 25°C 400V, ID = 80A, and TJ = 25°C
1000 30
900
25
800 VGS = 0V/15V, RG_ON=1.5W, RG_OFF=5W,
Snubber RS Energy (μJ)
Switching Energy (mJ)
Figure 23. Clamped inductive switching energies vs. Figure 24. RC snubber energy losses vs. snubber
snubber capacitance CS at VDS = 400V, ID = 80A, and TJ = capacitance CS at VDS = 400V, ID = 80A, and TJ = 25°C
25°C
1000
Switching Energy (mJ)
800
0
0 25 50 75 100 125 150 175
Junction Temperature, TJ (°C)
Figure 25. Clamped inductive switching energy vs. Figure 26. Schematic of the half-bridge mode switching
junction temperature at VDS =400V and ID = 80A test circuit. Note, a device snubber (Rs =5Ω, Cs = 680pF)
and bus RC snubber (RBS = 1W, CBS=100nF) is used to
reduce the power loop high frequency oscillations.
SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET
connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This
combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low
on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching
losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode.
Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high
dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum
reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com.
A snubber circuit with a small R(G), or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R(G) value.
There is no extra gate delay time when using the snubber circuitry, and a small R(G) will better control both the turn-off V(DS) peak spike and
ringing duration, while a high R(G) will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a
snubber circuit is less than using high R(G), while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency
will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit
the UnitedSiC website at www.unitedsic.com
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UJ4SC075005L8S