Implementing MIPS

• We're ready to look at an implementation of the MIPS instruction set

• Simplified to contain only
– arithmetic-logic instructions: add, sub, and, or, slt
– memory-reference instructions: lw, sw
– control-flow instructions: beq, j

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format
 Implementing MIPS: the
Fetch/Execute Cycle
• High-level abstract view of fetch/execute implementation
– use the program counter (PC) to read instruction address
– fetch the instruction from memory and increment PC
– use fields of the instruction to select registers to read
– execute depending on the instruction
– repeat…

Data

Register #
PC Address Instruction Registers ALU Address
Instruction Register #
memory Data
Register # memory

Data
 Overview: Processor Implementation

Single Cycle
– perform each instruction in 1 clock cycle
– clock cycle must be long enough for slowest instruction; therefore,
– disadvantage: only as fast as slowest instruction
Multi-Cycle
– break fetch/execute cycle into multiple steps
– perform 1 step in each clock cycle
– advantage: each instruction uses only as many cycles as it needs
Pipelined
– execute each instruction in multiple steps
– perform 1 step / instruction in each clock cycle
– process multiple instructions in parallel – assembly line

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

An overview of Implementation:

For every Instruction

 Send Program Counter(PC) to memory that contains code and

fetch the instruction from that memory

 Read one or two registers, using fields of the instruction to select

the registers.

 For the load word instruction, we need to read only one register,
but most other instructions require that we need two registers.

 After these two steps actions required depend on instruction

class.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

All instruction classes except jump use arithmetic-logic unit
(ALU) after reading the registers.

Memory reference instructions use ALU for an address

calculation

Arithmetic-logical instruction use ALU for operation execution

Branch use ALU for comparison.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

After using ALU, the actions required to complete various
instruction classes differ

A memory reference instruction will need to access memory

either to write data for a store or read data for load

An arithmetic/logical instruction write data from the ALU back

into the register

For branch instruction may need to change the next instruction

address based on comparison.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Datapath: Instruction Store/Fetch &
PC Increment

Instruction
address
Add
PC
Instruction Add Sum
Instruction
4
memory

PC Read
address
a. Instruction memory b. Program counter c. Adder
Instruction
Instruction
Three elements used to store memory

and fetch instructions and

increment the PC
Datapath
Animating the Datapath
Instruction <- MEM[PC]
PC <- PC + 4
ADD

PC
ADDR
Memory
RD Instruction
 Datapath: R-Type Instruction

ALU control ALU operation

5 Read 3 Read 3
register 1 register 1
Read Read
Register 5 data 1 data 1
Read Read
numbers register 2 Zero Zero
Registers Data ALU ALU Instruction register 2
5 Write result
Registers ALU ALU
register Write result
Read
data 2 register
Write Read
Data data data 2
Write
RegWrite
data

RegWrite
a. Registers b. ALU

Two elements used to implement Datapath

R-type instructions
Animating the Datapath

add rd, rs, rt

Instruction
op rs rt rd shamt funct R[rd]  R[rs] + R[rt];

5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite
 Datapath: Load/Store Instruction

3 ALU operation
Read
MemWrite register 1 Read MemWrite
Read data 1
Instruction register 2 Zero
Registers ALU ALU
Address Read Write result Address Read
data 16 32 register data
Sign Read
extend Write data 2
Data data Data
Write
data memory memory
RegWrite Write
data
16 32
Sign MemRead
MemRead
extend

a. Data memory unit b. Sign-extension unit

Two additional elements used Datapath

To implement load/stores
Animating the Datapath

lw rt, offset(rs)
R[rt]  MEM[R[rs] + s_extend(offset)];
Animating the Datapath

sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)]  R[rt]
Datapath: Branch Instruction

PC + 4 from instruction datapath

No shift hardware required:

Add Sum Branch target
simply connect wires from
input to output, each shifted Shift
left 2 bits left 2

ALU operation
Read 3
Instruction register 1 Read
Read data 1
register 2 To branch
Registers ALU Zero
Write control logic
register Read
Write data 2
data
RegWrite

16 32
Sign
extend

Datapath
 Animating the Datapath

PC +4 from
op rs rt offset/immediate instruction
16 datapath ADD
5 5 Operation
<<2
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite

16
E
X 32
beq rs, rt, offset
T
N if (R[rs] == R[rt]) then
D
PC  PC+4 + s_extend(offset<<2)