Digital Electronics Unit 10

Unit 10 Shift Registers

Structure:
10.1 Introduction
Objectives
10.2 Introduction to Shift Registers
10.3 Types of Shift Registers
10.4 Bidirectional Shift Registers
10.5 Universal Shift Register
10.6 Shift Register Counters
10.7 Typical ICs for Shift Registers
10.8 Sequence Generators
10.9 Summary
10.10 Terminal Questions
10.11 Answers

10.1 Introduction
In the previous unit, we have studied the definition of sequential circuit, and
flip flops and the types of flip-flops. Shift registers are typically used as
converters between serial and parallel devices. Most of the data processing
logic works on set of bits together. For example the CPU of a computer
works on data bits stored in the registers. Hence mapping serial stream of
data into parallel data bytes is really useful. At the same time it is easier to
implement serial data transmission logic. Shift registers also act as delay
elements. The timing properties of shift register are defined and limited by
the clock signal supplied to it. Most of the CPU’s that have machine level
instructions can move the bits stored in a shift register to the left or right in a
group. Earlier computers used very large sized shift registers with sizes of a
few thousand bits. These worked like delay line memory elements. In this
unit we study the definition of shift registers, their types and operation. We
also study some shift register ICs.
Objectives:
After studying this unit, you should be able to:
 define shift registers
 list and explain the different types of shift registers
 discuss the operation of bidirectional shift registers

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 explain the function of universal shift registers

 list and explain shift register counters
 list the ICs used as shift registers
 design the sequence generators

10.2 Introduction to Shift Registers

We know that a Flip-flop is a 1 bit memory cell which can be used for storing
the digital data. To increase the storage capacity in terms of number of bits,
a group of flip-flop is used. Such a group of flip-flops is known as a Register.
Shift Register is a group of flip-flops combined and connected together to
facilitate the movement or shifting of the data bits from one flip flop to
another whenever desired by activating control signals. In other words, a
register that allows shifting of data either from left to right or from right to left
is called a shift register.
The Shift register is another type of sequential logic circuit that can be used
for the storage or the transfer of data in the form of binary numbers. This
sequential device loads the data present in its inputs and then moves or
“shifts” it to its output once in every clock cycle, hence the name “shift
register”.
A shift register usually consists of several single bit “D-Type Data Latches”,
one for each data bit, either a logic “0” or a “1”, connected together in a
serial type daisy-chain arrangement so that the output from one data latch
becomes the input to the next latch and so on. Sometimes an SR flip-flop
may also be used for the construction of shift registers. Data bits may be fed
in or out of a shift register serially, that is, one after the other from either the
left or the right direction, or all together at the same time in a parallel
configuration.
The effect of data movement from left to right through a shift register can be
presented graphically as shown in figure 10.1.

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Figure 10.1: Data movement in a shift register

Also, the directional movement of the data through a shift register can be
either to the left, (left shifting) to the right, (right shifting) left-in but right-out,
(rotation) or both left and right shifting within the same register thereby
making it bidirectional. In this tutorial it is assumed that all the data shifts to
the right, (right shifting).
The number of individual data latches required to make up a single shift
register device is usually determined by the number of bits to be stored. So
an n-bit register will consist of n number of flip-flop and it is capable of
storing an n-bit word.
Shift registers are used for data storage or for the movement of data.
Therefore they are also commonly used inside calculators or computers to
store data, or to convert the data from either a serial to parallel or parallel to
serial format. The individual data latches that make up a single shift register
are all driven by a common clock (CLK) signal making them synchronous
devices.
There are bi-directional shift registers that allow shifting of data bits in both
directions, i.e. from left to right and vice versa. If we connect inputs and
outputs of a serial-in serial-out shift register, we get so called circular shift
register.

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Self-Assessment Questions
1. Register is a group of__________________.
2. __________________ is a group of flip-flops combined and connected
together to facilitate the movement of data bits from one flip flop to
another.
3. Shift registers are used only for data storage but not for the movement
of data. (State true or false)

10.3 Types of Shift Registers

Inputs to the shift registers can be serial or parallel. Similarly outputs of the
shift registers can be serial or parallel. Based on the serial or parallel nature
of inputs and outputs, we can have four types of shift registers. They are:
1) Serial Input Serial Output (SISO)
2) Serial Input Parallel Output (SIPO)
3) Parallel Input Serial Output (PISO)
4) Parallel Input Parallel Output (PIPO)
In Serial-in to Serial-out (SISO) shift register, the data is shifted serially “IN”
and “OUT” of the register, one bit at a time in either a left or right direction
using clock pulses. This concept is shown in the figure 10.2

Figure 10.2: Serial-In Serial-Out (SISO)

In Serial-in to Parallel-out (SIPO) shift register, the register is loaded with

serial data, one bit at a time, with the stored data being available at the
output in parallel form. The concept of SIPO is shown in figure 10.3.

Figure 10.3: Serial-In Parallel-Out (SIPO)

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In Parallel-in to Serial-out (PISO) shift register, the parallel data is loaded

into the register simultaneously and is shifted out of the register serially one
bit at a time using clock pulses. The concept of SIPO is shown in figure 10.4.

Figure 10.4: Parallel-In Serial-Out (PISO)

Parallel-in to Parallel-out (PIPO) shift register, the parallel data is loaded

simultaneously into the register, and transferred together to their respective
outputs by the same clock pulse. The concept of PIPO is shown in
figure 10.5.

Figure 10.5: PIPO Shift Register

Now we will see the operation of all the four types of shift registers.
1. Serial Input Serial Output (SISO) Shift Register:
As the name suggests, in SISO shift register data bits are stored in serially
and in the same way they get out of the shift register serially. The
figure 10.6 shows the block diagram of a 4-bit SISO shift register
implemented using positive edge triggered D flip-flops. The table 10.1
shows the truth table of SISO shift register.

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Figure 10.6: Block diagram of a 4-bit SISO shift register

Table 10.1: Truth table of SISO shift register

Clock Pulse Data In Q0 Q1 Q2 Q3

0 0 0 0 0 0
1 1 (LSB) 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 1 (MSB) 1 1 0 1 (LSB)
5 x X 1 1 0
6 x X x 1 1
7 x X x x 1(MSB)
8 x X x x x

Note: X = don’t care condition = 0 or 1

Operation:
The string of bits that we want to shift in are applied to the input named
‘Data in’. Each bit presented at ‘Data in’ is shifted to its right flip-flop one bit
at a time when every time ‘clock signal is applied signal. First time, the bit
on ‘Data in’ line is moved into the first ‘flip-flop. The data bit on the rightmost
flip-flop gets shifted out through the output line of the shift register ‘Serial
Data output line (Q3). This bit goes out through ‘Serial Data output’ and is
lost.
Let us see more clearly how this works. Each row of four bits in the
table 10.1 can be imagined to be the outputs of the four flip-flops that make
up our SISO (serial-in serial-out) shift register. Assume that we want to shift
the data stream 1101 into the shift register serially and read them out
serially.

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Let the register is reset so that all the flip-flop outputs are reset to 0.
We now feed a stream of bits (LSB) 1, 0, 1, 1 (MSB) at ‘Data in’ line and at
the same time apply the clock pulse for every data bit. We see that data is
right shifted for every clock pulse (i.e. positive edge of the clock pulse) and
after four pulses the register is filled with 1101 from left to right. Now we can
read first bit (LSB). The remaining bits can be read by applying three more
clock pulses, and the data can be read out from ‘Serial Data output line’
(i.e Q3 output line) as shown in the table 10.1. Note that, from 5th clock pulse
onwards, we assume that the data in takes the X where X=0 or 1 as its input
data.
If we collect all the data bits at ‘Data Out’ line after the register is filled with
the serial data input, we get 1101 as the bit stream from the single serial
output data line called “serial data out” So what we get at the output is what
we had put in through the input. However the output is delayed by four
cycles of clocking. The data movement though SISO shift register
resembles a queue implemented in hardware. Since the data bits that are
shifted out of ‘Data Out’ are lost, we call this destructive readout.
Non-destructive readout
It is possible to ensure reading the data out from a SISO shift register as
non-destructive. All we have to do is to connect the ‘Data Out’ line to ‘Data
in’ line under the control of an additional input line. Let us call this
‘Read/Write (R/W)’ line. When this input is set to 1(or Write), it behaves like
a normal SISO register with destructive readout. When R/W is set
to 0 (Read), ‘Data Out’ gets logically connected to ‘Data in’ and the data bits
that get shifted out upon pulsing the ‘Data Shift’ line become the inputs and
get shifted in again. Thus the data is retained in the shift register.
2. Serial in parallel Out(SIPO) Shift register:
This is almost similar to SISO shift register except that the data are readout
in parallel at the same time. This means, we can input the data bits into this
shift register serially through ‘Data in’ input line and data can be read out in
parallel from data out lines Q3Q2Q1Q0. The figure 10.7 shows the block
diagram of a 4-bit SIPO shift register implemented using positive edge
triggered D flip-flops. The table 10.2 shows the truth table of SIPO shift
register.

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Figure 10.7: Block diagram of a 4-bit SIPO shift register

Table 10.2: Truth table of SIPO shift register

Clock Pulse Data In Q0 Q1 Q2 Q3
0 0 0 0 0 0
1 1 (LSB) 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 1 (MSB) 1 1 0 1

Operation:
The string of bits that we want to shift in are applied to the input named
‘Data in’. Each bit presented at ‘Data in’ is shifted to its right flip-flop one bit
at a time when every time ‘clock signal is applied, First time, the bit on ‘Data
In’ line is moved into the first ‘flip-flop’s output. The data bit on the rightmost
flip-flop gets shifted out through the output line of the shift register ‘Serial
Data output line which is the output line Q3.
Let us assume that we want to store the data 1101 serially into the shift
register and read them out in parallel. Let the register is reset so that all the
flip-flop outputs become 0.(i.e. Q3Q2Q1Q0 =0000). Now we feed a stream of
bits (LSB) 1, 0, 1, 1 (MSB) at ‘Data in’ line serially one bit at a time using the
clock pulses. So we require four clock pulses to store all the four data bits
into four flip-flops. We see that data is right shifted for every clock pulse and
after four clock pulses, the register is filled with 1101 from left to right. Now
we can read out data from Q3Q2Q1Q0 output lines simultaneously in parallel
and this is shown in the table 10.2.

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3. Parallel Input Serial Output (PISO) Shift register:

In Parallel-In, Serial-Out (PISO) shift register, the data input is given in
parallel to the input line of each of the flip-flops and outputs are readout
serially from single output line (Serial Data Out).
The figure 10.8 shows the 4-bit Parallel-In Serial-Out (PISO) Shift Register
and table 10.3 shows its truth table.

Figure 10.8: 4-bit Parallel-In Serial-Out (PISO) Shift Register

Table 10.3: Truth table of PISO shift register

Parallel Data
Clock Pulse Q1 Q2 Q3 Q4
D1D2D3D4
0 0 0 0 0 0 0 0 0
1 1 0 1 1 1 0 1 1
2 XX XX x 1 0 1
3 XX XX x x 1 0
4 XX XX x x x 1

Where X is a don’t care condition, X= 0 or 1

Let us assume that we want to store the data 1011 parallely into the shift
register and read them out in a serial fashion. The data inputs are given to
parallel input lines of each of the flip-flops, D0 through D3. To switch
between data-input and data-shift mode, a control signal Write /Shift’ ( W /S)
is used.

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When W /S input =0, the data bits on D0-D3 lines get loaded to the outputs
of the respective flip-flops, Q0-Q3 after the application of a single clock pulse.
After the single clock pulse, we can read the LSB (least significant Bit) 1 that
is available at Q3 output line. For reading the remaining data bits, we have
to shift the loaded data bits so that they appear at the output line Q3. So for
shifting the data out, we have to set W /S = 1. Now by applying three more
clock pulses we can shift and read the remaining data bits serially at the
single output line Q3 one bit at time for every single clock pulse. This is
shown in the table 10.3. Thus four clock pulses are sufficient to load, shift
and read all the data bits.
4. Parallel Input Parallel Output (PIPO) Shift register:
In PIPO shift register, Input data bits can be loaded into the register in
parallel and the output data can be read out of the register in parallel. This
type of shift register also acts as a temporary storage device or as a time
delay device since the same input data appears at the output terminals of
the flip-flops after a delay.
The figure 10.9 shows the 4-bit Parallel-In Parallel-Out (PIPO) Shift Register
and table 10.4 shows its truth table.

Figure 10.9: Block diagram of 4-bit PIPO Shift Register

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Operation:
Let us assume that we want to load the four bit binary input 1011. These
four bits are applied to the data inputs D3D2D1D0 of respective four flip-flops
such that D3=1 D2=0 D1=1 D0 =1. As soon as a positive clock edge is applied,
the input binary bits will be loaded into the four flip-flops simultaneously.
Only one clock pulse is essential to load all the bits. The loaded bits will now
appear simultaneously at all the four outputs terminal Q3Q2Q1Q0. Now we
can read all the data bits from outputs simultaneously in parallel and this is
shown in the table 10.4.
Table 10.4: Truth table of PIPO shift register
Parallel Data inpputs
Clock Pulse Q0 Q1 Q2 Q3
D0D1D2D3
1 1 0 1 1 1 0 1 1

Self-Assessment Questions
4. SIPO stands for_________________________.
5. In _________________ shift register, the data input is given in parallel
to the input line of each of the flip-flops and outputs are readout serially
from single output line (Serial Data Out).
6. In PIPO shift register a single clock pulse is sufficient to store and read
the data bits. (State true or false)

Activity 1:
Draw the logic diagram of 6 bit SISO shift register and write the truth
table.

10.4 Bidirectional Shift Registers

A shift register which can shift the data in only one direction is called a
unidirectional shift register.
A shift register which can shift the data in both directions (shift either left or
right) is called a bi-directional shift register.
The figure 10.10 shows the block diagram of a 4 bit bidirectional shift
register which is implemented using D flip-flops.

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Figure 10.10: Block diagram of 4-bit bidirectional shift register

There are two serial inputs namely the serial right shift data input DR and
the serial left shift data input DL along with a select input LEFT /Right.
Operation:
1) When LEFT / Right = 1: Shift right operation takes place and the AND
gates 1, 3, 5 and 7 are enabled whereas the remaining AND
gates 2,4,6 and 8 will be disabled. The data at DR is shifted to right bit
by bit from FF3 to FF0 on the application of clock pulses. Thus with
LEFT /Right = 1 we get the serial right shift operation.

2) When LEFT /Right = 0: Shift left operation takes place and the AND
gates 2, 4, 6 and 8 are enabled while 1,3,5 and 7 are disabled. The
data at DL is shifted left bit by bit from FF0 to FF3 on the application of
clock pulses. Thus LEFT /Right = 0 we get the serial right shift
operation.

10.5 Universal Shift Register

A shift register which can shift the data in both directions as well as load it
serially and parallely is known as a universal shift register. The shift register
is capable of performing the following operations:
 Parallel loading
 Lift shifting
 Right shifting

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Today, there are many high speed bi-directional “universal” type Shift
Registers available in the form of integrated circuits (ICs) chips. For
example, IC chips such as the TTL 74LS194, 74LS195 or the CMOS 4035
which are 4-bit multi-function devices can be used in either serial-to-serial,
left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-
to-parallel multifunction data register, hence the name “Universal”. These
universal shift registers can perform any combination of parallel and serial
input to output operations but require additional inputs to specify desired
function and to pre-load and reset the device.
Universal shift registers can be configured to respond to operations that
require some form of temporary memory storage or for the delay of
information such as the SISO or PIPO configuration modes or to transfer
data from one point to another in either a serial or a parallel format. We can
use a Universal shift in arithmetic operations for shifting data to the left or
right for multiplication or division.
Self-Assessment Questions
7. A shift register which can shift the data in both directions (shift either
left or right) is called a ________________shift register.
8. A shift register which can shift the data in both directions as well as
load it serially and parallely is known as a _____________shift register.
9. The integrated circuit (IC) chip 74LS194 is a universal shift register
(State true or false)

10.6 Shift Register Counters

A shift register has no specified sequence of states. However, if the serial
output of the shift register is fed back to the serial input, it can exhibit a
specified sequence of states like that of a counter. Then the resulting shift
register circuits are known as shift register counters.
Depending upon the nature of the feedback, there are two types of shift
register counters: the Ring counter and the Johnson counter. These are
basically shift registers with the serial outputs connected back to the serial
inputs in order to produce particular sequences.
Ring Counters
A ring counter is basically a circulating shift register in which the output of
the most significant stage (Q3) is fed back to the input of the least significant

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stage. We can circulate any bit (0 or 1), but usually the ring counter is used
for circulating a single bit ‘1’ in a loop in a ring fashion.
The figure 10.11 shows a 4-bit ring counter constructed from D flip-
flops. The output of each stage is shifted into the next stage on the positive
edge of a clock pulse. If the CLEAR (CLR) signal is high, flip-flops FF1,
FF2 ,FF3 are reset to 0 and FF0 is preset to 1.

Figure 10.11: 4-bit ring counter

Table 10.5: Truth table of Ring counter

The count sequence has 4 distinct states. So we can consider the counter
as a mod-4 counter. Only 4 of the maximum 16 states are used, making
ring counters very inefficient in terms of state usage. But the major
advantage of a ring counter over a binary counter is that it is
self-decoding. No extra decoding circuit is needed to determine what state
the counter is in.
Johnson Counters:
Johnson counters are a variation of standard ring counters, with the inverted
output of the last stage fed back to the input of the first stage. They are also
known as twisted ring counters. Depending on the initial bit pattern stored
in the shift register, the shift register content changes for every clock pulse

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and the bit pattern gets repeated after 2n clocks, where n is the number of
bits in the shift register. So an n-stage Johnson counter yields a count
sequence of length 2n, so it may be considered to be a mod-2n
counter. The figure 10.12 shows a 4-bit Johnson counter. The state
sequence for the counter is given in the table as well as the animation on
the left.

Figure 10.12: 4-bit Jonson counter

Table 10.6: Truth table of Johnson counter

Clock Pulse Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1
5 1 1 1 0
6 1 1 0 0
7 1 0 0 0

The disadvantage of this counter is that the maximum available states are
not fully utilized. The maximum states available are sixteen but only eight
states are used.
Note: Both the Ring and the Johnson counter must initially be forced into a
valid state in the count sequence because they operate on a subset of the
available number of states. Otherwise, the ideal sequence will not be
followed.

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Applications:
Shift registers can be found in many applications. Here is a list of a few
applications.
1) To produce time delay: SISO shift register can be used to introduce
time delay. The time delay Δt is given by
Δt = N*( 1/fc)
where N is the number of flip flop stages and fc is the clock frequency.
2) To convert serial data to parallel data: A computer or
microprocessor-based system commonly requires data in a parallel
format. So serial-to-parallel conversion is required. So we can use
SIPO shift register for this purpose.
3) Shift register counters: We can use shift register to work as counter
to produce particular sequence. For example, ring counter and Johnson
counter.

10.7 Typical ICs for Shift Registers

There are typical ICs that work as shift registers. For example, IC 74LS194
is a commonly used 4-bit Universal Shift Register. The pin details are shown
in the figure 10.13.

Figure 10.13: Pin details of IC 74LS194

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The parallel loading of data is accomplished with a positive transition of the

clock and by applying the four bits of data to the parallel inputs and a HIGH
to the S1 and S0 inputs. Similarly, shift-right is done synchronously with the
positive edge of the clock when S0 =1 and S1 =0. In this mode the serial
data is entered at the shift right serial input (At Pin no.2). Similarly, when
S0 = 0 and S1 = 1, data bits shift left synchronously with the clock pulse and
new data is entered at the shift-left serial input (At pin no.7).
IC 7491: 8-bit Serial in Serial out Shift Register
The IC 7491 packages an 8-bit shift register. There are eight SR flip flops
connected to provide a serial input as well as a serial output. Data present
on the input pins will be clocked in to the first register once the circuit
receives a clock pulse. All other data, already registered, will be shifted over
to make room for the new input. Data at the far end of the chain will be
clocked out every cycle. In this regard, this circuit acts as an 8 bit First-In-
First-Out buffer queue. The figure 10.14(a) shows the pin diagram of
IC 7491 and figure 10.14(b) shows its logic diagram.

Figure 10.14: IC 7491-8 bit SISO shift register (a) Pin details (b) logic diagram

In the logic diagram, the inputs A and B of NAND gate are the two gated
data input lines for serial data entry. When the data are entered on A, the B

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input must be HIGH, and vice versa. Therefore, either A or B can be used as
serial data input and other input can be used as control line.
IC type 74195
IC type 74195 is a 4-bit shift register with parallel load and asynchronous
clear. It is capable of shifting only in one direction. The pin diagram of
IC 74195 is shown in figure. 10.15.

Figure 10.15: Pin diagram of IC 74195

The single control line labeled SH/LD (shift/load) decides the synchronous
operation of the register. When SH/LD = 0, the control input is in the load
mode and the four data inputs are transferred into the four internal flip-flops,
QA through QD. When SH/LD = 1, the control input is in the shift mode and
the information in the register is shifted right from QA toward QD. The serial
input into QA during the shift is determined from the J and K inputs. The two
inputs behave like the J and the complement of K of a JK flip-flop. When
both J and K are equal to 0, flip-flop QA is cleared to 0 after the shift. If both
inputs are equal to 1, QA is set to 1 after the shift. When the clear input
goes to 0, the four flip-flops clear to 0 asynchronously. To load the input
data, the SH/LD must be equal to 0 and a positive clock-pulse transition
must occur. To shift right, the SH/LD must be equal to 1. The J and K inputs
must be connected together to form the serial input.
Self-Assessment Questions:
10. A shift register which can exhibit a specified sequence of states as that
of a counter is known as __________________.
11. An n-stage Johnson counter yields a count sequence of length 4n.
(True or False?).

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12. SISO shift register can be used to introduce time delay. (True or
False?)

10.8 Sequence Generators.

A sequence generator is a digital circuit that generates a desired sequence
of bits in synchronization with a clock. It can be used as a random
bit generator, code generator, and prescribed period generator. The
figure 10.16 shows the block diagram of a sequence generator.

Figure 10.16: Block diagram of a sequence generator

The sequence generator is constructed using shift register and a next state
decoder. The output of the next state decoder (Y) is a function of QN-1,
QN-2,……Q1, Q0 and is connected to the serial input of the shift register.
Now let us see the design of a 5-bit sequence generator. We consider the
design of a sequence generator to generate a sequence of 10011. The
minimum number of flip-flops (n) required to generate a sequence of length
N is given by the equation
N ≤ 2n –1.
Here N = 5 and hence, the minimum number of flip-flops required is 3. If the
given sequence does not lead to five distinct states, then more than three
flip-flops may be required. The states of the given sequence generator are
shown in table 10.7.

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Table 10.7 State table for a 5-bit (10011) sequence generator

The given sequence (10011) is listed under Q2 and the sequence under
Q1 and Q0 are the same sequence delayed by one and two clock pulses
respectively as indicated by arrow marks. Also note that all 5 states are
distinct and hence three flip-flops are sufficient to implement the sequence
generator. The last column gives the serial input required at the shift register
(i.e., D2 of MSB flip-flop), assuming D flip-flops are used and considering the
output at Q2. Now, the K-map for the serial input (Y) is shown in
figure 10.17.

Figure 10.17: K-map of Y for a 5-bit (10011) sequence generator.

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In the k-map, we have entered 0 to the cells corresponding to Q2Q1Q0=011,

Q2Q1Q0=111, and entered 1 to the cells that corresponds to Q2Q1Q0=001,
Q2Q1Q0=100 and Q2Q1Q0=110. This is required to get the required
sequence as per the column Y in the truth table 10.7. To other cells, we
have entered don’t care condition X whose value may be 0 or 1.
From the K-map shown in figure 10.17, the simplified expression for serial
input Y can be written as Y = Q’1 + Q’0. The logic diagram of a given 5-bit
sequence generator is shown in figure 10.18.

Figure 10.18: Logic diagram of a 5-bit (10011) sequence generator.

Activity 2:
Generate a sequence 11001 using a sequence generator and draw the
logic diagram.

Self-Assessment Questions
13. In case of universal shift register IC 74LS194, shift-right is done
synchronously with the positive edge of the clock when S0 is High and
S1 is Low. (State true or false)
14. A _______________ is a digital circuit that generates a desired
sequence of bits in synchronization with a clock.

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10.9 Summary
Let us recapitulate the important concepts discussed in this unit:
 A group of flip-flops is known as a Register.
 Shift Register is a group of flip-flops combined and connected together to
facilitate the movement or shifting of the data bits from one flip flop to
another whenever desired by activating control signals.
 There are four types of shift registers: Serial Input Serial Output
(SISO),Serial Input Parallel Output (SIPO),Parallel Input Serial Output
(PISO) and Parallel Input Parallel Output (PIPO)
 In SISO shift register data bits are stored in serially and get out of the
shift register serially.
 In SIPO data bits can be stored into shift register serially and data can be
read out in parallel.
 In Parallel-In, Serial-Out (PISO) shift register, the data input is given in
parallel to the input line of each of the flip-flops and outputs are readout
serially from single output line (Serial Data Out).
 In PIPO shift register, Input data bits can be loaded into the register in
parallel and the output data can be read out of the register in parallel.
 A shift register which can shift the data in both directions (shift either left
or right) is called a bi-directional shift register.
 A shift register which can shift the data in both directions as well as load
it serially and parallely is known as a universal shift register.
 A ring counter is basically a circulating shift register in which the output of
the most significant stage is fed back to the input of the least significant
stage.
 A sequence generator is a digital circuit that generates a desired
sequence of bits in synchronization with a clock.

Glossary:
Register: A group of flip-flops.
Shift register: A group of flip-flops combined and connected together to
facilitate the movement or shifting of the data bits from one flip flop to
another.

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Digital Electronics Unit 10

SISO: A type of shift register in which data bits are stored in serially and in
the same way these get out of the shift register serially.
Bi-directional shift register: A shift register which can shift the data in both
directions (shift either left or right).
Universal shift register: A shift register which can shift the data in both
directions as well as load it serially and parallely.
Ring counter: A circulating shift register in which the output of the most
significant stage is fed back to the input of the least significant stage and
single bit ‘1’ circulates in a loop in a ring fashion.
Sequence generator: A digital circuit that generates a desired sequence of
bits in synchronization with a clock.

10.10 Terminal Questions

1. What is shift register? Explain.
2. List the types of flip flops and explain the functions.
3. Explain the operation of PISO shift register.
4. What is a bidirectional shift register? Explain the operation of a 4 bit
bidirectional shift register.
5. Discuss universal shift registers.
6. Describe the operation of a ring counter.
7. What is a sequence generator? Discuss.

10.11 Answers
Self-Assessment Questions
1. Flip-flops
2. Shift Register
3. False
4. Serial-in to Parallel-out
5. Parallel-In, Serial-Out (PISO)
6. True
7. Bi-directional
8. Universal
9. True
10. Shift register counters
11. False

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Digital Electronics Unit 10

12. True
13. True
14. Sequence generator

Terminal Questions
1. Shift Register is a group of flip-flops combined and connected together
to facilitate the movement or shifting of the data bits from one flip flop to
another whenever desired by activating control signals. Refer to
section 10.2.
2. There are four types of shift registers: Serial Input Serial Output (SISO),
Serial Input Parallel Output (SIPO), Parallel Input Serial Output (PISO)
and Parallel Input Parallel Output (PIPO). Refer to section 10.3.
3. In Parallel-In, Serial-Out (PISO) shift register, the data input is given in
parallel to the input line of each of the flip-flops and outputs are readout
serially from single output line (Serial Data Out). Refer to section 10.3.
4. A shift register which can shift the data in both directions (shift either left
or right) is called a bi-directional shift register. Refer to section 10.4.
5. A shift register which can shift the data in both directions as well as load
it serially and parallely is known as a universal shift register. Refer to
section 10.5.
6. A ring counter is basically a circulating shift register in which the output
of the most significant stage is fed back to the input of the least
significant stage. Refer to section 10.6.
7. A sequence generator is a digital circuit that generates a desired
sequence of bits in synchronization with a clock. Refer to section 10.8.

Sikkim Manipal University B2072 Page No.: 285