VERILOG HDL

INTRODUCTION
 OBJECTIVE

 To understand the different ways of representing the circuit using Verilog

HDL.

To design various digital circuits using Verilog HDL.

To implement the circuit using Verilog HDL.

 Importance of HDL in IC Design
Design and implement a simple unit permitting to speed
up encryption with RC5-similar cipher with fixed key
set on 8031 microcontroller. Unlike in the experiment
5, this time your unit has to be able to perform an
Design Specification (Lab Experiments)
encryption algorithm by itself, executing 32 rounds…..

Verilog HDL description (Your Source Files)

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RC5_core is
Functional simulation
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;

Synthesis (Code to Circuit) Post-synthesis simulation

Design Process
 HARDWARE DESCRIPTION LANGUAGE(HDL)
 HDL (Hardware Description Language) is a hardware description language used

in electronic design automation tool for formal description of

digital electronic circuits such as field-programmable gate arrays

(FPGAs) and Integrated Circuits (IC).

 HDL is a specialized computer language used to describe the structure, design
and operation of electronic circuits, and most commonly, digital logic circuits.
 Verilog HDL that allows for the automated analysis, simulation, and simulated
testing of an electronic circuit.
 A programming language that can describe the functionality and timing of the
hardware.
 Languages whose only characteristic is to express circuit connectivity between a
hierarchy of blocks.
 HARDWARE DESCRIPTION LANGUAGE(HDL)

 HDL is a formal notation intended for use in all phases of the creation of
electronic systems.
 HDL has constructs to handle the parallelism inherent in hardware designs
 HDL, when used for systems design, is that it allows the behavior of the required
system to be described (modeled) and verified (simulated) before synthesis
tools translate the design into real hardware (gates and wires).
 It also allows for the compilation of an HDL program into a lower level
specification of physical electronic components, such as the set of masks used
to create an integrated circuit.
 One important difference between most programming languages and HDLs is
that HDLs explicitly include the notion of time.
 Difference Between Programming and
HDL Language
Programming Language HDL
•Middle level language •High level language
•Can only handle sequential instructions •Allows both sequential and concurrent
executions.
•Successfully written with pure logical or •Successful VHDL programmer needs
algorithmic thinking thorough working knowledge of the
hardware circuits
•Don't care about resource usage in C. •Memory and other logic elements are
limited in a FPGA.
•C program is usually ran on a computer •That’s why it is very difficult to implement
which uses a powerful processor with high image processing algorithms in VHDL than
speed. We also don't care about the memory in C.
usage.
Programming Language Vs Verilog
 Types of HDL
HDLs for analog circuit design
Name Description
Analog Hardware Descriptive an open analog hardware
Language description language
a proprietary analog hardware
SpectreHDL
description language
an open standard extending Verilog
Verilog-AMS (Verilog for Analog
for analog and mixed analog/digital
and Mixed-Signal)
simulation
VHDL-AMS (VHDL with a standardized language for mixed
Analog/Mixed-Signal extension) analog/digital simulation
a proprietary analog hardware
HDL-A
description language
 HDL - Digital
The two most widely-used and well-supported HDL varieties used in industry are Verilog and VHDL.
Name Description
Advanced Boolean Expression Language (ABEL) basic HDL
Altera Hardware Description Language (AHDL) a proprietary language from Altera
AHPL A Hardware Programing language
Bluespec high-level HDL based on Haskell
Bluespec SystemVerilog (BSV) based on Bluespec, with Verilog HDL like syntax.
C-to-Verilog Converter from C to Verilog
JHDL based on Java
M A HDL from Mentor Graphics
My HDL based on Python (embedded DSL)
PALASM for Programmable Array Logic (PAL) devices
ROCCC (Riverside Optimizing Compiler for
Free and open-source C to HDL tool
Configurable Computing)
RHDL - Ruby (hardware description language) based on the Ruby programming language
a standardized class of C++ libraries for high-level
SystemC
behavioral and transaction modeling of digital hardware
a superset of Verilog, with enhancements to address system-
SystemVerilog
level design and verification
Verilog One of the most widely-used and well-supported HDLs
VHDL (VHSIC HDL) One of the most widely-used and well-supported HDLs
 Popular HDL Language
 The two most widely-used and well-supported HDL varieties used in industry are

1. Verilog HDL
2. VHDL. (Very High Speed Integrated Circuit HDL)
HDL Modeling Capability
 General Properties

 Purpose of VHDL and Verilog HDL are same but they differ in
their syntax and the levels of circuit descriptions.
 Supports Digital only doesn’t support analog circuits.
 Purpose is to create a Digital IC.
 Basic Requirement to learn the language – Digital Electronic
Circuits
 Tools Support: Xilinx ISE , Cadence
 Verilog HDL
 Based on C, originally Cadence proprietary, now an IEEE Standard.

Verilog HDL is case sensitive.

 File Extension .v

 Used to describe the functionality, timing and simulate the digital hardware.

Verilog HDL is a formal notation intended for use in all phases of the creation of
electronic systems. Because it is both machine readable and human readable.

 It also supports the

1.Development 5. Testing of hardware designs.
2.Verification 6. Maintenance.
3.Logic Synthesis 7. Modification.
4.Communication of hardware 8. Procurement of hardware.
 Standards in Verilog HDL
 Invented by Phil Moorby & Prabhu Goel at Gateway Design
Automation Systems in 1983/84.
Later , Cadence took full proprietary in 1990.
 In 1995, Cadence published Verilog for public domain under OVI
(Open Verilog International).
 Verilog-95 – IEEE Standard 1364-1995.
 Verilog 2001 – IEEE Standard 1364-2001.
 Verilog 2005 – IEEE Standard 1364-2005.
 SystemVerilog – Extended from Verilog and C++.
Design Process
Typical Design Flow
 Verilog HDL Simulation Tools
 Synopsys
– VCS – simulator
– Virsim – waveform viewer and environment

 Cadence
– Verilog XL – simulator
– NC Verilog – simulator
– Simvision–waveform viewer and environment

Mentor Graphics
- Leonardo Spectrum-Simulator
- Precision Synthesizer- Simulator
- Modelsim-Simulator,Waveform viewer

 Xilinx ISE
 Altera Quartus II
Hierarchy
Applications
Tool Flow
 Design Methodologies
There are 2 types of design methodologies:
1. Top-down design methodology
2. Bottom-up design methodology

 Top-down design : First define the top-level block

and identify the sub-blocks necessary to build the top-level
block.

 Bottom-up design : First identify the building blocks

that are available to us then build bigger cells, using these
building blocks.
Top Down Design
Bottom Up Design
Example- Ripple Carry Counter
Design Hierarchy of Counter
 Layout of Verilog Language

module <mod name> (<port list>);

<declarations>; // input, output, inout
// wire, register, etc.
<statements>; // initial, begin, end, always
// dataflow statements
endmodule
Components of Verilog Modules
 Module
 A Module is the basic building block in Verilog.
 Elements are grouped into modules to provide the common functionality
that is used at many places in the design.
 A module provides the necessary functionality to the higher-level block
through its port interface (inputs and outputs).
 Keyword - module.
 Keyword – endmodule, must appear at the end of the module definition.
 Modules cannot be nested.
 PORTS

Output should be declared as register – store the values.

Input and In out should be declared as wire does not store the
value they simple reflect the changes in the external signal.
Module
Name: arith

in1
out1

in2

out2

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Module (cont)
Name: arith module arith (out1, out2, in1, in2);
output out1, out2;
input in1, in2;
…
…
endmodule

34
Module Port
Name: arith1
3 types of module port
in1
bi_out ► input
in2
► output
out
in3
► inout

35
Module Port (cont)
Name: arith1 module arith1 (bi_out, out, in1,
in2, in3);
in1 inout bi_out;
bi_out
output out;
input in1, in2;
in2
input in3;
…
out
…
in3
endmodule

36
Comments in Verilog

// One- Line Comment //

/* Block Comment */
Data Types Value Levels
Logical (0,1,x,z) Operation
Verilog Number

Format:
<number of bit><base><number>

Bit length in decimal. Default is host

<number of bit>
machine word size, usually 32 bit.

<base> ‘b, ‘B, ‘d, ‘D, ‘o, ‘O, ‘h, ‘H. Default is ‘d

<number> 0-9, a-f, A-F, X, Z, ?, _

40
Representation of Number in Verilog
What do you infer from this picture ?
Logical (0,1,x,z) Operation
Sized Number

Unsized Number

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 X or Z Values

 X – Unknown Value

 Z – High Impedance Value

Underscore Characters:

Underscore “_” is allowed anywhere in the number except the first

character. It improve the readability of the number.

Eg: 8’b1010_0011 //Use of underscore character for readability.

 Nets & Register
 Net Types: Physical Connection between structural elements
 Register Type: Represents an abstract storage element.
 Keyword – wire, reg
 Default Values
a) Net Types : z
b) Register Type : x
Examples
 Restrictions on Data Types

 Data Flow and Structural Modeling

 Can use only wire data type
 Cannot use reg data type

 Behavioral Modeling
 Can use only reg data type (within initial and always
constructs)
 Cannot use wire data type

47
 Vectors
Reg datatypes can be declared as vectors (multiple bit widths).

Vector Can be declared at [high#,:low#].

Left number in the square bracket is always indicates MSB of

the vector.
Contd..,
 Net Type: Wire
wire [ msb : lsb ] wire1, wire2, …
 Example
wire Reset; // A 1-bit wire
wire [6:0] Clear; // A 7-bit wire

 Register Type: Reg

reg [ msb : lsb ] reg1, reg2, …
 Example
reg [ 3: 0 ] cla; // A 4-bit register
reg cla; // A 1-bit register

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Try Yourself
Contd..,
 Integer, Real, Time Register Data Types
Integer
It is a general purpose data types used for manipulating quantities.

Keyword – integer.

Default width for an integer is the host machine word size, but it is
at least 32 bits

Register store values are Unsigned Quantities.

Integer store values are Signed Quantities.

 Real
Real Number constants and real register data types are declared by real.

Keyword – real.

Number can be specified using decimal notation (3.14) or in scientific

notation (3e6 = 3x106).

Real Numbers cannot have a range of declaration. Default Value is 0.

When a real value is assigned to an integer , the real number is rounded off to
the nearest integer.
Time
 Used to Store the simulation time.

 Keyword – time.

 Simulation time measured in terms of seconds.

 $time – is invoked to get simulation time.

 Arrays
 Arrays are allowed in verilog for reg, integer, time and vector registered
data types.

Arrays are not allowed for real variables.

 Vector is a single element that is n bits wide.

Arrays are multiple elements that are 1 bit or n bits wide

 Parameters

• Keyword – parameter.

• Parameter cannot be used as variables.

• Parameter can be changed at module instantiation or

by defparam.
 Strings
Strings is a sequence of characters that enclosed by a double
quotes.

Strings are limited to 1024 chars. It must contain in a single

line.

Strings are treated as a sequence of one byte ASCII value.

Strings Contd..,
Strings can be stored in reg.

Each Character in a string takes up 8 bits(1 byte).

 SUMMARY
• Output should be declared as register – store the values.
• Input and In out should be declared as wire does not store the
value they simple reflect the changes in the external signal.
• Net Types: Physical Connection between structural elements
• Register Type: Represents an abstract storage element
• Vector Can be declared at [high#,:low#] or [low# :high#].
THANK YOU