Behavioural Modeling

General Objective
 To understand the behavioural modelling and able to apply in digital
design.

Outcome:
At the end of this module the students will be develop the Verilog HDL
code for digital design
Specific Objective
1. List the importance of behavioural modelling.(E )

2. Formulate the usage of conditional statements in Verilog HDL.(E)

Formative Assessment 1

3. Implement various digital circuits using gate level modelling.(T)

Formative Assessment 2
Specific Objective 1
List the importance of behavioural modelling.(E )
Behavioral Modeling
 Behavioral Modeling
 always and initial -- Basic Statements in Behavioral Modeling.

 All other behavioral statements appear only inside the always or

initial statements.
 The Statement inside the always or initial cannot be nested (executes in

sequentially)

 Sequential Block: All statements within the block are executed

sequentially
 When is it executed?
 Occurrence of an event in the sensitivity list
 Event: Change in the logical value

 Statements with a Sequential Block: Procedural Assignments

 Procedural Constructs
 Two Procedural Constructs
 initial Statement
 always Statement
 initial Statement : Executes only once
 always Statement : Executes in a loop
 Example:
… …
initial begin always @(A or B) begin
Sum = 0; Sum = A ^ B;
Carry = 0; Carry = A & B;
end end
… …

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 Initial Statement
It is typically used for initialization, monitoring , waveforms
and other processes.

This statement executes only once during the entire

simulation run.

If Multiple initial block exists each block executes

concurrently.

Multiple behavioral statement grouped together by keyword

begin and end .

If only one behavioral statement is exists grouping is not

necessary.
 Contd..,
 Three Initial statements start to execute parallel at time.

Initial statements

Execution Sequence
 Always Statement
 Keyword – always

 It starts at time 0.

 It executes the statement inside the always block in a continuously in a looping

fashion.

 It is used to model a block of activity that is repeated continuously in a digital

circuits.

 Example: Clock Generator Module that toggles the clock signal every half cycle.
 Initial v/s Always

 initial always
begin begin
… imperative statements … … imperative statements …
End End

 Runs when simulation starts.

Runs when simulation starts
 Terminates when control reaches the end
 Restarts when control reaches the
 Good for providing stimulus.
end.
 Good for modeling / specifying
hardware.
 Types of Procedural Assignments
 Blocking Assignments
 Non Blocking Assignments
 Blocking Assignment
 Blocking Statements are executed in the order they are specified in a
sequential block.

Execution Sequence Y=1 executed after x=0

Counter = Counter+1 executed at Last
 Non Blocking Assignments
 Non Blocking assignments allow scheduling of assignments without
blocking execution of the statement that follow in a
sequential block.
 Operator <= - specify non blocking assignments.
 Non Blocking Assignment to Eliminate Race Condition

 Blocking-Values of register a and b will not be swapped . Instead both

register will get the same value.

 Non Blocking- During Positive Edge of clock, the value on RHS are
read RHS expression evaluated and stored in temporary variable.
 During Write operation , the values stored in the temporary variables
are assigned to LHS. Separating RD and WR Operation ensures the
values of a and b gets swapped. It eliminate race around condition.
Specific Objective 2
Formulate the usage of conditional statements in Verilog HDL.(E)
 Conditional Statements
It is used for making decisions based upon certain conditions.

These conditions are used to decide whether or not a

statement should be executed.

 Keyword = if and else.

Types of Conditional Statements
Conditional Statements Contd..,
 if Statement
 Format:
if (condition)
procedural_statement
else if (condition)
procedural_statement
else
procedural_statement
 Example:
if (Clk)
Q = 0;
else
Q = D;
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 Example
 Example:

module mux_2x1(a, b, sel, out);

input a, b, sel;
output out;
reg out;
always @(a or b or sel)
begin Sensitivity List
if (sel == 1)
out = a;
else out = b;
end
endmodule
Mux using IF Statement
module IF_MUX (c, d, e, f, s, pout);
input c, d, e, f;
input [1:0]s;
output pout;
reg pout;
always @(c or d or e or f or s) begin
if (s == 2'b00)
pout = c;
else if (s ==2'b01)
pout = d;
else if (s ==2'b10)
pout = e;
else pout = f;
end
endmodule
 D Flip Flop
module dff_async_rst (data, clk, reset, q);
module dff (data, clk, q); input data, clk, reset;
output q;
input data, clk; reg q;
output q; always @(posedge clk or negedge or reset)
reg q; if (~reset)
always @(posedge clk) q = 1'b0;
q = data; else
endmodule q = data;
endmodule
 T Flip Flop
module tff(q,clk,rst,t);
input t,clk,rst;
output q;
reg q;
always @ (posedge clk)
begin
if(rst==1)
q<=0;
else
q<=~t;
end
endmodule
 Multiway Branching (Case) Statement
 It is used at the situation when too many alternatives exists.
 Keyword = case, endcase and default.

 Multiple statements must be grouped by keywords begin and end.

 None of the alternatives match, the default statement is executed.
 Default statement is optional.
 Case statement can be nested.
Example
Case Statements (cont.)

 Case Statement
 Example :
case (X)
2’b00:Y = A + B;
2’b01:Y = A – B;
2’b10:Y = A / B;
endcase

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 Casex & Casez Keywords
casez – treat all z values in case expression as donot cares. All the
bit position with z can also represented by ? in that position.

casex – treat all x and z values in case expression as donot cares.

The use of casex and casez allows comparison of only non x or z

positions in the case expression and the case alternatives.

Thus, an input encoding =4’b10xz would cause next_state =3 to be executed.

Contd..,
 Variants of case Statements:
 casex and casez

 casez – z is considered as a don’t care

 casex – both x and z are considered as don’t cares

 Example:
casez (X)
2’b1z: A = B + C;
2’b11: A = B / C;
endcase

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 Case z - Example
module casez_example();
reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;
always @ (opcode or a or b or c)
casez(opcode)
4'b1zzx : begin // Don't care about lower 2:1 bit, bit 0 match with x
out = a;
end
4'b01?? : begin
out = b; // bit 1:0 is don't care
end
4'b001? : begin // bit 0 is don't care
out = c;

end
default : begin
out= x;
end
endcase
 Case x - Example
module casex_example();
reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;

always @ (opcode or a or b or c)
casex(opcode)
4'b1zzx : begin // Don't care 2:0 bits
out = a;
end
4'b01?? : begin // bit 1:0 is don't care
out = b;
end
4'b001? : begin // bit 0 is don't care
out = c;
end
default : begin
out = x;
end
endcase
Mux using Case Statement
module MUX (C, D, E, F, S, MUX_OUT);
input C, D, E, F;
input [1:0] S;
output MUX_OUT;
reg MUX_OUT;
always @(C or D or E or F or S)
begin
case (S)
2'b00 : MUX_OUT = C;
2'b01 : MUX_OUT = D;
2'b10 : MUX_OUT = E;
default : MUX_OUT = F;
endcase
end
endmodule
Contd..,
module mux (a,b,c,d,sel,y);
input a, b, c, d;
input [1:0] sel;
output y;
reg y;
always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
default : $display("Error in SEL");
endcase

endmodule
Contd..,
module case1 (output reg [7:0] d_out
input [7:0] a_in, b_in, c_in, d_in,
input [1:0] sel, );
always @(a_in or b_in or c_in or d_in or sel )
begin
case (sel)
2’b00 : d_out = a_in;
2’b01 : d_out = b_in;
2’b10 : d_out = c_in;
2’b11 : d_out = d_in;
default : d_out = 8’bx;
endcase
end
endmodule
Decoder module decode (Ain, En,Yout);
input En;
input [2:0] Ain;
output [7:0] Yout;
reg [7:0] Yout;
always @ (En or Ain)
begin
if (!En)
Yout = 8'b0;
else
case (Ain)
3'b000 :Yout = 8'b00000001;
3'b001 :Yout = 8'b00000010;
3'b010 :Yout = 8'b00000100;
3'b011 :Yout = 8'b00001000;
3'b100 :Yout = 8'b00010000;
3'b101 :Yout = 8'b00100000;
3'b110 :Yout = 8'b01000000;
3'b111 :Yout = 8'b10000000;
default :Yout = 8'b00000000;
endcase
end
endmodule
 module srff(q,clk,rst,s,r);
SR Flip Flop input s,r,clk,rst;
output q;
reg q;
always @ (posedge clk or rst)
begin
if(rst)
q<=0;
else
begin
case({s,r})
2'b00:q<=q;
2'b01:q<=s;
2'b10:q<=s;
default:$display("Not Allowed");
endcase
end
end
endmodule
 module jkff(q,clk,rst,j,k);

JK Flip Flop input j,k,clk,rst;

output q;
reg q;
always @ (posedge clk or rst)
begin
if(rst)
q<=0;
else
begin
case({j,k})
2'b00:q<=q;
2'b01:q<=j;
2'b10:q<=j;
2'b11:q<=~q;
endcase
end
end
endmodule
Specific Objective 3
Apply the Module Instantitation for digital design.
 Arithmetic Operator
module arithmetic (A, B, Q1, Q2, Q3, Q4);
input [3:0] A, B;
output [4:0] Q1;
output [3:0] Q2, Q3;
output [7:0] Q4;
reg [4:0] Q1;
reg [3:0] Q2, Q3;
reg [7:0] Q4;
always @ (A or B)
begin
Q1 = A + B; //addition
Q2 = A - B; //subtraction
Q3 = A / 2; //division
Q4 = A * B; //multiplication
end
endmodule
Relational Operator Contd..,
module relational (A, B, Q1, Q2, Q3, Q4);
input [3:0] A, B;
output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4;
always @ (A or B)
begin
Q1 = A > B; //greater than
Q2 = A < B; //less than
Q3 = A >= B; //greater than equal to
if (A <= B) //less than equal to
Q4 = 1;
else
Q4 = 0;
end
endmodule
Equality
module equality (A, B, Q1, Q2);
input [3:0] A;
input [3:0] B;
output Q1;
output Q2;
reg Q1, Q2;
always @ (A or B)
begin
Q1 = (A == B); //equality
if (A != B) //inequality
Q2 = 1;
else
Q2 = 0;
end
endmodule
Shift Operators

module shift (data, q1, q2);

input [3:0] data;
output [3:0] q1, q2;
parameter B = 2;
reg [3:0] q1, q2;
always @ (data)
begin
q1 = data << B; // logical shift left
q2 = data >> B; //logical shift right
end
endmodule
 Binary Counter
//Binary counter
module counter(Q , clock, clear);
// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q = 4'd0;
else
Q = (Q + 1) ; //Since Q is 4 bit, if value is
more than 15 its wrap around
end
DISCUSSION
MINDMAP
 Summary
• always and initial -- Basic Statements in Behavioral Modeling.
• All other behavioral statements appear only inside the always or initial statements.
• The Statement inside the always or initial cannot be nested (executes in sequentially)
• Sequential Block: All statements within the block are executed sequentially
• An Event is a change in the value on a register or a net.
• Blocking Statements are executed in the order they are specified in a sequential
block.
• Non Blocking assignments allow scheduling of assignments without blocking
execution of the statement that follow in a sequential block.
• Operator <= - specify non blocking assignments.
• Initial Statement executes only once during the entire simulation run.
 References
1. Samir Palnitkar, Verilog HDL, Pearson Education, 2ndEdition, 2004
2. Ming-Bo Lin, Digital System Designs and Practices using Verilog HDL and FPGAs,
Wiley, 2012.
3. http://www.asic-world.com/verilog/gate.html
Thank You!