UNIT V

ASICs
 ASIC
ASIC [“a-sick”] is an acronym for Application Specific Integrated Circuit.
As the name indicates, ASIC is a non-standard integrated circuit that is
designed for a specific use or application.
Generally an ASIC design will be undertaken for a product that will have a
large production run , and the ASIC may contain a very large part of the
electronics needed on a single integrated circuit.
Examples for ASIC Ics are : a chip for a toy bear that talks; a chip for a
satellite; a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU; and a chip containing a
microprocessor as a cell together with other logic
 ASICs
ASICs typically designed and used by a single company in a specific system.
They are incredibly expensive, time-consuming, and resource-intensive to
develop, but they do offer extremely high performance coupled with low power
consumption.
ASSPs
Application-specific standard parts (ASSPs) are designed and implemented in
exactly the same way as ASICs. ASSP is a more general-purpose device that is
intended for use by multiple system design houses. For example, a standalone
USB interface chip, ROM,RAM, would be classed as an ASSP.

SoC
System-on-Chip (SoC) is a silicon chip that contains one or more processor cores
-- microprocessors (MPUs) and/or microcontrollers (MCUs) and/or digital signal
processors (DSPs) -- along with on-chip memory, hardware accelerator functions,
peripheral functions, and (potentially) all sorts of other "stuff." ASIC contains one
or more processor cores then it's an SoC. ASSP contains one or more processor
cores then it's an SoC.

ASIC & ASSPs are Application Specific – every IC has an

ASIC Design Flow (RTL to GDSII)
 ASIC Design Flow
System Specification

Partitioning
ENTITY test is
Architectural Design
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design Clock Tree Synthesis

Physical Verification
DRC
LVS and Signoff Signal Routing
ERC

Fabrication
Timing Closure
Packaging and Testing

Chip

5
 1. Design Entry / Options

Schematic Design
Hardware Description Language (HDL) Based
Design
 Schematic Design
SPICE
•Small Design
PSPICE •Transistor Based
TSPICE Design
HSPICE
2. Logic Synthesis
 Elements of Logic Synthesis
 It is the process converting of high level description into gate level netlist.

 HDL Code to Netlist.

 Netlist- Interconnection between nodes. (Description of Logic Cells and their

interconnections)

 Synthesizer – Tool to Perform Synthesis

Synthesize Platform
 Physical Design Cycle/Flow
 The input of the physical design cycle is a circuit diagram and
the output is the layout of the circuit.

Circuit Partitioning

Floorplanning & Placement
Deadspace

Routing

v
Layout Compaction

Extraction and Verification

Basic scheme of cell-based design

• Planning
on chip
area
Basic scheme of cell-based design

to place cells

area to route wires

 Placement
• Mapping logical
gates (cells)
onto locations
for cells
Routing

route wires
 Contd..,
 Partitioning – Divide a large system into ASIC sized pieces
 Prelayout Simulation – Check to see if the design functions correctly
 Floor planning- area of each block can be estimated & arrange the blocks of
netlist on the chip
 Placement- Decide the exact locations of cells in a block
 Routing- Make the interconnections between modules

 Extraction – Determine the resistance and capacitance of the

Interconnect
 Post Layout Simulation - Check to see the design still works with the added
loads of the interconnect
 Physical verification
Physical verification is a process whereby an IC layout design
is checked via EDA software tools to see if it meets certain
criteria.

Verification involves DRC (Design rule check),

 LVS (Layout versus schematic),
ERC (Electrical Rule Check)
Parasitic Extraction
 DRC Check
•The Design Rule Checker helps ensure that a layout design conforms
to the physical constraints required to produce it.

•These constraints can be a requirement of the design itself, such as

reducing noise, or a requirement of the process used to produce the
design.

Steps
• Define or select a design rule.
• Run the design check using the defined or selected
rule.
• Load the results.
 ERC Check
 ERC (Electrical rule check) involves checking a design for all
electrical connections that are considered dangerous. This might
include checking for

• well and substrate areas for proper contacts and spacing thereby
ensuring
correct power and ground connections.
• unconnected inputs or shorted outputs.
LVS Check
• gates connected directly to supplies.

LAYOUT VERSUS
SCHEMATIC
 LVS Check
 Layout Versus Schematic (LVS) is the class of electronic design automation (EDA)
verification software that determines whether a particular integrated circuit layout
corresponds to the original schematic or circuit diagram of the design.

 Comparison: The extracted layout netlist is then compared to the netlist taken from
the circuit schematic. If the two netlists match, then the circuit passes the LVS check.

Used to Find out

•Shorts: Two or more wires that should not be connected have been and must be
separated.

•Opens: Wires or components that should be connected are left dangling or only
partially connected. These must be connected properly to fix this.

•Component Mismatches: Components of an incorrect type have been used (e.g. a low
Vt MOS device instead of a standard Vt MOS device)

•Missing Components: An expected component has been left out of the layout.

•Parameter Mismatch: Components in the netlist can contain properties.

 Parasitic Extraction
 Parasitic extraction is extracting
internal capacitance and resistances
effects in both the designed devices and
the required wiring interconnects of an
electronic circuit.

 Detailed device parameters, parasitic

capacitances, parasitic resistances and
parasitic inductances, commonly called
parasitic devices, parasitic components,
or simply parasitic.
 Mask Generation – GDSII / Stream

Physical
design
Data GDSII (Stream)

GDS- Graphic Database System

Masks

Wafer

30
 Fabrication
 Fabrication: Process includes lithography, polishing,
deposition, diffusion, etc., to produce a chip.

 Fabrication process consists of several steps and requires

various masks.

 Before the chip is mass produced, a prototype is made and

tested.
 Packaging, Testing and Debugging
 Packaging – Put together the chips on a PCB (Printed Circuit
Board) or an MCM (Multi-Chip Module)

 Each chip is then packaged and tested to ensure that it meets all
the design specifications and that it functions properly.
 Summary
•Logic Synthesis - RTL to Netlist.

• Netlist- Interconnection between nodes. (Description of Logic Cells and

their interconnections)

• Physical Synthesis – Netlist to Layout

• Physical verification is a process whereby an IC layout design is checked

via EDA software tools

• Parasitic extraction is extracting internal capacitance and resistances

• Tape Out Format of ASIC Flow - GDSII (Graphic Database System

Information Interchange)
 TYPES OF ASICs
ASICs

Semi Programmabl
Full Custom Custom e

Standard Gate Array PLDs FPGAs

Cell Based Based

Channel
Channeled Structured
less Gate
Gate Array Gate Array
Array
 Full-Custom ASICs
A Full custom ASIC is one which includes some
(possibly all) logic cells that are customized and all
mask layers that are customized.
 Each and Every Components designed by designer.
 Microprocessor is an example of a full-custom IC .
Designers spend many hours squeezing the most out
of every last square micron of microprocessor chip
space by hand.
 Contd..
 Customizing all of the IC features in this way allows designers to
include optimized memory cells
 Full-custom ICs are the most expensive to manufacture and to
design.
 More manufacturing lead time (the time required just to make
an IC not including design time) is typically eight weeks for a full-
custom IC.
 These specialized full-custom ICs are often intended for a specific
application so, we might call some of them as full-custom ASICs.
 Designer avoids using pretested and pre characterized cells for all
or part of that design.
 SEMI CUSTOM
ASICs , for which all of the logic cells are
predesigned and some (possibly all) of the mask
layers are customized are called semi custom ASICs.
Using the predesigned cells from a cell library
makes the design , much easier.
 There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii)Gate-array–based ASICs.
 Standard-Cell Based ASICs
• A cell-based ASIC (cell-based IC, or CBIC pronounced
sea-bick) uses predesigned logic cells (AND gates, OR
gates, multiplexers, and flip-flops, for example) known
as standard cells.
• One can apply the term CBIC to any IC
• Standard-cell areas (also called flexible blocks) in a
CBIC are built of rows of standard cells like a wall built
of bricks.
• Standard-cell areas may be used in combination with
microcontrollers or even microprocessors, known as
mega cells.
 Standard-Cell Based ASICs
 Mega cells are also called mega functions, full-
custom blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks (FSBs)
 Features Contd…
• All mask layer are customized – transistors and
interconnect (Placement & Routing)
• Custom Blocks can be embedded
• Manufacturing lead time is about 8 Weeks
• Reduces the design time
• Reduces the risk
 Disadvantages Contd…
• More Time or More expense of designing or buying
the standard-cell library

• Time needed to fabricate all layers of the ASIC for

each new design is difficult.
 GATE ARRAY BASED ASICs
 Transistors are predefined on the silicon wafer
 Predefined pattern of transistors is called the base array
 The smallest element that is replicated to make the base array is
called the base cell or primitive cell
 Top level interconnect between the transistors is defined by the
designer in custom masks - Masked Gate Array (MGA)
 Design is performed by connecting predesigned and characterized
logic cells from a library (macros)
 After validation, automatic placement and routing are used to
convert the macro-based design into a layout on the ASIC using
STATE ITS DIFFERENCE
 CHANNELED GATE ARRAY

 Only the interconnect is

customized.
 Interconnect uses
predefined spaces
between rows of base
cells.
 Manufacturing lead time is
between two days and
Similar to a CBIC - bothtwo use the rows of cells
weeks
separated by channels used for interconnect.
Difference is that the space for interconnect between
rows of cells are fixed in height in a channeled gate
array, whereas the space between rows of cells may be
 CHANNELLESS GATE ARRAY
This channel less gate-array architecture is now more widely used
The routing on a channelless gate array uses rows of unused
transistors.
The key difference between a channel less gate array and
channeled gate array is that there are no predefined areas set
aside for routing between cells on a channel less gate array.
Instead we route over the top of the gate-array devices.
We can do this because we customize the contact layer that defines
the connections between metal 1, the first layer of metal, and the
transistors.
 FEATURES

 Only the interconnect is customized.

 The interconnect uses predefined spaces between
rows of base cells.
 Manufacturing lead time is around two days to two
weeks.
 When we use an area of transistors for routing in a
channel less array, we do not make any contacts to the
devices lying underneath , we simply leave the
transistors unused.
CHANNELLESS GATE ARRAY
 Contd…
• The logic density ,the amount of logic that can be
implemented in a given silicon area is higher for channel
less gate arrays than for channeled gate arrays.

• This is usually attributed to the difference in structure

between the two types of array.

• In fact, the difference occurs because the contact mask is

customized in a channel less gate array, but is not usually
customized in a channeled gate array. This leads to denser
cells in the channel less architectures.

• Customizing the contact layer in a channel less gate array

allows us to increase the density of gate-array cells because we
can route over the top of unused contact sites.
 STRUCTURED GATE ARRAY
 Design combines some of the features of CBICs and
MGAs.
 Known as an embedded gate array or structured gate
array(also called as master slice or master image).
 Limitations of the MGA is the fixed gate-array base
cell - Implementation of memory, difficult and
inefficient.
 In an embedded gate array some of the IC area is set
aside and dedicate it to a specific function.
 This embedded area either can contain a different
base cell that is more suitable for building memory
 STRUCTURED GATE ARRAY
A structured or embedded gate-array die showing an embedded block
in the upper left corner
 FEATURES
 Only the interconnect is customized.
 Custom blocks (the same for each design) can be
embedded.
 Manufacturing lead time is between two days and two
weeks.
 An embedded gate array gives the improved area
efficiency and increased performance of a CBIC but
with the lower cost and faster turn around of an MGA.
 Disadvantages
 Disadvantage of an embedded gate array is that the
embedded function is fixed.
For example, if an embedded gate array contains an
area set aside for a 32 k-bit memory, but we only
need a 16 k-bit memory, then we may have to waste
half of the embedded memory function.
PROGRAMMABLE ASICs
 Programmable Logic Devices(PLD)
 A programmable logic device or PLD is electronic component
used to build reconfigurable (programmable) digital circuits.
 PLD has an undefined function at the time of manufacture.
 Programmed by the end user
 PLD- Field-Programmable Device (FPD) i. e., can be
programmed outside of the manufacturing environment.
 An IC that contains large numbers of gates, flip-flops, etc. that
can be configured or programmed by the user to perform
different functions is called a Programmable Logic Device
(PLD).
 Most of the programmable logic devices are erasable and
reprogrammable.
a) Allows “updating” a device or firmware,
correction of errors
 PLD - FEATURES
• No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macro cells that usually consist of
programmable array logic followed by a flip-flop or
latch
 Types of PLDs

• ROM(Read Only Memory)

Simple
• PLA(Programmable Logic Device) PLDs
• PAL(Programmable Array Logic)

• CPLD(Complex Programmable Logic Device)

• FPGA(Field Programmable Gate Array)

 Programmable Configurations
• Read Only Memory (ROM) - a fixed array of AND gates
and a programmable array of OR gates

• Programmable Array Logic (PAL) - a programmable array

of AND gates feeding a fixed array of OR gates.

• Programmable Logic Array (PLA) - a programmable array

of AND gates feeding a programmable array of OR gates.

• Complex Programmable Logic Device (CPLD) /Field-

Programmable Gate Array (FPGA)
 ROM, PAL and PLA Configurations
Fixed Programmable
Inputs Programmable Outputs
AND array
(decoder) Connections OR array

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

 FPGA
 FPGA- Field Programmable Gate Array – Integrated Circuit.
 The designed to be configured by a customer or a designer after manufacturing
hence "field-programmable".
 FPGAs are programmable semiconductor devices
They consist of an array of logic blocks that are configured using software.
 Programmable I/O blocks surround these logic blocks. Both are connected
through programmable interconnects.
 FPGAs can be programmed to the desired application or functionality
requirements.
 FPGAs allow designers to change their designs .
Even after the end product has been manufactured and deployed in the field.
 FPGA configuration is generally specified using a hardware description
language (HDL).
FPGA DIE
Mindmap
 SUMMARY

Full Custom ASIC

•Each transistor hand drawn, (polygon pushing)
•Analog parts are done this way
•Highest performance, longest design time
•Hand optimized parts of high-end uPs
•Full set of masks needed

Standard Cell ASIC

•Predesigned (standard) cells in a library are used
•These cells are connected together to form the design
•High performance, much shorter design time than full custom
•Most digital ASICs are designed this way
•Usually uses HDLs with logic synthesis
•Full set of masks needed
 SUMMARY

Gate Array ASIC

•Predrawn transistors are on a die
•These transistors are connected together to form cells
•The cells are connected to form a design
•Usually digital in nature
•Lower performance, but very quick to fabricate
•Only metalization masks are needed
•Usually uses HDLs with logic synthesis
 TYPES OF ANALYSIS

DC Analysis
AC Analysis
Transient (Time Domain) Analysis
 DC Analysis
DC Operating Point of the circuit .
DC Analysis is to determine the transient initial conditions.
Determine the linearized, small-signal models for nonlinear
devices.
It is used to generate dc transfer curves (Vout Vs Vin): a specified
independent voltage or current source is stepped over a user-
specified range.
 DC Output variables are stored for each sequential source value.
 Sweep any source value.
 Sweep temperature range
 Small Signal Transfer Function
 AC Analysis

Computes the ac output variables as a function of

frequency.

Resultant linear circuit is then analyzed over a user-

specified range of frequencies.

Desired output of an ac small-signal analysis is usually a

transfer function (voltage gain, transimpedance, etc).
 Transient Analysis
Transient analysis is dependent on time, it uses different analysis
algorithms.
Computes the transient output variables as a function of time
(Vout Vs time(ms)) over a user-specified time interval.
Example
The Transient response analysis causes the response of the circuit to
be calculated from TIME = 0 to a specified time.
.tran 20ns 1000ns
The analysis is to span the time interval from 0 to 1000
nanoseconds and values should be reported to the simulation output
 Difference Between Analysis
DC AC Transient
 Used to find  Used to find  Used to analyze
Operating Point Response of AC analysis Response of output
Small Signal Transfer  Print magnitude and variable
Function phase angles of output Initial Condition for
DC Sweep voltages and currents transient analysis
DC Parametric Sweep  Finding Behavior of the
Circuit

Function of Voltage & Function of Frequency Function of time

Current
X Axis- Voltage/Current X Axis- Frequency X Axis-Time
Y Axis - Voltage/Current Y Axis – Magnitude or Gain Y Axis - Voltage/Current

Eg: DC Transfer Eg: Bode Plot Eg: Logic Gates

Characteristics Simulation,
Characteristics of Circuit.
 .DC (DC Sweep)

DC Sweep also known as dc transfer characteristics.

 The Input variable is varied over a range of values.

For each values, the dc operating point and small

signal dc
gain by calling small signal transfer function capability.
 .PARAM (DC Parametric Sweep)
To Vary a parameter and to evaluate its effect on the DC
analysis.

 The Parameter could be a circuit element such as R,L,C

and their model parameters.
.DC PARAM SWNAME SWMIN SWMAX SWINC

Where SWNAME – Sweep Parameter Name

SWMIN - Minimum Value of Sweep Parameters
SWMAX - Maximum Value of Sweep Parameters
SWINC – Sweep Increment