QUESTION BANK UNIT 3 - Computer Organization and Architecture
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09 laxmikant doijodeQUESTION BANK UNIT 3 - Computer Organization and Architecture
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09 laxmikant doijodeSemester: IV
Subject Name: Computer Organization and Architecture
Unit 3
1a. Explain different addressing modes of 8086 microprocessor.
Answer:
1. Immediate Addressing Mode:
o The operand is specified in the instruction itself.
o Example: MOV AX, 1234H (1234H is directly moved to AX)
2. Register Addressing Mode:
o The operand is in a register.
o Example: MOV AX, BX (content of BX is moved to AX)
3. Direct Addressing Mode:
o The operand's memory address is specified directly.
o Example: MOV AX, [1234H] (content of memory location 1234H is moved to
AX)
4. Register Indirect Addressing Mode:
o The operand's memory address is in a register.
o Example: MOV AX, [BX] (content of memory location pointed to by BX is
moved to AX)
5. Based Addressing Mode:
o Combines a base register and an offset.
o Example: MOV AX, [BX+1234H] (content of memory location BX+1234H is
moved to AX)
6. Indexed Addressing Mode:
o Combines an index register and an offset.
o Example: MOV AX, [SI+1234H] (content of memory location SI+1234H is
moved to AX)
7. Based-Indexed Addressing Mode:
o Combines a base register, an index register, and an offset.
o Example: MOV AX, [BX+SI]
8. Relative Addressing Mode:
o The effective address is obtained by adding a constant value to the current
value of the program counter (PC).
o Example: JMP LABEL (the jump is to the address specified by LABEL, relative
to the PC)
1b. Explain the concept of segmentation and its importance in 8086.
Answer:
Segmentation:
• Segmentation divides the memory into different segments, each having a specific
purpose.
• In 8086, memory is divided into four segments: Code Segment (CS), Data Segment
(DS), Stack Segment (SS), and Extra Segment (ES).
• Each segment has a base address stored in a segment register.
Importance:
1. Modularity: Allows logical separation of code, data, and stack.
2. Memory Management: Facilitates efficient memory usage and management.
3. Security: Segments can be protected, allowing control over access permissions.
4. Large Programs: Enables handling of programs larger than 64 KB by dividing them
into manageable segments.
2a. Explain the instruction set of 8086 microprocessor.
Answer:
The instruction set of the 8086 microprocessor includes several categories:
1. Data Transfer Instructions:
o MOV: Move data.
o PUSH: Push data onto the stack.
o POP: Pop data from the stack.
2. Arithmetic Instructions:
o ADD: Add.
o SUB: Subtract.
o MUL: Multiply.
o DIV: Divide.
3. Bit Manipulation Instructions:
o AND: Logical AND.
o OR: Logical OR.
o XOR: Logical XOR.
o NOT: Logical NOT.
4. Control Transfer Instructions:
o JMP: Jump.
o CALL: Call a procedure.
o RET: Return from a procedure.
5. String Manipulation Instructions:
o MOVS: Move string.
o CMPS: Compare string.
o SCAS: Scan string.
6. Processor Control Instructions:
o STC: Set carry flag.
o CLC: Clear carry flag.
o HLT: Halt the processor.
2b. Explain the memory interfacing with 8086.
Answer:
Memory interfacing with the 8086 involves connecting memory chips to the microprocessor
in a way that ensures data can be read and written correctly.
Key Points:
1. Address Bus: 20-bit address bus (A0-A19) to address 1MB of memory.
2. Data Bus: 16-bit data bus (D0-D15) for data transfer.
3. Control Signals:
o RD (Read): Indicates data read operation.
o WR (Write): Indicates data write operation.
o M/IO (Memory/Input-Output): Differentiates between memory and I/O
operations.
Steps:
1. Address Decoding: Ensure the correct memory chip is selected based on the address.
2. Control Signal Generation: Generate appropriate control signals to perform
read/write operations.
3. Data Transfer: Facilitate data transfer between the processor and memory.
3a. Explain how to interface I/O devices with 8086.
Answer:
I/O Interfacing involves connecting input/output devices to the 8086 microprocessor.
Methods:
1. Memory-Mapped I/O:
o Uses the same address space for memory and I/O devices.
o I/O devices are treated as memory locations.
o Example: MOV AX, [IO_ADDRESS]
2. I/O Mapped I/O (Isolated I/O):
o Separate address space for I/O devices.
o Special instructions IN and OUT are used.
o Example: IN AL, DX
Steps:
1. Address Decoding: Ensure correct I/O device is selected.
2. Control Signals: Generate IO/M, RD, and WR signals.
3. Data Transfer: Use data bus for data exchange.
Example:
assembly
Copy code
MOV DX, PORT_ADDRESS ; Load port address into DX
IN AL, DX ; Read from the port
OUT DX, AL ; Write to the port
3b. Explain the function of 8255 PPI with its pin diagram.
Answer:
The 8255 Programmable Peripheral Interface (PPI) is used to interface peripheral devices
with the microprocessor.
Pin Diagram:
mathematica
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+-------------------+
| D0 - D7 | Data Bus
| RD | Read Signal
| WR | Write Signal
| CS | Chip Select
| A0 - A1 | Address Lines
| PA0 - PA7 | Port A
| PB0 - PB7 | Port B
| PC0 - PC7 | Port C
| RESET | Reset Signal
+-------------------+
Function:
• Ports: Three 8-bit ports (A, B, C) which can be programmed as input or output.
• Control Word: Determines the mode of operation for the ports.
Modes:
1. Mode 0: Basic input/output.
2. Mode 1: Strobed input/output.
3. Mode 2: Bi-directional data bus.
Example:
assembly
Copy code
MOV AL, 80H ; Set port A as input
OUT CONTROL, AL ; Send control word to control register
IN AL, PORT_A ; Read data from port A
4. Explain the concept of DMA with a neat diagram.
Answer:
Direct Memory Access (DMA) allows peripheral devices to transfer data directly to/from
memory without CPU intervention.
Diagram:
lua
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+-----------+ +-------------+
| CPU | | Peripheral |
| | | Device |
| +-------+ | | +---------+ |
| | | | | | | |
| | Memory|<--------->|DMA | |
| | | | DMA |Controller| |
| +-------+ | | +---------+ |
+-----------+ +-------------+
Concept:
1. DMA Controller: Manages the data transfer.
2. Bus Arbitration: DMA controller takes control of the bus.
3. Data Transfer: Data is transferred directly between memory and peripheral.
Steps:
1. CPU Initiates: CPU configures DMA controller.
2. Bus Request: DMA controller requests bus access.
3. Bus Grant: CPU grants bus control.
4. Transfer: DMA controller performs the transfer.
5. Interrupt: DMA controller signals the completion to CPU.
Benefits:
• Reduces CPU overhead.
• Faster data transfer.
• Efficient for large data blocks.
5. Explain the architecture and function of 8257 DMA controller.
Answer:
The 8257 DMA Controller manages DMA operations for data transfer between memory and
peripherals.
Architecture:
• 4 DMA Channels: Allows up to 4 devices to use DMA.
• Address Registers: Stores address for data transfer.
• Word Count Registers: Stores the number of bytes to transfer.
• Control Logic: Manages the DMA operations.
Function:
1. Initialization: CPU initializes DMA controller.
2. Request: Peripheral requests DMA service.
3. Address Generation: Generates address for memory access.
4. Data Transfer: Transfers data between memory and peripheral.
5. Interrupt: Notifies CPU after completion.
Modes:
1. Single Transfer Mode: One byte at a time.
2. Block Transfer Mode: Block of data.
3. Demand Transfer Mode: As per peripheral demand.
4. Cascade Mode: For multiple 8257s.
Example:
assembly
Copy code
MOV AL, 100H ; Set DMA mode
OUT DMA_CONTROL, AL ; Send to control register
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