11/28/2016

Time to Examine a Processor’s Control Signals in Detail

University of Illinois at Urbana-Champaign
Dept. of Electrical and Computer Engineering Recall the control unit FSM
◦ inputs: signals from the datapath
ECE 120: Introduction to Computing ◦ outputs: control signals for the datapath
Let’s look at the control signals for Patt
and Patel’s LC-3 datapath (Figure C.3).
We ignore control signals associated with
LC-3 Control Signals interrupt and privilege.
Those of you who take ECE391 will cover
these concepts in the context of the x86 ISA.

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We Consider Five Groups of LC-3 Control Signals Register Loads Control Updates to Register Values

Let’s split the control signals into five groups: The first group: register loads.
◦ register loads: Each register load signal controls
does a register take a new value? one or more registers.
◦ bus gating: Each signal is set iff the RTL for the
should a value be copied onto the bus? current FSM state changes that
◦ mux selection register’s value.
◦ ALU function selection In other words, the load signal is
◦ memory operation ◦ 1 if the register appears on the
left side of an RTL expression,
◦ and is 0 otherwise.

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Register Load Signals are Set iff a Register Should Change Register Load Signals are Set iff a Register Should Change

Load signals include: ◦ LD.REG

(register file;
which register
◦ LD.MAR depends on
DR input)
◦ LD.MDR ◦ LD.CC
(all three; logic
◦ LD.IR calculates
values based
on bits on bus)
◦ LD.BEN ◦ LD.PC
(not shown)

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What Values Do the Registers Write? Bus Gating Signals Determine the Value on the Bus

Most registers’ new values come from The second group: bus gating.
the bus: MAR, IR, REG, and CC. Recall that tri-state buffers are
MDR’s new value comes either used to write values onto the bus.
from the bus or from the memory. Each bus gating control signal is wired to
the enable inputs of 16 tri-state buffers
PC’s new value comes from a mux that write to the bus.
(PCMUX), with one mux input from the bus.
At most one bus gating signal can be a 1.
Finally, BEN (branch enable) is loaded
based on CC and IR. All others must be 0 to avoid
short circuits through the bus.

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Bus Gating Signals Determine the Value on the Bus Mux Selection Signals Control Mux Outputs

Bus gating signals The third group: mux selection.

include:
Muxes are used to control
◦ GatePC
◦ the value loaded into the PC,
◦ GateMDR
◦ the destination register in the register file,
◦ GateALU
◦ source register 1 from the register file, and
◦ GateMARMUX
◦ memory address generation (three muxes).
MARMUX is
When mux outputs are not used,
used for memory
their select inputs can be don’t cares.
address generation.

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PCMUX Controls the Value Loaded into the PC DRMUX Controls the Destination Register
PCMUX controls the value DRMUX controls the destination register,
loaded into the PC, and is and is thus only meaningful when
thus only meaningful LD.REG = 1.
when LD.PC = 1. Choices include:
Choices include: 00 IR[11:9]
00 PC + 1
01 R7
01 bus 10 R6
10 address generation
adder (used for BR and JMP) The instructions that we covered only
make use of the first option.

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SR1MUX Controls the First Source Register Two Muxes are Used for the Memory Address Adder

SR1MUX controls source register 1 from ADDR1MUX

the register file, which is selects between
used by the ALU and 0 PC
by ADDR1MUX. 1 SR1
Choices include: ADDR2MUX
selects between
00 IR[11:9] (stores) 00 0
01 IR[8:6] (ALU ops, JMP, LDR/STR) 01 SEXT(IR[5:0]) from SR1

10 SEXT(IR[8:0])
10 R6 (nothing that we have seen) 11 SEXT(IR[10:0])

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And a Third Mux is Used to Select the Address Address Generation is Not Always Used
Finally, MARMUX Notice that
selects between ADDR1MUX and
0 ZEXT(IR[7:0]) ADDR2MUX are used
1 address by both PCMUX and
generation
adder by MARMUX.
The instructions that MARMUX is useful
we explained* use only
the second option. only when
from SR1
GateMARMUX = 1. from SR1

*TRAP’s implementation
uses the first option.

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The LC-3 ALU Supports Four Functions The LC-3 Memory Requires Two Signals
The fourth group of control signals: The fifth group of control signals:
ALU function selection. memory operation.
The ALUK control signals support for functions,
including passing the A input to the output. The LC-3 memory requires two controls:
00 ADD MIO.EN tells the memory to operate
01 AND
(1 to do a read or a write).
10 NOT A When MIO.EN = 1,
11 PASS A ◦ R.W = 1 for a write, and
◦ R.W = 0 for a read.
ALUK is meaningful only when GateALU = 1.

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We Consider Twenty-Five Control Signals in All

How many control signals do we have?

◦ register loads 7
◦ bus gating 4
◦ mux selection 10
◦ ALU function selection 2
◦ memory operation 2
TOTAL 25

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