Design Rules for Quantum-dot Cellular Automata

Weiqiang Liu, Liang Lu and Máire O’Neill Earl E. Swartzlander Jr.

Institute of Electronics, Communications and Information Technology Department of Electrical and Computer Engineering
Queen’s University Belfast The University of Texas at Austin
Queen’s Road, Belfast, BT3 9DT, UK Austin, Texas, 78712, USA
[email protected], {l.lu, m.oneill}@ecit.qub.ac.uk [email protected]

Quantum Dot Electron

Abstract—As a promising alternative to CMOS technology,
QCA circuit design has been extensively studied in recent years.
However, although a concrete set of design rules exist for
integrated circuit design, little attention has been paid to the “ 0” “ 1” “ 1”
“ 0”
design rules necessary for efficient QCA circuit design. This paper (a) Regular QCA Cell (900) (b) Rotated QCA Cell (450)
compiles a set of important QCA design rules which include D-1 D-1 D-1 D-1
layout design rules, timing rules and some special rules for QCA
technology to ensure QCA circuits function correctly and reliably. Input Output
These rules will promote the development of practical and
Clock zone 0 Clock zone 1 Clock zone 2 Clock zone 3
efficient QCA systems. A GF (2m ) multiplier design is proposed Z-1
as a case study to illustrate these design rules. (c) QCA Wire

Fig. 1. Schematics of QCA cell and wire

I. M OTIVATION
The new computing paradigm, Quantum-dot Cellular Au-
tomata (QCA) [1], has been extensively studied in recent The paper is organized as follows: Section II presents the
years. It is a promising alternative to CMOS technology to background of QCA. Design rules including layout rules,
help maintain the trend predicted by Moore’s Law. QCA has timing rules and special rules are compiled and discussed in
significant advantages of fast speed, high density and low Section III. In Section IV, a GF (2m ) multiplier is designed
power consumption. Therefore, it is an attractive technology as a case study of the design rules. Conclusions are given in
for the development of the digital circuits or even SoC systems Section V.
[2]. To date, only simple QCA components and small circuits
have been fabricated and demonstrated in the laboratory. More II. BACKGROUND OF QCA
sophisticated QCA circuits including arithmetic circuits [3], The basic computing device in QCA is a square nano-
memory and a simple processor [2] have been designed and structure with four quantum dots in each corner. The QCA
verified by simulation tools. cell is occupied by two electrons that can tunnel between
When mapping a digital design to majority logic-based these four quantum dots. The two electrons tend to occupy
QCA circuits, knowledge of QCA layout and timing con- antipodal sites within the cell due to the Coulombic repulsion.
straints is necessary. The objective of defining design rules Tunneling action only occurs within the cell and no tunneling
is to simplify mapping from a circuit schematic to an actual happens between cells. Therefore, two ground states of charge
layout implementation. Design rules have played an important configuration in QCA cells can be used to represent binary ”0”
role in the development of CMOS technology. A CMOS and ”1” with polarizations of -1 and +1, respectively. Two
design rule set specifies certain geometric and connectivity types of QCA cells are shown schematically in Fig.1 (a) and
restrictions to ensure sufficient margins to take into account (b). The rotated 450 cells are used for coplanar crossing. In
variability in the semiconductor manufacturing processes, so contrast to a physical wire, a QCA ”wire” is a chain of cells
as to ensure that circuits function correctly. Developing design where the cells are coupled to each other as shown in Fig. 1
rules for emerging QCA technology will help the designer (c).
understand the QCA features and efficiently achieve correct The logic elements of QCA are an inverter and majority
functionality and reliability. This will ultimately promote the gate. An inverter is designed by positioning cells diagonally
development of practical QCA systems. from each other to achieve the inversion functionality. A ma-
Due to the unique clocking scheme used in QCA, there is jority gate consists of five QCA cells that realize the function
a critical relationship between the layout and timing, referred of M (a, b, c) = ab + bc + ac. Two-input AND gate and OR
to as ”layout = timing” [4]. Consequently, the timing rules are gates can be designed by fixing one of the majority gate inputs
as important as layout in QCA. Both the layout and timing to ”0” and ”1”, respectively. In combination with inverters,
rules are discussed in this paper in addition to some special these two logic components can be used to implement any
rules for QCA technology. logic function.

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 INPUT
In contrast to CMOS, there are four phases in QCA clocking
rather than two phases of high and low. The four phases exist Zone 0
0 1 0 1
in each QCA clocking zone and there is a 900 phase shift
Zone 1
from one clocking zone to the next. The cells are in the
HOLD phase when the clock signal is low and in the RELAX
Zone 2
phase when the clock signal is high. When the clock signal
changes from high to low or low to high, the cell is in the Zone 3
SWITCH or the RELEASE phase, respectively. Information
is transferred during the SWITCH phase. A cell is latched OUTPUT

while it is in the HOLD phase. Since the cells in one clocking Fig. 2. The distorted waveforms from one-cell clocking zones
zone become latched and remain in this state until the cells
are latched in the next clocking zone, a clocked QCA wire
can be treated as a chain of D-latches. Therefore, information
is transferred and processed in a pipelined manner. Let Z −1 r
r1
and D−1 indicate one clock cycle delay and one clocking θ
zone delay, respectively. As shown in Fig. 1 (c), the following
relationship holds: Z −1 = D−4 = 4 × D−1 .
r2=2r1

III. QCA D ESIGN RULES (a) (b)

A. Layout Design Rules Fig. 3. Relationship between QCA cell position and kink energy
In CMOS, design rules are a series of parameters that
enable the designer to verify the correctness of a mask set.
A design rule set specifies certain geometric and connectivity 2) The Minimum Number of Cells in a Single Clocking
restrictions to ensure that circuit components work correctly. Zone: A clocking zone can contain only a single QCA cell.
Following this concept, some layout design rules for QCA are However, the waveform of a one-cell clocking zone can
developed as follows: become distorted and cascading of this kind of clocking zone
1) The Maximum Number of Cells in a Single Clocking could lead to incorrect results [6]. In the wire simulation shown
Zone: QCA computation is achieved by relaxing the physical in Fig. 2, the signals in clocking zone 1 are distorted and
array to its ground state. Computing with the ground state has become worse in clocking zone 2 and finally lead to a wrong
the undesired accompanying effect of being temperature sen- output in clocking zone 3. To observe correct outputs from a
sitive. Thermal fluctuations may excite the QCA array above circuit, it is recommended that clocking zones should consist
its ground state, which may produce an incorrect output. To of at least two cells. For a long QCA wire, the cells should be
achieve robust operation, the excitation energy must be greater put into different clocking zones and divided evenly to avoid
than kB T . Kink energy (denoted as Ek ) is the excitation the effects of a one-cell clocking zone and ensure robust signal
energy, which introduces a ”kink” in the polarization of the transmission.
wire. A complete analysis of thermodynamic effects on a linear 3) The Minimum Wire Spacing for Signal Separation: QCA
array is provided in [5]. The more cells in a single clocking cells interact through a quadrupole-quadrupole interaction
zone, the more mistakes may happen. The limitation on the which decays inversely by a power of five of the distance
number of QCA cells to avoid undesired kink is given by [5]: between cells. Referring to Fig. 3 (a), the relationship between
Ek the cell position and the kink energy is as follows [7]:
N ≤ e kB T (1)
Ek (r, θ) ∝ r−5 cos(4θ) (2)
N is the number of cells in the array, kB is the Boltzmann
constant and T is the operating temperature. The maximum Therefore, the kink energy will decay rapidly with distance
operating temperature is affected by the QCA cell size. As cell and the effective neighborhood of interacting cells can be made
size decreases, the energy separations between states increase small. If two QCA cells are aligned properly with a center-to-
and higher temperature operation is possible [5]. center distance of one cell size as shown in Fig 3 (b), the kink
Long QCA wires also result in an increased delay in signal energy between them is proportional to r1 −5 . For two cells
propagation and switching, which can significantly reduce with center-to-center distance of two cells, the kink energy
the overall operating speed. Therefore, the clock rate can is proportional to 321
r1 −5 which is 32 times smaller. Thus, a
be improved if a small number of cells is set into a single space of one QCA cell size is sufficient separation between
clocking zone. The length of QCA wire in a single clocking two wires carrying different signals.
zone is limited due to the thermodynamic effects and clock 4) Crossover Option: A unique property of QCA layout
rate considerations. As a result, the long QCA wires have to is the possibility of implementing crossovers by using only
be partitioned into different clocking zones to ensure correct one layer, known as coplanar crossing, as shown in Fig. 4 (a).
functionality. As the limitation relies on future fabrication Coplanar crossing uses both 450 and 900 cells . The two types
technology, it can be set as a design parameter at this stage. of cells do not interact with each other when they are properly

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 1
as well as its output should be in the successive clocking zone

0
450 wire
[(i + 1 )mod4 ]. As a result, at least one clocking zone delay
1
1
(denoted as D−1 ) is required in a majority gate. Thereupon,
0
0 0 1 the minimum delays in its derivatives, such as OR and AND
900 wire
1 gates are also one clocking zone delay (D−1 ). However, the
QCA inverter have only one input that does not need to be
synchronized. So there is no delay in QCA inverter.

0
1

(a) Coplanar Crossing (b) Multi-layer Crossing 2) Clocking Zone Assignment Rule: In QCA circuits even
combinational logic, as defined in CMOS, should be synchro-
Fig. 4. Two crossover options in QCA
nized. It is easy to assign clocking zones to a signal-forward
architecture in QCA, as this only requires adding delays,
but for conventional sequential circuit architectures, especially
aligned. However, they can easily fail due to low robustness those with feedback, the clocking zone assignment may be
[2] and fabrication issues [8]. Another alternative is multi-layer very difficult. However, the cut-set retiming method used by
crossing, which uses more than one layer of cells similar to the the authors in [9] provides a feasible timing methodology to
routing of metal wires in CMOS technology as shown in Fig. 4 assign correct clocking zones in complicated architectures with
(b). The extra layers of QCA are believed to be useful as active feedback. By performing delay-transfer and time-scaling, the
components of the circuits and consume less area compared timing relationship can be re-balanced to assign the clocking
to coplanar circuits [2]. In QCADesigner, the commonly used zones in an efficient way.
QCA simulator, multi-layer crossing is adopted to achieve a
robust simulation result. Nevertheless, multi-layer crossovers C. Special Rules for QCA
are not easy to fabricate. As a result, the option on crossover 1) Majority Logic Reduction: The logic primitive used in
is still an open question. The correct answer heavily depends QCA is the majority gate. Although the conventional AND and
on future fabrication technology. OR gates can be derived from the majority gate, it is costly in
5) The QCA Equivalent λ-Rule: In CMOS, λ-based layout terms of cell-count to design QCA circuits by directly mapping
design rules were originally devised to simplify the industry from the equivalent CMOS design. The majority logic based
micron-based rules and to allow scaling capability for various reduction method [10] can significantly reduce the complexity
processes. The λ-rule specifies the layout constraints in terms of QCA circuits. A QCA design should be optimized using
of a single parameter and allows linear, proportional scaling majority logic reduction before translating it into the layout.
of all geometrical constraints. In developing QCA design 2) Systolic Design: Systolic architectures involve an ar-
rules, the equivalent QCA λ-rule is a good starting point. The rangement of processors in an array where data flows syn-
previous discussions show that QCA design rules such as the chronously across the array between neighbours, usually with
maximum number of cells in a clocking zone and the minimum different data flowing in different directions. Each processor
wire spacing are related to the cell size. As QCA layouts are at each step takes input data from its neighbours, processes
built from cells and the size of a QCA cell determines the it and, in the next step, outputs the results. The features of
geometry of the actual design, QCA designs can be transferred systolic architectures in terms of synchrony, deep pipelines and
from one fabrication technology to another by scaling up or local interconnection are particularly suitable for accommo-
down the size of the QCA cell, which in effect is the meaning dating the special timing requirement in QCA circuits. When
of the λ-rule in CMOS. The future ”λ-rule” for QCA circuit applying systolic architectures to QCA, significant benefits
design could be defined according to the size of a QCA cell, can be achieved, even more so than when applied to CMOS-
or perhaps the cell size itself could be used as the equivalent based technology [11]. Therefore, systolic architecture design
λ. is preferred in QCA technology.
B. Timing Design Rules IV. C ASE S TUDY- A GF (2m ) M ULTIPLIER
A successful QCA layout is largely determined by a proper To illustrate the benefits of the above design rules, a QCA
clocking zone assignment due to the unique ”layout = timing” systolic architecture of GF (2m ) multiplier using polynomial
aspect of QCA. Therefore, when considering QCA design basis representation has been designed based on the CMOS
rules, the timing rules are as important as the layout rules. architecture proposed in [12]. A data flow graph of the systolic
1) Logic Component Timing Rule: The timing constraint GF (2m ) multiplier is shown in Fig. 5. The result, Ri , indicates
on a QCA majority gate is that all three inputs are expected a 3-input logic XOR operation (i.e., a full adder without carry-
to reach the device cell (central cell) at the same time in out, which has been optimized using majority logic reduction
order to have fair voting. If all three input wires are equally [10]) and the circles with Bi (the parallel inputs) and Pi (the
long, the device cell can be within the same clocking zone modulo) indicate the logic AND operation. The architecture
as the inputs. However, in practice, the length of input wires is not easy to design in QCA; however, by applying the rules
is usually different. Therefore, these three inputs should be discussed in this paper, a functionally correct and robust design
designed with the same clocking zone i , and the majority gate can be achieved and verified in QCADesigner [2].

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 B3 B2 B1 B0
Ai B3 B2 B1 B0
Ai
D-4 D-4 D-4
R3 R2 R1 R0 0

D-4
P3 P2 P1 P0
D-4 -4 -4
D D

Fig. 5. Data Flow Graph of a systolic GF (2m ) multiplier architecture

R3 R2 R1 R0
CUT 3 CUT 4 CUT 5
P3 P2 P1 P0
-4
D
CUT 2 D-3 Fig. 7. The layout of a 4-bit QCA GF (2m ) multiplier
D-2
D-1
Ai B3 B2 B1 B0 CUT 1
D-1

D-1

D-1

D-1

D-3 D-3 D-3

× × × × 0
D-1

D-1

D-1

D-1

CUT 6
D-3 P P2 P1 P0
3
D-4 D-5 D-6

Fig. 6. Applying cut-set retiming method to assign clocking zones Fig. 8. Simulation of R = (A × B)modP = x3 + x = (1010)2 = (10)10

First, the cut-set retiming method is used to achieve a proper R EFERENCES

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