RTL Design of 16-Bit Processor

Abhishek M B1, Gopal2, Kabilan D3, Gangappa Sattapa Kurali4, K Rithesh5 and Bindu H M6
1
Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]
2
Department of Electronics and Telecommunication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]
3
Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]
4
Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]
5
Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]
6
Department of Electronics and Communication Engineering
Dayananda Sagar College of Engineering
Bengaluru, India.
[email protected]

Abstract. In this project, a 16-bit processor is designed and implemented using

Verilog HDL, with an emphasis on the fundamentals of digital hardware design
and processor architecture. The CPU supports 22 different instructions and uses
a Reduced Instruction Set Computing (RISC) architecture. The design maxim-
ises efficiency by distinct instruction and data memory processing by utilising
the Harvard architecture.

A significant feature is the employment of a test bench to thoroughly verify the

processor's operation and performance in conjunction with a control finite state
machine (FSM) to supervise instruction execution cycles. In order to facilitate
debugging and comprehension, the project places a strong emphasis on modular
design, which divides the processor into smaller, more understandable parts.

Developing an effective processor with a range of arithmetic, logic, memory,

and branching operations is one of the project's goals. A barrel shifter allows for
more efficient shifting operations, and advanced instructions like ASR, ROR,
and MOVETOP are included for faster execution.
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Error detection systems provide reliability, and branch instructions such as BL LABEL im-
prove subroutine linkage.

The procedure entails establishing the design criteria for the processor, creating separate mod-
ules for the decoder, instruction memory, data memory, and processor, and then combining
these modules into a single, cohesive system. To make sure the CPU satisfies its design para-
meters and operates as intended, a thorough test bench is employed for testing and verifica -
tion.

The goal of this project is to serve as a teaching tool by on the complexities of processor
design and the real-world uses for Verilog in hardware development.

Keywords: RISC, Harvard, Error Detection, FSM.

1 Introduction

Nowadays, it is essential to comprehend and develop 16-bit processors in a simpli-

fied manner. These processors are great teaching aids because they make it easier for
engineers and students to understand the fundamentals of computer architecture,
which is necessary to deal with more complex systems. The 16-bit processors are
important in the world of embedded systems and the Internet of Things. Their ability
to balance performance and resource consumption makes them perfect for low-
power, economical applications like home automation, smart sensors, and basic
industrial controls.

It is impossible to overestimate the importance of comprehending and building

streamlined processors like the 16-bit RISC model in the quickly changing world of
technology today. With the growing prevalence of computing devices, ranging from
potent servers to small Internet of Things sensors, it is imperative to customize pro -
cessor design to meet the demands of individual applications. A 16-bit processor
that has been simplified is a great teaching tool because it helps engineers and stu-
dents learn the fundamentals of computer design, which is necessary to go on to
more complicated systems.

The requirement to comprehend and impart basic principles of processor architec-

ture and digital hardware development gives rise to the demand for a more straight-
forward 16-bit CPU. This kind of processor is an excellent teaching tool because it
gives novices and students a reasonable foundation on which to understand the com-
plexities of instruction sets, computer architecture, and the operation of different
digital components. Furthermore, in low-power and resource-constrained applica-
tions, where complicated 32- or 64-bit processors are redundant, such a CPU can be
employed.
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The project provides a hands-on approach to learning the core ideas of processor
architecture and digital hardware design by focusing on the design and implementa-
tion of a simplified 16-bit processor using Verilog HDL [5].

2 Literature Survey

No Reference Paper Summary

1. “Design of 16 Bit RISC Processor and Im This paper outlines a high-performance RISC microprocessor
plementation using MIPS Technique”, Ra with a five-stage pipeline, designed to swiftly execute a limited
kesh C R, Chetan S, J S Baligar. Scholars set of instructions. Utilizing Verilog HDL, ModelSim 6.4 c, an
Journal of Engineering and Technology, I d Xilinx tools, the design was simulated and synthesized, then
SSN 2347-9523 (Print) | ISSN 2321- implmented on an FPGA. Key features include the five pipe-
435X (Online). line stages and components like the ALU, Control Unit, and Pr
ogram Counter.

2. “Design of 16-bit RISC Processor”, Supr This paper presents a 16-bit RISC processor with separate me
aj Gaonkar, Anitha M. International Jour- mory for data and instructions. It supports 16 instructions, thre
nal of Engineering Research & Technol- e addressing modes, and has 16 general-purpose registers. The
ogy (IJERT) Vol. 2 Issue 7, July – 2013 I processor includes a 16-bit ALU for arithmetic and logical op-
SSN: 2278-0181. erations and flag registers for carry, zero, and parity. Designed
in Verilog, the processor was tested and integrated using Xil-
inx ISE 10.1 and Modelsim 10.2.

3. “Design of a 16-Bit Harvard Structure RI The project involves designing and implementing a 4-stage pip
SC Processor in Cadence 45nm Technol- elined RISC processor using MIPS architecture. It employs clo
ogy”, Chandran Venkatesan, Thabsera Su ck gating to reduce power consumption, increas-
lthana M, Sumithra M.G, Suriya M. 2019 ing system reliability and speed. The processor, coded in Ver-
5th International Conference on Ad- ilog HDL, covers stages from RTL to GDSII and uses Cadence
vanced Computing & Communication Sy tools to evaluate area, power, and delay with 45nm technology
stems (ICACCS). libraries.

4. “Design of a 16 Bit RISC Processor”, This paper describes the design of a 16-bit RISC processor us-
K. Vishnuvardhan Rao, A. Anita Ange- ing a custom approach. The design aims to enhance efficiency
line and V. S. Kanchana Bhaaskaran. In- by incorporating compressed instructions, which reduce area a
dian Journal of Science and Technology, nd power usage. Key components, including the Control Unit a
Vol 8(20). nd ALU, were designed and simulated using Cadence tools wit
4

h 180nm technology. The processor consumes 68.9mW for the

AND instruction (1600ns delay) and 77.6mW for the ADD in-
struction (1900ns delay).

3 Analysis Of Literature Survey

Paper 1: “Design of 16 Bit RISC Processor and Implementation using MIPS

Technique”.

Advantage: The Paper throws light into the design process of the 16-bit RISC
Processor and also explains how the 5-stage pipeline method can be integrated by
dividing the process into specific units during the operation. This pipeline method
shortens the execution time of instructions.

Disadvantage: The ALU can only do eight operations AND, NAND, OR, XOR,
Arithmetic & Shift operations. This limits the usability as it can perform only the
basic set of operations. The Processor can’t do advanced operations like Branch
Operations, ROR & ASR Shift Operations. And no error detection.

Paper 2: “Design of 16-bit RISC Processor”.

Advantage: The processor incorporates 16-bit ALU capable of performing 11

arithmetical and logical operations, 16-bit program counter, 24-bit Instruction
register, sixteen 16-bit general purpose registers, 3-bit flag register to indicate carry,
zero and parity. The16-bit RISC processor is based on Harvard architecture and
utilizes minimum functional units.

Disadvantage: The Processor uses only Jump for immediately change its execution
path to another part of the code but does not use the BL LABEL instruction which is
capable of subroutine linkage. It also lacks important instructions like Compare and
some modified instructions like Move top. And no error detection.

Paper 3: “Design of a 16-Bit Harvard Structure RISC Processor in Cadence

45nm Technology”.

Advantage: The major drawback in portable devices was that it takes high power
which leads to less battery life and causes failure in silicon parts of the devices. So
always there is a trade off in VLSI circuits between systems area, power and delay.
This drawback has been reduced in this project by using 45nm Technology. Pipelin-
ing is also done which reduces the number of cycles of execution.
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Disadvantage: The Model is incapable of doing Shift instructions like Barrel Shift
Operation and Push-Pop Instructions. This reduces its flexibility and its applications
in various aspects. In such cases it should be redesigned to suit such purposes. And
no error detection.

Paper 4: “Design of a 16 Bit RISC Processor”.

Advantage: The ALU can perform 16-bit Arithmetic and 16-bit Logical Operations.
It also contains several functional units like 16-bit Carry Look Ahead (CLA) unit,
16-bit Wallace Tree Multiplier unit, 16-bit Barrel Shifter. The function sub-blocks
are successfully integrated.

Disadvantage: Here the branching operation and error detection are not implemen-
ted. It’s also lacking application in some advanced operation.

4 Methodology

Design Specifications

 Specify the working and requirements of the processor.

 Designing the 16-bit processor with data and instruction memory.
 The instruction sets like arithmetic operations, error checker and logical l
operations are designed.
 Design two separate instruction and data memory modules.
 Design the Finite State Machine (FSM) as control logic to control the execution
steps.

Design of various modules

Processor
 Define the inputs ‘DIN’, ‘Resetn’, ‘Clock’, ‘Run’ and ‘err_process_mem’.
 Define the outputs ‘DOUT’, ‘ADDR’, ‘IM’, ‘DM’, ‘DONE’ and ‘W_D’.
 Define the internal registers and wires ‘Gin’, ‘Ain’, ‘Addsub’, ‘IR_in’,
‘ADDR_in’, ALU_and, ‘rX_in’, ‘pc_incr’, ‘DOUT_in’, ‘sp_decr’, ‘sp_incr’ and
‘pc_in’. These are the control signals for various operations [1].
 ‘Tstep_D’ and ‘Tstep_Q’ registers are used for FSM control and ‘Select’ register
used for the multiplexer select signal.
 ‘IR’, ‘BusWires’, ‘A’ and ‘data_out’ are used as data registers, and the ‘G’ as ALU
output.
 We define the flags such as ‘z’ for zero, ‘n’ for negative and ‘c’ for carry.
 For enable the registers we define ‘R_in’ signal.
 Define the ‘III’, ‘rX’ and ‘rY’ are as instruction fields.
 ‘shift_type’ is used for specify the type of shift operation.
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FSM logic
Using different instructions and control signals define the 6 states of FSM (T0 to T5)
and their transitions.
 Implement the registers for storing the intermediate values and results and also the
arithmetic and logical operations.
 Bus wires are designed for transfer the data between the other parts of the proces -
sor.
 The next step (‘Tstep_D’) id determined on the basis of current step(‘Tstep_Q’).
 We load appropriate data into internal buses on the basis of select line.

Control FSM Flip-Flop

We define two always blocks:
The first always block is triggered at positive edge of clock or the falling edge of
‘Resetn’ or falling edge of ‘clock’. If ‘Resetn’ is low or if there is an ‘err’ or
‘err_process_mem’ resets ‘Tstep_Q’ to ‘3’b000’. Otherwise, it sets ‘Tstep_Q’ to the
value of ‘Tstep_D’.
The second always block triggers at any change in the inputs. And it calculates check -
sum of the lower 16 bit of ‘IR’. And if the check sum is does not match the upper 8
bits of ‘IR’. Set ‘err’ as 1’b1, otherwise set ‘err’ to 1’b0. This is the error detection we
can implement the hamming code for error the correction.

Decoder
 Implement 3-bit input (w) and 8-bit one encoded output (y) for decode the register
addresses when enable E is active [6, 8].

Register
 Implement a 16 bit register with input as ‘Buswires’, ‘Resetn’, ‘r_in’, ‘Clock’,
‘pc_incr’, ‘sp_decr’, ‘sp_incr’. And output as 16-bit ‘r’.
 If ‘Resetn’ is low the ‘r’ is set as 0x0000. If ‘r_in’ is high then load the value from
Bus wires into registers.
 Else it checks the program counter (‘pc_incr’) if it is high increment the value of r
by 1. Else it checks the stack pointer decrement (‘sp_decr’) if it is high, decrement
the value of r by 1.
 In last it checks the stack pointer increment (‘sp_incr’) if it is high, increment the
value of r by 1 [8].

Instruction memory
 Define the inputs such as ‘Address’ of 16 bits, ‘data’ of 24 bit, write
enable(‘wren’), ‘IM’ and ‘clock’. And the output as ‘q’. Implement read and write
functionality based on these inputs, this is designed for selecting the multiple pre-
defined instruction sets [7].
Data memory
 Define the inputs such as ‘Address’ of 16 bits, ‘data’ of 24 bit, ‘DM’, write en-
able(‘wren’) and ‘clock’. And the output as ‘q’ of 24 bit. Based on these we imple -
ment the read and write operations [1, 4].
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Integration

 Define the top processor module as “processor_top_module_new_harv_err_ctr1”,

in which we will integrate the individual modules to form a core system [3].
 Model the processor, instruction memory and data memory modules, and connect
the internal signals by ‘DIN1’, ‘DIN2’, ‘DOUT’, ‘ADDR’, ‘IM’, ‘DM’, ‘W_D’
and ‘err_process_mem’.
 The output of instruction and data memory are merged to form single input ‘DIN’
to the processor [2].

Testing

 This is the functionality verification of integrated system. Here we will verify the
integrated system by using testbench.
 The testbench signals ‘Clock_tb’, ‘Resetn_tb’ and ‘Run_tb’ are initialized.
 Start the processor by applying the reset. And implement a clock signal generator.
 Run the simulation to observe the behavior and functionality of the designed pro-
cessor [9, 10].

Verifying and Debugging

 Verification of functionality: Assuring that all the instructions are executed

correctly. And check the interaction between processor and memory modules.
 Debugging: Identify the issues related to the control signals, timing or data han-
dling and fix them.

5 Block Diagram
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Fig. 1. The Block Diagram of the Processor.

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Fig. 2. Program Counter & Stack Pointer.

Fig. 1 & 2, show the block diagram, program counter and stack pointer.

6 Results

INSTRUCTIONS MACHINE CODE

(HEX)
MOV R1, #ACH 12AC

MOVT R0, #FFH 30FF

AND R0, R1 8001

ADD R0, #08H 5008
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ST R0, [R1] C001

LD R2, [R1] A401

MOV R5, #50H 1A50

PUSH R1 D205

POP R3 B605

LSL R0, #02H E182

HERE: LSR R0, #02H E1A2

CMP R0, #28H F028

B{NEQ} HERE 25FD

Table. 1. Instruction in HEX Code.

Fig. 3. Output Waveform 1.

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Fig. 4. Output Waveform 2.

Fig. 5. Output Waveform 3.

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Table. 1 and Fig. 3, 4 & 5, show the instruction executed and its output.
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7 References

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prototype: An extensible and configurable platform for the system-level”, Journal of Systems
Architecture, Volume 109, 2020, 101756, ISSN13837621,
https://doi.org/10.1016/j.sysarc.2020.101756.[4]. Waterman Andrew, Asanović Krste (Eds.),
The RISC-V Instruction Set Manual; Volume II: Privileged Architecture, RISC-V Foundation
(2019).

2. Palmiero, G. Di Guglielmo, L. Lavagno and L. P. Carloni, "Design and Implementation of

a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT
Applications," 2018 IEEE High-Performance Extreme Computing Conference (HPEC),
Waltham, MA, USA, 2018, pp. 1-7.

3. Sudhanya P Department of Electronics and Communication Engineering Faculty of

Engineering and Technology SRM Institute of Science and Technology 2023 5th
International Conference on Inventive Research in Computing Applications (ICIRCA),
Design and Simulation of RISC Processor using Verilog | 979-8-3503-2142-5/23/$31.00
©2023 IEEE | DOI: 10.1109/ICIRCA57980.2023.10220777 Kattankulathur, India-603203
[email protected].

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Processor using Cadence,” in IEEE International Conference on Advanced Communication
Control and Computing Technologies (ICACCCT), 2014, pp. 979–983.

5. Samiappa Sakthikumaran, Salivahanan S and Kanchana Baaskaran V S, “16-Bit RISC

Processor Design for Convolution Applications,” in IEEE- International Conference on
Recent Trends in Information Technology, Jun. 2011, pp. 394–397.

6. B. Fechner. Analysis of Checksum-Based Execution Schemes for Pipelined Processors.

Proc. 11th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric
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Upset in SRAM Based FPGAs. MAPLD 2002, Proceedings of the 2002 Military and
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9. Vishwas V. Balpande*, Abhishek B. Pande, Meeta J. Walke, Bhavna D. Choudhari, Kiran

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