T2080QDS features
Specification Description
Core Processors 4x64-bit up to 1.8 GHz Power Architecture Book
E-compliant cores
HS Serial Port (SerDes)1 • 16 lanes, up to 10.3125 GHz SerDes, divisible into
combinations
• Supports Aurora debug, PEX3.0, SATA2.0, SGMII,
sRIO2.0, XFI, XAUI, and HiGig
DDR • Supports one DDR3/DDRL 32-/64-bit memory
controller
• T2080QDS supports 64-bit DDR3/DDR3L controller
connected to single uDIMM socket
• Default DIMM module - DDR3, 72-bit, ECC, 2 GB up
to 2100MT/s, 1.5V
• Optional DDR3L DIMM module could be <= 8 GB,
72-bit, ECC up to 1866MT/s, 1.35V
EtherNet • Dual 10/100/1000 Mbit/s port uses onboard
RTL8211EG-VB-CG PHY’s in RGMII mode.
1588 PTP • Support through on-board header J28
Processor Support Dual USB 2.0, Internal PHY Two high speed onboard USB 2.0 connectors
IFC • One in-socket 128 MB NOR flash 16-bit data bus
• One 512 MB NAND flash with ECC support
• IFC Test Port
• PromJet debug Port
eSDHC PEX x1 Right Angle connector (J4) is used for the following
add-in card types:
• 1-/4-/8-bit MMC Legacy CARD
• 1-/4-/8-bit MMC Card
• 4-bit eMMC Card Rev 4.4
• 8-bit eMMC Card Rev 4.5
• SD Card Rev 2.0 and Rev 3.0
SPI • 16 MB high-speed flash Memory for boot code and
storage (up to 108MHz)
• 8 MB high-speed flash Memory (up to 104 MHz)
• 512 MB low-speed flash Memory (up to 40 MHz)
• All memory operate at 1.8V
Multimaster Serial Computer Four controllers
Bus, I2C,
DUART (2/channel) Two 4-pin or four 2-pin serial ports at up to 115.2 Kbit/s
SATA (2 channels) Two SATA onboard connectors
Debug Features • Legacy, COP/JTAG, and Aurora support
• Event and EVT support
Package • 896-pin, Flip-Chip PBGA of 25x25mm pitch 0.8mm
• Supports attached socket and solder
T2080QDS features
Specification Description
ProASIC3E FPGA • Manages the following:
– system reset sequencing
– system and SerDes clock speed selections
– boot and RCW source selection
• Implements registers for system control and
monitoring
System Logic • Internal Cortex-M1 Soft Processor allows independent
Vcore/temperature monitoring and reconfiguration
• Supports legacy TMT test features
• (PORt, IRS, SYSCLK synchronous assertion)
• General fault monitoring and logging
• Runs from ATX-PS Hot power rails, allowing operation
while system is off
SYSCLK • Switch selectable to one of 16 common settings in the
range of (64-166) MHz
• Software programmable in 1MHz increments from
(1-200) MHz
SerDes • Supports four domains
Clocks • 100 (Spread Spectrum optionally), 125, and 156.25
MHz configurations support PEX, SATA, SGMII, sRIO,
XFI, XAUI, HiGig and Aurora debug
EtherNet • Supports 125 MHz ethernet clocks for T2080,
on-board RGMII PHY and 1588 test connector
USB • Supports 24MHz T2080 USB clock input
One dedicated programmable • PMBus control
regulator supply T2080 core • Power:
domain and DDR power pools. – 1.0V for USB Core
– 1.89V for T2080 PROG_SFP and PROG_MTR
Set of independent DC/DC (POVDD)
and LDO power supplies – 1.5V for FPGA Core
– 1.35/1.5V XVDD
Power Supplies – 1.0V SVDD
– 1.8V for T2080 Gen.I/O, SerDes MUX (OVDD) and USB
OVDD
– 2.5V for Ethernet PHY IO (LVDD)
– 1.8/2.5/3.3V UART/I2C (DVDD)
– 3.3V switchable regulator for FPGA
– 3.3V for USB HVDD
– VTT/VREF for DDR3
– 1.8/2.5V for eSPI, eSDHC (CVDD)
– 1.0V for Secure monitor (VDD_LP)
T2080QDS block diagram
T2080 XFI Modules x4
DDR uDIMM x72 DDR Interface 1 x4
DDR uDIMM x72
[A:D]
SERDES 1
PEX#3 GEN2[x1-x8]/XAUI/HiGigx2/ or SGMII [x2-x4] SLOT3
x4 x16
SPI Flash
x4
[E:H] PEX1,PEX2, GEN2x1, SGMIIx2x3 SLOT2
4/8-bit eSDHC/eMMC/MMC/SD x4 x8
x2 PEX#4 GEN3[x1-x4] or SGMIIx1x4 SLOT1
USB x2
x8
x4
10/100/1G RGMII x2 [A:D] SLOT4
SERDES 2
PEX#1 GEN3x4/GEN2[x1-x8] or SRIO2 x4
x2 x16
x4 SLOT5
1588 PTP Test PEX#2 GEN2[x2x4] or SRIO1 x4
[E:H] x8
Aurora
SYS/DDR/
SERDES/RGMII SATA1/2
Clocks
I2C
#2,#3
IFC Card/Test
Port Conn.
Connector
16bit
PromJet
IFC
IFC I2C
#1,#4 FLASH/RCW,RTC/PWR CNTR/THERM.
16bit 8bit MONITOR, etc.
NOR Flash ASYNC NAND x2
16bit
x16bit Flash x8bit DUART
5V0 (IFC Card Conn)
ATX PS
12V1 (TO PEX SLOTS)
3V3HOT
1V5HOT
SYSTEM FPGA
VDD=1V0
G1VDD,D1_MVREF,VTT On-board
COP/JTAG Cascade
XVDD,SVDD,AVDD’s
Secondary
USB_HVDD,OVDD,SVDD
PS’s
1
COP/JTAG
OVDD=1V8/3V3-INTERPOSER
AURORA
CWTAP
LED’s LVDD=2V5
POWER
EVENT
HRESET
CVDD=1V8/2V5/3V3-INTERPOSER
DVDD=1V8/2V5/3V3
SW[1:12] POVDD=1.89V
VDD_LP=1V0
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