Overview Programmable logic (PLAs & PALs )

 Last lecture  Concept: Large array of uncommitted AND/OR gates

 "Switching-network" logic blocks  Actually NAND/NOR gates
 Multiplexers/selectors  You program the array by making or breaking connections
 Demultiplexers/decoders  Programmable block for sum-of-products logic
 Programmable logic devices (PLDs)
 Regular structures for 2-level logic • • •
inputs
 Today
 PLDs
 PLAs AND OR
 PALs array product array
 ROMs terms
 Tristates
 Design examples outputs
• • •

CSE370, Lecture 11 1 CSE370, Lecture 11 2

Programming the wire connections Short-hand notation

 Fuse: Comes connected; break unwanted connections  Draw multiple wires as a single wire or bus
 Anti-fuse: Comes disconnected; make wanted connections  × signifies a connection
A B C

Before Programming After Programming

F0 = A + B'C' AB A B C D
F1 = AC' + AB
B'C AB
F2 = B'C' + AB
F3 = B'C + A A'B'
AC'
CD'
B'C'
C'D
A
1
F0 = AB + A'B' F0 F1
F1 = CD' + C'D
F0 F1 F2 F3
CSE370, Lecture 11 3 CSE370, Lecture 11 4
PLA example PLAs versus PALs
F1 = ABC Think of as a memory-address decoder  We've been looking at PLAs
F2 = A+B+C A B C
Memory bits  Fully programmable AND / OR arrays
F3 = A' B' C'  Can share AND terms
F4 = A' + B' + C' A'B'C'
F5 = A xor B xor C A'B'C
 Programmable array logic (PAL)
F6 = A xnor B xnor C  Programmable AND array
A'BC'
 OR array is prewired
A'BC  No sharing ANDs
A B C F1 F2 F3 F4 F5 F6
0 0 0 0 0 1 1 0 0 AB'C'  Cheaper and faster than PLAs
0 0 1 0 1 0 1 1 1
0 1 0 0 1 0 1 1 1 AB'C
0 1 1 0 1 0 1 0 0 ABC'
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0 ABC
1 1 0 0 1 0 1 0 0
1 1 1 1 1 0 0 1 1
F1 F2 F3 F4 F5
F6
CSE370, Lecture 11 5 CSE370, Lecture 11 6

Example: BCD to Gray code converter Example (con’t): Wire a PLA

A B C D W X Y Z A A Minimized functions: A B C D
AB AB
0 0 0 0 0 0 0 0 CD 00 01 11 10 CD 00 01 11 10
0 0 0 1 0 0 0 1 00 0 0 X 1 00 0 1 X 0
W = A + BC + BD
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 01 0 1 X 1 01 0 1 X 0 X = BC'
D D
0 1 0 0 0 1 1 0 11 0 1 X X 11 0 0 X X Y =B+C
0 1 0 1 1 1 1 0 C C
0 1 1 0 1 0 1 0 10 0 1 X X 10 0 0 X X Z = A'B'C'D + BCD
0 1 1 1 1 0 1 1 B B + AD' + B'CD'
1 0 0 0 1 0 0 1 K-map for W K-map for X
1 0 0 1 1 0 0 0
1 0 1 0 X X X X A
1 0 1 1 X X X X AB AB A
1 1 0 0 X X X X CD 00 01 11 10 CD 00 01 11 10
1 1 0 1 X X X X 00 0 1 X 0 00 0 0 X 1
1 1 1 0 X X X X 01 0 1 X 0 01 1 0 X 0
1 1 1 1 X X X X D D
11 1 1 X X 11 0 1 X X
C C
10 1 1 X X 10 1 0 X X
B B
K-map for Y K-map for Z

W X Y Z
CSE370, Lecture 11 7 CSE370, Lecture 11 8
Example: Wire a PAL Compare implementations
Minimized functions:  PLA:
W = A + BC + BD  No shared logic terms in this example
X = BC'  10 decoded functions (10 AND gates)
Y =B+C
Z = A'B'C'D + BCD
 PAL:
+ AD' + B'CD’  Z requires 4 product terms
 16 decoded functions (16 AND gates)
 6 unused AND gates
What do we do with the
unused AND gates?  This decoder is a poor candidate for PLAs/PALs
 10 of 16 possible inputs are decoded
 No sharing among AND terms

 Better option?
 Yes — a ROM

CSE370, Lecture 11 9 CSE370, Lecture 11 10

Read-only memories (ROMs) ROM details

 Two dimensional array of stored 1s and 0s  Similar to a PLA but with a fully decoded AND array
 Input is an address ⇒ ROM decodes all possible input addresses  Completely flexible OR array (unlike a PAL)
 Stored row entry is called a "word"  Extremely dense: One transistor per stored bit
 ROM output is the decoded word
+5V
Only one word line
n address lines n-1 is active at any time
2
• • •
inputs 2
decoder
1
memory
array 0
2n word
decoder (2n words
lines by m bits)
0 n-1 0 m-1
Bit lines: Normally pulled high through
Address Outputs
outputs resistor. If transistor stores a zero, then
• • • line pulls low when row is selected

CSE370, Lecture 11 11 CSE370, Lecture 11 12

Two-level combinational logic using a ROM ROMs versus PLAs/PALs
 Use a ROM to directly store a truth table  ROMs
 No need to minimize logic  Benefits
 Example: F0 = A'B'C + AB'C' + AB'C  Quick to design, simple, dense
F1 = A'B'C + A'BC' + ABC  Limitations
F2 = A'B'C' + A'B'C + AB'C'  Size doubles for each additional input
F3 = A'BC + AB'C' + ABC'  Can't exploit don't cares

 PLAs/PALs
A B C F0 F1 F2 F3  Benefits
0 0 0 0 0 1 0 ROM
You specify whether
 Logic minimization reduces size
0 0 1 1 1 1 0 8 words x 4 bits/word to store 1 or 0 in each
0 1 0 0 1 0 0 location in the ROM  Limitations
0 1 1 0 0 0 1  PAL OR-plane has hard-wired fan-in
1 0 0 1 0 1 1
1 0 1 1 0 0 0
1 1 0 0 0 0 1 A B C F0 F1 F2 F3  Another answer: Field programmable gate arrays
1 1 1 0 1 0 0 address outputs  Learn about in 467

CSE370, Lecture 11 13 CSE370, Lecture 11 14

Loose end: Tristates Example: BCD to 7-segment display controller

 Tristate buffers have a control input  The problem
 Enabled: Buffer works normally  Input is a 4-bit BCD digit (A, B, C, D)
 Disabled: Buffer output is disconnected  Need signals to drive a display (7 outputs C0 – C6)

c0
2:1 Tristate Mux module muxtri (In1,In2,Sel,OUT); c5 c1
input In1,In2,Sel;
c6
output OUT; c4 c2
In1 OUT tri OUT; c3
bufif1 (OUT,In1,Sel); c0 c1 c2 c3 c4 c5 c6
bufif0 (OUT,In2,Sel);
endmodule
In2 BCD to 7–segment
control-signal
decoder
Sel
A B C D
CSE370, Lecture 11 15 CSE370, Lecture 11 16
Formalize the problem Sum-of-products implementation
 15 unique product terms if we minimize individually
 Truth table A B C D C0 C1 C2 C3 C4 C5 C6
 Many don’t cares 0 0 0 0 1 1 1 1 1 1 0
A A A A A
0 0 0 1 0 1 1 0 0 0 0
 Choose implementation 0 0 1 0 1 1 0 1 1 0 1 1 0 X 1 1 1 X 1 1 1 X 1 1 0 X 1 1 0 X 1
0 1 X 1 1 0 X 1 1 1 X 1 0 1 X 0 0 0 X 0
target 0 0 1 1 1 1 1 1 0 0 1 D D D D D
0 1 0 0 0 1 1 0 0 1 1 C 1 1 X X C 1 1 X X C 1 1 X X C 1 0 X X C 0 0 X X
 If ROM, we are done 1 1 X X 1 0 X X 0 1 X X 1 1 X X 1 1 X X
0 1 0 1 1 0 1 1 0 1 1
 Don't cares imply PAL/PLA 0 1 1 0 1 0 1 1 1 1 1 B B B B B
may be good choice 0 1 1 1 1 1 1 0 0 0 0 A A
C0 = A + B D + C + B' D'
1 0 0 0 1 1 1 1 1 1 1 1 1 X 1 0 1 X 1
 Implement design 1 0 0 1 1 1 1 0 0 1 1 0 1 X 1 0 1 X 1
C1 = C' D' + C D + B'
D D C2 = B + C' + D
 Minimize the logic 1 0 1 – – – – – – – – C 0 0 X X C 1 0 X X C3 = B' D' + C D' + B C' D + B' C
 Map into PAL/PLA 1 1 – – – – – – – – – 0 1 X X 1 1 X X C4 = B' D' + C D'
B B C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C

CSE370, Lecture 11 17 CSE370, Lecture 11 18

Better SOP implementation PLA implementation

 Can do better than 15 product terms C0 = BC'D + CD + B'D' + BCD' + A A B C D
 Share terms among outputs ⇒ only 9 unique product terms C1 = B'D + C'D' + CD + B'D'
C2 = B'D + BC'D + C'D' + CD + BCD'
 Each term not necessarily minimized
C3 = BC'D + B'D + B'D' + BCD' BC'
A A C4 = B'D' + BCD'
B'C
C2 C2 C5 = BC'D + C'D' + A + BCD'
1 1 X 1 1 1 X 1
C6 = B'C + BC' + BCD' + A B'D
1 1 X 1 1 1 X 1
D D
BC'D
C 1 1 X X C 1 1 X X
0 1 X X 0 1 X X C'D'
B B CD
C0 = A + BD + C + B'D' C0 = BC'D + CD + B'D' + BCD' + A B'D'
C1 = C'D' + CD + B' C1 = B'D + C'D' + CD + B'D'
C2 = B + C' + D C2 = B'D + BC'D + C'D' + CD + BCD' A
C3 = B'D' + CD' + BC'D + B'C C3 = BC'D + B'D + B'D' + BCD' BCD'
C4 = B'D' + CD' C4 = B'D' + BCD'
C5 = A + C'D' + BD' + BC' C5 = BC'D + C'D' + A + BCD'
C6 = A + CD' + BC' + B'C C6 = B'C + BC' + BCD' + A
C0 C1 C2 C3 C4 C5 C6 C7
CSE370, Lecture 11 19 CSE370, Lecture 11 20
Example: Logical function unit Formalize the problem and solve
 Multipurpose functional block C0
0
C1
0
C2
0
A
0
B
0
F
1

3 control inputs (C) specify function

0 0 0 0 1 1
 0
0
0
0
0
0
1
1
0
1
1
1 Implementation choice:
 2 data inputs (operands) A and B 0
0
0
0
1
1
0
0
0
1
0
1 multiplexer with discrete gates
 1 output (same bit-width as input operands) 0
0
0
0
1
1
1
1
0
1
1
1
0 1 0 0 0 1
0 1 0 0 1 1
0 1 0 1 0 1
0 1 0 1 1 0
0 1 1 0 0 0 1 0
C0 C1 C2 Function Comments 0
0
1
1
1
1
0
1
1
0
1
1 1
0 0 0 1 always 1 0 1 1 1 1 0 A
1 0 0 0 0 1
B 2
0 0 1 A+B logical OR F
3 control inputs: C0, C1, C2 1
1
0
0
0
0
0
1
1
0
0
0 A 3 8:1 MUX
0 1 0 (A • B)' logical NAND 2 data inputs: A, B
1
1
0
0
0
1
1
0
1
0
1
0 B 4
0 1 1 A xor B logical xor 1 0 1 0 1 0 5
1 output: F 1 0 1 1 0 0
A
1 0 0 A xnor B logical xnor 1 0 1 1 1 1 6
1 1 0 0 0 1 B
1 0 1 A•B logical AND 1 1 0 0 1 0 0 7
1 1 0 1 0 0
S2 S1 S0
1 1 0 (A + B)' logical NOR 1
1
1
1
0
1
1
0
1
0
0
0
1 1 1 0 always 0 1
1
1
1
1
1
0
1
1
0
0
0
1 1 1 1 1 0 C0 C1 C2

CSE370, Lecture 11 21 CSE370, Lecture 11 22

Pal Feature: Tri-stated outputs Pal Feature: Individually Tri-stated outputs

Enable Enable

(Active Low) (Active Low)

CSE370, Lecture 11 23 CSE370, Lecture 11 24

Pal Feature: Feedback terms Pal Feature: Registered outputs

CSE370, Lecture 11 25 CSE370, Lecture 11 26

Pal Feature: Registers with bypass multiplexers

CSE370, Lecture 11 27