18-12-2008

BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
Midterm Exam II - SOLUTIONS

Surname: ________________________________

Name: ________________________________

ID-Number: ________________________________

Signature: ________________________________

Duration is 120 minutes. Solve all 5 questions. Show all your work.

Q1 (12 points)
Q2 (22 points)
Q3 (22 points)
Q4 (22 points)
Q5 (22 points)
Total
Question 1-(12 pts):
(a) (4 pts) Draw the block diagram of a synchronous finite-state machine, and explain
the difference between Mealy and Moore machines. Make sure to label all of the blocks
properly.

Clocked synchronous state-machine structure (Mealy machine)

Clocked synchronous state-machine structure (Moore machine)

The outputs for Mealy machines depend on the current state as well as on the input
directly. For Moore mchines, the outputs depend on the current state only.

(b) (4 pts) What is the fundamental difference between a flipflop and a latch?

Flipflops are edge-triggered while latches are level-sensitive.

(c) (4 pts) Draw the gate-level circuit diagram of an S-R latch and explain how it works.

S-R latch circuit design S-R latch function table

Question 2-(22 pts):
You are to design an FSM that recognizes the occurence of a particular sequence of bits.
This “sequence-recognizer” has one input X and one output Z. The circuit is to
recognize the occurence of the sequence of bits 1101 on X by making Z equal to 1 when
the previous three inputs to the circuit were 110 and the current input is a 1. Otherwise,
Z equals 0. Design and draw this FSM using D flip flops with active low Preset and
Clear controls. Show all steps of FSM design procedure. Note for clarification that the
LSB in the sequence 1101 is the present value of X.

Solution:
States: Power ON 0,0
S0: Power ON state (Also not enough
S0
information, or start of seeking a new
sequence)
S1: First 1 of the sequence is received. 1,0 0,0
0,0
S2: Two 1s in a row are received.
S3: 110 is received.

We need 2 flip flops. 1,1 S3

S1

State encoding:
Q1 Q0 1,0
S0 0 0 0,0
S1 0 1 S2

S2 1 0
S3 1 1
1,0
Next state table:
Q1 Q0 X Q1* Q0*
0 0 0 0 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 0
1 1 1 0 1

D1: D0:
Q1Q0 Q1 Q1Q0 Q1
X X

0 0 0 1 0 0 0 1

0 1 0 1 1 0 1 0

Q0 Q0

D1 = Q1Q0’+ Q1’Q0X D0 = Q1Q0’X’+Q1’Q0’ X+Q1Q0X

Output table:
Q1 Q0 X Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Z=Q1Q0X

X
+5v

D1 PR Q1
Q1Q0’+ Q1’Q0X D Q

CLK Q Z
CLR

P
+5v
+5v

Q1Q0’X’+ RESET
D0 PR Q0 IC
Q1’Q0’ D Q P
X+Q1Q0X’

clock CLK
CLR

Another solution:

State encoding:
Q1 Q0
S0 0 0
S1 0 1
S2 1 1
S3 1 0

Next state table:

Q1 Q0 X Q1* Q0*
0 0 0 0 0
 0 0 1 0 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 1 1

D1: D0:
Q1Q0 Q1 Q1Q0 Q1
X X

0 0 1 0 0 0 0 0

0 1 1 0 1 1 1 1

Q0 Q0

D1 = Q1Q0+ Q0X D0 = X

Output table:
Q1 Q0 X Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

Z=Q1Q0’X

In this solution the next state circuit is simpler.

Question 3– Part (a) -(7 pts):
Write a VHDL code to design a single-bit Full-Adder. You need to first draw the Truth
table and/or write the logical expressions for the output signals before writing your
VHDL code.

X Single- S
bit
Y Full
Adder
Cin Cout

Solution:
a) Full Adder:

Truth Table is

Cin X Y S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = Cin’(X ⊕ Y)+ Cin(X ⊕ Y)’= X ⊕ Y ⊕ Cin

To find a minimal function for Cout let us form a K-map

Y\ CinX 00 01 11 10

0
0 0 1 0
1
0 1 1 1

Cout =XY + XCin + YCin

 X
Y S
Cin

Cout

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
Port (X, Y, Cin: in BIT;
Cout, S: out BIT);
end fulladder;

architecture Behavioral of fulladder is

begin
S<=X xor Y xor Cin;
Cout<= X and Y or X and Cin or Y and Cin;
end Behavioral;
Question 3– Part (b) -(15 pts):
Write a VHDL code to design a 4-bit 2’s complement Ripple Adder/Subtractor using the
Full-Adder module designed in part (a). The circuit receives two 4-bit 2’s complement
numbers and a control input depending on which it does addition or subtraction.
CONTROL must be 0 to make addition and it must be 1 to make subtraction. The
outputs are the sum/difference (SumDiff) and the overflow being set to 1 if overflow
exists and 0 otherwise. You need to first draw the block diagram of the circuit then
implement your design in VHDL.

X X 4-bit S SumDiff
Y Y
Ripple
Adder/
Subtractor
CONTROL C O Overflow

Solution:
b) Ripple Adder/Subtractor:

To perform addition of 2 4-bit numbers, we use 4 full adders and set the carry-in of the
rightmost full adder to 0 (CONTROL = 0). There is overflow if c4 ≠ c3 . That is,
OVERFLOW = 1 if c4 ≠ c3 and OVERFLOW = 0 if c4 = c3 .

For subtraction, we know that X-Y = X + (-Y) = X+Y’+1. Thus we complement Y and add 1
through setting c0 to 1 (CONTROL = 1).

Y3 Y2 Y1 Y0

X3 X2 X1 X0

X Y X Y X Y X Y

Full Full Full Full

Adder Adder Adder Adder
c4 c3 c2 c1 c0
Cout Cin Cout Cin Cout Cin Cout Cin
S S S S

S3 S2 S1 S0

OVERFLOW

VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RippleAdder_Subtractor is
Port(X: in BIT_VECTOR (3 downto 0);
Y: in BIT_VECTOR (3 downto 0);
CONTROL: in BIT;
SumDiff: out BIT_VECTOR (3 downto 0);
Overflow: out BIT);
end RippleAdder_Subtractor;

architecture Behavioral of RippleAdder_Subtractor is

component fulladder
Port (X, Y, Cin: in BIT;
Cout, S: out BIT);
end component;

signal C: BIT_VECTOR (4 downto 0);

signal Y_A: BIT_VECTOR (3 downto 0);

begin
C(0)<= CONTROL;
Y_A(0)<=CONTROL xor Y(0);
Y_A(1)<=CONTROL xor Y(1);
Y_A(2)<=CONTROL xor Y(2);
Y_A(3)<=CONTROL xor Y(3);

LABEL1: fulladder
port map(X(0), Y_A(0), C(0), C(1), SumDiff(0));
LABEL2: fulladder
port map(X(1), Y_A(1), C(1), C(2), SumDiff(1));
LABEL3: fulladder
port map(X(2), Y_A(2), C(2), C(3), SumDiff(2));;
LABEL4: fulladder
port map(X(3), Y_A(3), C(3), C(4), SumDiff(3));;

Overflow<=C(3) xor C(4);

end Behavioral;
Question 4-(22 pts):

Implement F = (A+B)C’
a) (4 pts) using a generic 8-to-1 multiplexer and minimum number of additional simple
gates,

A B C (A+B)C’ 1
0 0 0 0
0 0 1 0 E
0 1 0 1 0 D0
0 1 1 0 0 D1
1 0 0 1
1 0 1 0 1 D2
1 1 0 1 0 D3
1 1 1 0 Y
1 D4
0 D5
1 D6
0 D7
S2 S1 S0

A B C
b) (4 pts) using a generic 4-to-1 multiplexer and minimum number of additional simple
gates,
1

E
B D0
0 D1
1 D2 Y
0 D3
S1 S0

A C

c) (4 pts) using a generic 2-to-1 multiplexer and minimum number of additional simple
gates,
1

A E
B D0

Y
0 D1
S0

C
Question 4-(22 pts) - Continued:
d) (4 pts) using one 74XX138 decoder and minimum number of additional simple gates.
(note that 74XX138 is a 3-to-8 binary decoder with active low outputs and with three
enables, one active high and two active low),
74X138

1 G1 Y0
0 G2A Y1
0 G2B Y2
Y3
A S2 Y4 F
B S1 Y5
C S0 Y6
Y7

e) (6 pts) using two 2-to-4 generic decoders and minimum number of additional simple
gates.

E Y0
Y1
B S1 Y2
C S0 Y3

F
A
E Y0
Y1
B S1 Y2
C S0 Y3
Question 5-(22 pts):
The following VHDL code is given:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
Port ( b : in BIT;
a : in BIT_VECTOR (9 downto 0);
x : out STD_LOGIC_VECTOR (3 downto 0);
g : out BIT);
end top;

architecture Behavioral of top is

component devre
Port ( a : in BIT_VECTOR (9 downto 0);
d : out STD_LOGIC_VECTOR (3 downto 0);
g : out BIT);
end component;
signal y: STD_LOGIC_VECTOR (3 downto 0);

begin
devre1: devre port map (a,y,g);
x<="ZZZZ" when b='1' else y;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity devre is
Port ( a : in BIT_VECTOR (9 downto 0);
d : out STD_LOGIC_VECTOR (3 downto 0);
g : out BIT);
end devre;

architecture Behavioral of devre is

begin
d<="0000" when (a="1111111111") else
"1001" when a(9)='0' else
"1000" when a(8)='0' else
"0111" when a(7)='0' else
"0110" when a(6)='0' else
"0101" when a(5)='0' else
"0100" when a(4)='0' else
 "0011" when a(3)='0' else
"0010" when a(2)='0' else
"0001" when a(1)='0' else
"0000" when a(0)='0';
g<='0' when (a="1111111111") else '1';
end Behavioral;

a) Complete the following timing diagram assuming that

a(9)=a(6)=a(5)=a(4)=a(3)=a(2)=a(1)=a(0)=1.
b)

a(8)

a(7)

x(3)

x(2)
x(1)
x(0)

c) What is the function of the entity “devre”? How can you name it?
What is the function of the entity “top”? How can you name it?
What is the function of the signal “b”? How can you name it?
What is the function of the signal “g”? How can you name it?
Solution:
“devre” is a priority encoder with active low inputs giving highest priority to
a(9).
“top” is the same thing but with tri-state encoding outputs and active low enable.
“b” is the active low enable of “top” . If b=1 then the output of “top” becomes
high Z.
“g” is the active high got-something signal meaning that at least one of the inputs
are low.
Appendix: Some VHDL Templates 18-12-2008

ENTITY DECLARATION
entity entity_name is
generic ( constant_names : constant type;
constant_names : constant type;
…
constant_names : constant type);
port ( signal_names : mode signal_type;
signal_names : mode signal_type;
…
signal_names : mode signal_type);
end entity_name;
ARCHITECTURE DEFINITIONS
architecture architecture-name of entity-name is
type declarations
signal declarations
constant declarations
function definitions
procedure definitions
component declarations
begin
concurrent statement
...
concurrent statement
end architecture-name;
COMPONENT DECLARATION
component component_name
port ( signal_names : mode signal type;
signal_names : mode signal type;
…
signal_names : mode signal type);
end component;
COMPONENT INSTANTIATION
label: component_name port map (signal1, signal2, …,signaln);
or,
label: component_name port map (port1 =>signal1, port2 =>signal2, …, portn =>signaln);

DATAFLOW TYPE STATEMENTS:

Simple concurrent assignment statement

signal_name <= expression;
Conditional concurrent assignment statement
signal_name <=
expression when boolean-expression else
expression when boolean-expression else
…
expression when boolean-expression else
expression;
with-select statement
with expression select
signal_name <= signal_value when choices,
signal_value when choices,
…
signal_value when choices;

Note that conditional concurrent assignment statement and with-select statement cannot be used in a process
statement. Instead, in a process, one can use the the sequential conditional assignment statements if and case.
BEVAVIORAL TYPE STATEMENTS:

process statement
process(signal_name, signal_name, …, signal_name)
type_declarations
 variable declarations
constant declarations
begin
sequential-statement
…
sequential-statement
end process;
Simple sequential assignment statement
signal_name <= expression;
Simple variable assignment statement
variable_name := expression;
if statement in its general form
if boolean_ expression then sequential_statements
elsif boolean_ expression then sequential_statements
…
elsif boolean_ expression then sequential_statements
else sequential_statements
end if;
Note that you may not use the else and/or the elsif.
case-when statement
case expression is
when choices => sequential_statements
…
when choices => sequential_statements
end case;
loop statement
loop
sequential_statement
…
sequential_statement
end loop;
for-loop statement
for identifier in range loop
sequential_statement
…
sequential_statement
end loop;
while statement
while boolean_expression loop
sequential_statement
…
sequential_statement
end loop;

Note that the if, case, loop, for, and while statements are called sequential statements and they can only be used
in a process statement. Also note that each process is one concurrent statement.

If the “ieee.std_logic_arith.all” and “ieee.std_logic_unsigned.all” packages are included then + and – operators
for addition and subtraction can be used for UNSIGNED binary, SIGNED binary, and STD_LOGIC_VECTOR
types.

Concatenation operator & is used as follows: If A and B are 2 bit numbers then A&B is a four bit number with A
being more significant.
 BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
Midterm Exam Solution
6-04-2007

Duration 120 minutes

Surname: ________________________________

Name: ________________________________

ID-Number: ________________________________

Signature: ________________________________

There are 5 questions of equal weight. Solve all.

Do not detach pages. Show all your work.

Q1
Q2
Q3
Q4
Q5
Total
Q1. a) (4 points) Implement the function F=A’B+AC by using the following 4-to-1
generic multiplexer. You may assume that the inverted inputs are available. No
other logic gates are allowed.
One possible solution is as the following. There are other ways too.

0
A’
A
1

C B
b) (16 points) Determine the counting sequence of the following configuration and
fill in the following table. Assume that the counter is initially 0. Priority order is A3,
A2, A1, and A0 from high to low in the priority encoder.

Next State Table to determine the counting sequence:

Q3 Q2 Q1 Q0 LD Q3* Q2* Q1* Q0*
0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 1
0 0 1 1 0 0 1 0 0
0 1 0 0 1 1 0 1 1
1 0 1 1 1 0 1 1 1
0 1 1 1 1 1 0 1 1
1 0 1 1 1 0 1 1 1

Counting sequence: 7 – 11 – 7 – 11 – 7 – 11…..

Q2. a) (5 points) Find all minimized POS expressions for the following TT.
Z Y X W F W
WX
0 0 0 0 0
YZ
0 0 0 1 1
0* d d 0
0 0 1 0 1
0 0 1 1 d
0 1 0 0 d 1 1 1 0*
0 1 0 1 1 Z
0 1 1 0 1 d 1 d 0
0 1 1 1 1
1 0 0 0 0 Y
1 1 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0 X
1 1 0 0 d
1 1 0 1 1
1 1 1 0 0
1 1 1 1 d
F=(Y+Z)(W’+X)(W’+Z), F=(Y+Z)(W’+X)(W’+Y’)

b) (5 points) Draw the schematics of one of the above minimized functions by using
NOR gates only.
F=(Y+Z)(W’+X)(W’+Z)

c) (5 points) Expand F=(X+Y’).Z + (X’.Y.Z’) using Shannon’s expansion theorem

with respect to Y.
Shannon’s expansion theorem is as follows:
F(X1, X2, …. Xn) = X1.F(1,X2,,…..Xn)+ X1’.F(0,X2,,…..Xn)
F=Y(Z+X’Z’)+ Y’Z

d) (5 points) Prove using algebraic manipulation that

(X+Y’).Z + (X’.Y.Z’) = (X+Y’+Z’).(X’+Z).(Y+Z)
Duality: (XY’+Z)(X’+Y+Z’)=(XY’Z’)+(X’Z)+(YZ)
Multiply Out Left Side: XY’Z’+X’Z+YZ (Note that XX’=YY’=ZZ’=0)
 Q3. A synchronous FSM has one input X and one output Y. Y is 0 initially (at
Power ON). If at a clock +ve tick X = 1 then Y becomes 1 for three clock periods and
then returns to 0. If X is 1 during this time then it is not effective. Write VHDL code
to describe this circuit. The timing diagram below is given for you to understand the
problem better.

CLK

Solution:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity OneShot is
Port ( clock : in std_logic;
X : in std_logic;
Y : inout std_logic);
end OneShot;

architecture Behavioral of OneShot is

signal flag:std_logic :='0';
begin
Y<=flag;
process(clock)
variable count:std_logic_vector (1 downto 0) :="00";
begin
if clock'event and clock='1' then
if flag='0' then
if X='1'then flag<='1';end if;
elsif flag ='1' then
count:=count+1;
if count="11" then flag<='0';count:="00";end if;
end if;
end if;
end process;

end Behavioral;
Q4. The VHDL code of an FSM is given below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TwoInputFSM is
Port ( CLK : in std_logic;
A : in std_logic;
B : in std_logic;
Y : out std_logic);
end TwoInputFSM;

architecture Behavioral of TwoInputFSM is

type newtype is (S0,S1,S2,S3);
signal S:newtype :=S0;
signal N:newtype;

begin
S<=N when CLK'event and CLK='1' else S;
N<=S1 when (not A and B)='1' else S2 when (A and not B)='1' else S3 when (A and
B)='1' else S0 when (not A and not B)='1';
Y<='1' when S=S3 and A='0' else '0';
end Behavioral;

a) Draw the waveform of Y for the given waveforms for A and B.

Solution:

CLK

S S0 S0 S3 S2 S0 S3 S1 S0
b) Draw the state/output diagram of this FSM

Solution:

Power ON

A’B’,0
S0

A’B’,0 A’B’,1

A’B’,0

A’B,0 AB,0
A’B,1
A’B,0 S1 S3 AB,0
AB,0
AB,0

A’B,0
AB’,0 AB’,0

AB’,0

S2

AB’,0
Q5. Design and draw the FSM which has the state/output diagram shown below.
Show all your design steps. What does this FSM do?

Power ON
0
S0
1 (0)

S4
S1
0 (1)
(0)
0
0 1 1

S2 S3 1
(0) 0 (0)
1

Considering that S1 and S3 are equivalent states,

State Encoding:
State Q1 Q0
S0 0 0
S1 0 1
S2 1 0
S4 1 1

Next State Table:

Q1 Q0 X Q1* Q0*
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 0
1 1 1 0 1

Excitation Table: Same as NS table.

Next State Logic:
Q1*=D1=Q0X’+Q1Q0X
Q0*=D0=X

Output Table:
Q1 Q0 Y
0 0 0
0 1 0
1 0 0
1 1 1
Y=Q1.Q0

Circuit:

Function:
Detects “101” sequence from the input.
 BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
Midterm Exam II SOLUTION
14-12-2007

Duration 120 minutes

Surname: ________________________________

Name: ________________________________

ID-Number: ________________________________

Signature: ________________________________

There are 5 questions. Solve all.

Do not detach pages. Show all your work.

Q1
Q2
Q3
Q4
Q5
Total
Q1. (20 points)
Use one 74x163 binary up counter and minimal combinational logic to design a
counter which has the following properties:
i) The count becomes 0 at Power ON.
ii) It counts as 0,1,2,3,4,5 and stops at 5.
iii) While the count is 5 if the signal RESTART is 1 then it goes to 0 and
continues to count up to 5 again.
iv) It is not self-correcting and if an undesired count is encountered then the
signal FAULT becomes 1, else it is 0.
v) However while it is in an undesired count if RESTART is 1, then it goes to 0
and counts up to five again.
(You can assume that at Power ON the 74x163 outputs are 0. Also remember that CLR
has precedence over LD in 74x163)

74x163
clock CLK
CLR
LD
ENP
ENT

D0 Q0
D1 Q1
D2 Q2
D3 Q3
RCO

SOLUTION:
Since it is not self-correcting let us assume that if it goes to an undesired state it
remains there. Thus if it is at state 5 or at an undesired state then we disable the
counter.
Thus

Q3 Q2 Q1 Q0 EN FAULT
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 0 1
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 0 1

Q3

Q3Q2
00 01 11 10
Q1Q0 0 4 12 8
00 1 1 0 0

1 5 13 9
01 1 0 0 0

3 7 15 11 Q0
11 1 0 0 0

Q1 2 6 14 10
10 1 0 0 0

Q2

EN = Q3’Q2’+ Q3’Q1’Q0’ = Q3’(Q2’+ Q1’Q0’)

Q3

Q3Q2
00 01 11 10
Q1Q0 0 4 12 8
00 0 0 1 1

1 5 13 9
01 0 0 1 1

3 7 15 11 Q0
11 0 1 1 1

Q1 2 6 14 10
10 0 1 1 1

Q2

FAULT = Q3 + Q2Q1
However if we are at state 5 or at an undesired state and also if RESTART is 1 then
we go to 0. Thus CLR_L = (EN’. RESTART)’

74x163
clock CLK
RESTART
EN CLR
1 LD
ENP
EN
ENT

Q0
Q1 EN=Q3’(Q2’+Q1’Q0’) D0 Q0
EN D1 Q1
Q2
Q3 D2 Q2 FAULT
D3 Q3 =Q3 +Q2Q1
RCO

Grading:
5 points FAULT
5 points Counts up to 5 and stops
4 points Is not self-correcting
6 points RESTART (is effective when in state5 3 points, is effective when in
undesired state 3 points)

Another solution:

74x163
clock CLK
RESTART
CLR
1 LD
S5 ENP S5
FAULT ENT

D0 Q0
D1 Q1
D2 Q2 FAULT
D3 Q3
RCO

In this solution S5 = Q3’Q2Q1’Q0, however one can also have S5 = Q2Q0.

Q2. (20 points)
For the counter described in Question 1 write VHDL code. Look at the appendix for
VHDL templates.

SOLUTION:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MT2_Q2_V1 is
Port ( CLK : in STD_LOGIC;
RESTART : in STD_LOGIC;
FAULT : out STD_LOGIC);
end MT2_Q2_V1;

architecture Behavioral of MT2_Q2_V1 is

signal Q:std_logic_vector(2 downto 0) :="000";
signal D:std_logic_vector(2 downto 0);
begin
--state memory
process(CLK)
begin
if CLK'event and CLK='1' then Q<=D;end if;
end process;
--next state logic
process(Q,RESTART)
begin
case Q is
when "000"=> D<="001";
when "001"=> D<="010";
when "010"=> D<="011";
when "011"=> D<="100";
when "100"=> D<="101";
when "101"=> D<="101";
when "110"=> D<="110";
when "111"=> D<="111";
when others => D<="000";
end case;
if (Q="101" or Q="110" or Q="111") and RESTART='1' then D<="000"; end if;
end process;
--output logic
FAULT<='1' when (Q="110" or Q="111") else '0';
end Behavioral;

3 points entity ( -1 for each unnecessary signal except Q)

3 points initialization of Q
4 points Counts up to 5 with CLK and stops
4 points RESTART (works at 5 2 points, works at 6,7 2 points)
 4 points FAULT
2 points Is not self correcting

-2 points for each simple VHDL mistake

-3, -4, -5 points for each less simple and major VHDL mistakes

Another solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MT2_Q2_V2 is
Port ( CLK : in STD_LOGIC;
RESTART : in STD_LOGIC;
FAULT : out STD_LOGIC);
end MT2_Q2_V2;

architecture Behavioral of MT2_Q2_V2 is

signal Q:std_logic_vector(2 downto 0) :="000";
signal D:std_logic_vector(2 downto 0);
begin
--state memory
process(CLK)
begin
if CLK'event and CLK='1' then Q<=D;end if;
end process;
--next state logic
process(Q,RESTART)
begin
if (Q<"101") then D<=Q+1; else D<=Q; end if;
if (Q="101" or Q="110" or Q="111") and RESTART='1' then D<="000"; end if;
end process;
--output logic
FAULT<='1' when (Q="110" or Q="111") else '0';
end Behavioral;

Another solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MT2_Q2_V4 is
Port ( CLK : in STD_LOGIC;
RESTART : in STD_LOGIC;
FAULT : out STD_LOGIC);
end MT2_Q2_V4;

architecture Behavioral of MT2_Q2_V4 is

signal Q:std_logic_vector(2 downto 0) :="000";
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if (Q<"101") then Q<=Q+1; else Q<=Q; end if;
if (Q="101" or Q="110" or Q="111") and RESTART='1' then Q<="000"; end if;
end if;
end process;
FAULT<='1' when (Q="110" or Q="111") else '0';
end Behavioral;

Another solution (RESTART is asynchronous)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MT2_Q2_V3 is
Port ( CLK : in STD_LOGIC;
RESTART : in STD_LOGIC;
FAULT : out STD_LOGIC);
end MT2_Q2_V3;

architecture Behavioral of MT2_Q2_V3 is

signal Q:std_logic_vector(2 downto 0) :="000";
signal D:std_logic_vector(2 downto 0);
begin
--state memory
process(CLK,RESTART)
begin
if CLK'event and CLK='1' then Q<=D;end if;
if (Q="101" or Q="110" or Q="111") and RESTART='1' then Q<="000"; end if;
end process;
--next state logic
process(Q,RESTART)
begin
if (Q<"101") then D<=Q+1; else D<=Q; end if;
if (Q="101" or Q="110" or Q="111") and RESTART='1' then D<="000"; end if;
end process;
--output logic
FAULT<='1' when (Q="110" or Q="111") else '0';
end Behavioral;
 Q3. (Total of 20 points)
Design and draw the counter described in Question 1 using D flip flops with active
low PR and CLR controls. Show all steps of the FSM design procedure except the
timing diagrams (optional). Look at the appendix for FSM design procedure.

SOLUTION:
There are 6 states and therefore we need 3 ffs, say Q2, Q1, and Q0.
State-Output diagram:
R=1
R is
Power ON
RESTART
0 R=1 R=0
5
(0)
(0)
6 R=0
1 (1)
(0) 4
(0)

7
(1) R=0
2
(0) 3
(0) R=1

Next state table

Q2 Q1 Q0 R Q2* Q1* Q0*
0 0 0 0 0 0 1
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 1 0 1
1 0 1 0 1 0 1
1 0 1 1 0 0 0
1 1 0 0 1 1 0
1 1 0 1 0 0 0
1 1 1 0 1 1 1
1 1 1 1 0 0 0
 Q2

Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 0 0 1 1

1 5 13 9
01 0 0 0 1

3 7 15 11 R
11 0 1 0 0

Q0 2 6 14 10
10 0 1 1 1

Q1

D2 = Q2R’+Q2Q1’Q0’+ Q2’Q1Q0

Q2

Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 0 1 1 0

1 5 13 9
01 0 1 0 0

3 7 15 11 R
11 1 0 0 0

Q0 2 6 14 10
10 1 0 1 0

Q1

D1 = Q2’Q1’Q0+Q2’Q1Q0’+ Q2Q1R’
 Q2
Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 1 1 0 1

1 5 13 9
01 1 1 0 1

3 7 15 11 R
11 0 0 0 0

Q0 2 6 14 10
10 0 0 1 1

Q1
D0 = Q2’Q0’+Q1’Q0’+ Q2Q0R’

Output table
Q2 Q1 Q0 FAULT
0 0 0 0 Q2
0 0 1 0 Q2Q1
00 01 11 10
0 1 0 0 Q0
0 1 1 0 0 0 1
0 0
1 0 0 0
1 0 1 0
Q0 1 0 0 1 0
1 1 0 1
1 1 1 1
Q1

FAULT = Q2Q1
 +5v

D2 PR Q2
D Q

CLK Q
CLR

P FAULT
RSTART = Q2 Q1 FAULT

+5v

D2 = Q2R’+Q2Q1’Q0’ PR Q1
D1
+ Q2’Q1Q0 D Q
D1 =Q2’Q1’Q0+Q2’Q1Q0’
+Q2Q1R’
D0 = Q2’Q0’+Q1’Q0’ CLK
+ Q2Q0R’ CLR +5v

P
or
RESET IC
+5v P for
generating
D0 PR P
D Q Q0

clock CLK
CLR

5 points State/output diagram and number of ffs (-1 for outputs, -1 for n of ffs, -1 for
unused states, -1 for Power ON)
1 points State encoding
3 points Next state table and excitation table (-2 for don’t cares)
3 points Minimized next state logic
2 points Output table
2 points Minimized output logic
4 points Circuit ( 2 points) with initialization (2 points)
 Let us see if the FSM becomes self correcting if for the unused states we don’t care
what the next state is for when RESTART = 0:
Next state table
Q2 Q1 Q0 R Q2* Q1* Q0*
0 0 0 0 0 0 1
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 1 0 1
1 0 1 0 1 0 1
1 0 1 1 0 0 0
1 1 0 0 d d d
1 1 0 1 0 0 0
1 1 1 0 d d d
1 1 1 1 0 0 0

Q2

Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 0 0 d 1

1 5 13 9
01 0 0 0 1

3 7 15 11 R
11 0 1 0 0

Q0 2 6 14 10
10 0 1 d 1

Q1

D2 = Q2R’+Q2Q1’Q0’+ Q2’Q1Q0
 Q2

Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 0 1 d 0

1 5 13 9
01 0 1 0 0

3 7 15 11 R
11 1 0 0 0

Q0 2 6 14 10
10 1 0 d 0

Q1

D1 = Q2’Q1’Q0+ Q2’Q1Q0’

Q2
Q2Q1
00 01 11 10
Q0R 0 4 12 8
00 1 1 d 1

1 5 13 9
01 1 1 0 1

3 7 15 11 R
11 0 0 0 0

Q0 2 6 14 10
10 0 0 d 1

Q1
D0 = Q2 Q0 + Q2R’ + Q1’Q0’
’ ’
 Next state table
Q2 Q1 Q0 R Q2* Q1* Q0*
0 0 0 0 0 0 1
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 1 0 1
1 0 1 0 1 0 1
1 0 1 1 0 0 0
1 1 0 0 1 0 1
1 1 0 1 0 0 0
1 1 1 0 1 0 1
1 1 1 1 0 0 0

The FSM is now self correcting which is not desired.

The above designs are Moore designs. However from the word description one may also
interpret that the RESTART signal is effective immediately without wating for a clock
tick. This means a Mealy FSM. Such a solution is also acceptable.
 Q4. (Total of 20 points)
Consider the implementation of a 3-bit two’s complement adder-subtractor with
mode control (mode control = 0 means A+B, mode control = 1 means A-B), carry
output, and two’s complement overflow output, using a single Nx5 ROM.
a. (3 points) Determine N.
b. (5 points) Label the IO pins of the ROM appropriately and make your signal
connections (Draw your circuit).
c. (6 points) With reference to your IO labeling, list all rows of your ROM table
that corresponds to the case when the first operand A is “101”. In your list,
indicate the data value and the ROM address for each of your entries.
d. (6 points) With reference to your IO labeling, list all rows of your ROM table
that corresponds to the case when the second operand B is “011”. In your list,
indicate the data value and the ROM address for each of your entries.
SOLUTION:
a. N = 27=128 (Two 3-bit numbers, and one mode control input)
b.
B0 A0

B1 A1 D0 R0

B2 A2 D1 R1

A0 A3 D2 R2

A1 A4 D3 Cout

A2 A5 D4 OVF

MC A6
-2 for not labeling the internal signals
c.
A6 A5 A4 A3 A2 A1 A0 D4 D3 D2 D1 D0
A B MC A2 A1 A0 B2 B1 B0 OVF CO R2 R1 R0 R RC
-3 0 0 1 0 1 0 0 0 0 0 1 0 1 -3 -3
-3 1 0 1 0 1 0 0 1 0 0 1 1 0 -2 -2
-3 2 0 1 0 1 0 1 0 0 0 1 1 1 -1 -1
-3 3 0 1 0 1 0 1 1 0 1 0 0 0 0 0
-3 -4 0 1 0 1 1 0 0 1 1 0 0 1 1 -7
-3 -3 0 1 0 1 1 0 1 1 1 0 1 0 2 -6
-3 -2 0 1 0 1 1 1 0 1 1 0 1 1 3 -5
-3 -1 0 1 0 1 1 1 1 0 1 1 0 0 -4 -4
-3 0 1 1 0 1 0 0 0 0 1 1 0 1 -3 -3
-3 1 1 1 0 1 0 0 1 0 1 1 0 0 -4 -4
-3 2 1 1 0 1 0 1 0 1 1 0 1 1 3 -5
-3 3 1 1 0 1 0 1 1 1 1 0 1 0 2 -6
-3 -4 1 1 0 1 1 0 0 0 1 0 0 1 1 1
-3 -3 1 1 0 1 1 0 1 0 1 0 0 0 0 0
-3 -2 1 1 0 1 1 1 0 0 0 1 1 1 -1 -1
-3 -1 1 1 0 1 1 1 1 0 0 1 1 0 -2 -2
Addresses are 40, 41, ... , 47, 104, 105. ... , 111
d.
A6 A5 A4 A3 A2 A1 A0 D4 D3 D2 D1 D0
A B MC A2 A1 A0 B2 B1 B0 OVF CO R2 R1 R0 R RC
0 3 0 0 0 0 0 1 1 0 0 0 1 1 3 3
1 3 0 0 0 1 0 1 1 1 0 1 0 0 -4 4
2 3 0 0 1 0 0 1 1 1 0 1 0 1 -3 5
3 3 0 0 1 1 0 1 1 1 0 1 1 0 -2 6
-4 3 0 1 0 0 0 1 1 0 0 1 1 1 -1 -1
-3 3 0 1 0 1 0 1 1 0 1 0 0 0 0 0
-2 3 0 1 1 0 0 1 1 0 1 0 0 1 1 1
-1 3 0 1 1 1 0 1 1 0 1 0 1 0 2 2
0 3 1 0 0 0 0 1 1 0 0 1 0 1 -3 -3
1 3 1 0 0 1 0 1 1 0 0 1 1 0 -2 -2
2 3 1 0 1 0 0 1 1 0 0 1 1 1 -1 -1
3 3 1 0 1 1 0 1 1 0 1 0 0 0 0 0
-4 3 1 1 0 0 0 1 1 1 1 0 0 1 1 -7
-3 3 1 1 0 1 0 1 1 1 1 0 1 0 2 -6
-2 3 1 1 1 0 0 1 1 1 1 0 1 1 3 -5
-1 3 1 1 1 1 0 1 1 0 1 1 0 0 -4 -4
Addresses are 3, 11, 19, ... , 51, 59, 67, 75, ..., 123
+1 point for knowing two’s complement binary addition
+1 point for knowing two’s complement binary subtraction
 Q5. (20 points)

Using combinational logic and D flip-flops as in the first figure below, design a
counter that has an active-high enable control, and counts in the following order
when enable is asserted: 000, 001, 011, 010, 110, 111, 101, 100, 000, ... . If enable is
unasserted then the counter stops counting and stays in the present count. Make sure
that Power-ON state is 000. Assume the availability of a reset IC as in the second
figure below.

SOLUTION:

Power ON 0
0
0 7
1
1 6 0
1
1
0 1 1

5
1 0

2 1
0
1 3 4

0
0
 Next state table
Q2 Q1 Q0 EN Q2* Q1* Q0*
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 1 1
0 1 0 0 0 1 0
0 1 0 1 1 1 0
0 1 1 0 0 1 1
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 1
1 0 1 1 1 0 0
1 1 0 0 1 1 0
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 0 1

Q2

Q2Q1
00 01 11 10
Q0EN 0 4 12 8
00 0 0 1 1

1 5 13 9
01 0 1 1 0

3 7 15 11 EN
11 0 0 1 1

Q0 2 6 14 10
10 0 0 1 1

Q1

D2 = Q2EN’+ Q2Q0 +Q1Q0’EN

 Q2

Q2Q1
00 01 11 10
Q0EN 0 4 12 8
00 0 1 1 0

1 5 13 9
01 0 1 1 0

3 7 15 11 EN
11 1 1 0 0

Q0 2 6 14 10
10 0 1 1 0

Q1

D1 = Q2’Q0EN+ Q1Q0’ +Q1EN’

Q2

Q2Q1
00 01 11 10
Q0EN 0 4 12 8
00 0 0 0 0

1 5 13 9
01 1 0 1 0

3 7 15 11 EN
11 1 0 1 0

Q0 2 6 14 10
10 1 1 1 1

Q1

D0 = Q2’Q1’EN+ Q2Q1EN +Q0EN’

 Next state table
EN Q2 Q1 Q0 Q2* Q1* Q0*
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 1 0 0
0 1 0 1 1 0 1
0 1 1 0 1 1 0
0 1 1 1 1 1 1
1 0 0 0 0 0 1
1 0 0 1 0 1 1
1 0 1 0 1 1 0
1 0 1 1 0 1 0
1 1 0 0 0 0 0
1 1 0 1 1 0 0
1 1 1 0 1 1 1
1 1 1 1 1 0 1

EN

ENQ2
00 01 11 10
Q1Q0 0 4 12 8
00 0 1 0 0

1 5 13 9
01 0 1 1 0

3 7 15 11 Q0
11 0 1 1 0

Q1 2 6 14 10
10 0 1 1 1

Q2

D2 = EN’Q2+ Q2Q0 + ENQ1Q0’

 EN

ENQ2
00 01 11 10
Q1Q0 0 4 12 8
00 0 0 0 0

1 5 13 9
01 0 0 0 1

3 7 15 11 Q0
11 1 1 0 1

Q1 2 6 14 10
10 1 1 1 1

Q2

D1 = EN’Q1+ ENQ2’Q0 + Q1Q0’

EN

ENQ2
00 01 11 10
Q1Q0 0 4 12 8
00 0 0 0 1

1 5 13 9
01 1 1 0 1

3 7 15 11 Q0
11 1 1 1 0

Q1 2 6 14 10
10 0 0 1 0

Q2

D0 = EN’Q0+ ENQ2Q1 + ENQ2’Q1’

 +5v

D2 PR Q2
D Q

CLK Q
CLR

+5v

D2 = EN’Q2+ Q2Q0 + ENQ1Q0’ PR Q1

D1
D Q
D1 = EN’Q1+ ENQ2’Q0 + Q1Q0’
EN
D0 = EN’Q0+ ENQ2Q1 + ENQ2’Q1’ CLK
CLR

+5v

D0 PR
D Q Q0

clock CLK
CLR

4 points 3 ffs +clock

4 points Initiation using P
12 points Next state logic (4+4+4) (if only for EN=1 then -6 points)
 For EN = 1 the next state table is
Q2 Q1 Q0 Q2* Q1* Q0*
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 1 1
1 1 1 1 0 1

Q2

Q2Q1
00 01 11 10
Q0 0 2 6 4
0 0 1 1 0

1 3 7 5

Q0 1 0 0 1 1

3 7 15 11

Q1
D2 = Q2Q0 + Q1Q0’

Q2

Q2Q1
00 01 11 10
Q0 0 2 6 4
0 0 1 1 0

1 3 7 5

Q0 1 1 1 0 0

3 7 15 11

Q1
D1 = Q2’Q0 + Q1Q0’
 Q2

Q2Q1
00 01 11 10
Q0 0 2 6 4
0 1 0 1 0

1 3 7 5

Q0 1 1 0 1 0

3 7 15 11

Q1
’
D0 = Q2Q1 + Q2 Q1’
Some VHDL Templates:
ENTITY DECLARATION
entity entity_name is
generic ( constant_names : constant type;
constant_names : constant type;
…
constant_names : constant type);
port ( signal_names : mode signal_type;
signal_names : mode signal_type;
…
signal_names : mode signal_type);
end entity_name;
ARCHITECTURE DEFINITIONS
architecture architecture-name of entity-name is
type declarations
signal declarations
constant declarations
function definitions
procedure definitions
component declarations
begin
concurrent statement
...
concurrent statement
end architecture-name;
COMPONENT DECLARATION
component component_name
port ( signal_names : mode signal type;
signal_names : mode signal type;
…
signal_names : mode signal type);
end component;
COMPONENT INSTANTIATION
label: component_name port map (signal1, signal2, …,signaln);
or,
label: component_name port map (port1 =>signal1, port2 =>signal2, …, portn =>signaln);

DATAFLOW TYPE STATEMENTS:

Simple concurrent assignment statement

signal_name <= expression;
Conditional concurrent assignment statement
signal_name <=
expression when boolean-expression else
expression when boolean-expression else
…
expression when boolean-expression else
expression;
with-select statement
with expression select
signal_name <= signal_value when choices,
signal_value when choices,
…
signal_value when choices;

Note that conditional concurrent assignment statement and with-select statement cannot be used in a
process statement. Instead, in a process, one can use the the sequential conditional assignment statements
if and case.
BEVAVIORAL TYPE STATEMENTS:

process statement
process(signal_name, signal_name, …, signal_name)
type_declarations
variable declarations
constant declarations
begin
sequential-statement
…
sequential-statement
end process;
Simple sequential assignment statement
signal_name <= expression;
if statement in its general form
if boolean_ expression then sequential_statements
elsif boolean_ expression then sequential_statements
…
elsif boolean_ expression then sequential_statements
else sequential_statements
end if;
Note that you may not use the else and/or the elsif.
case-when statement
case expression is
when choices => sequential_statements
…
when choices => sequential_statements
end case;
loop statement
loop
sequential_statement
…
sequential_statement
end loop;
for-loop statement
for identifier in range loop
sequential_statement
…
sequential_statement
end loop;
while statement
while boolean_expression loop
sequential_statement
…
sequential_statement
end loop;

Note that the if, case, loop, for, and while statements are called sequential statements and they can only be
used in a process statement. Also note that each process is one concurrent statement.
Concatenation operator & is used as follows: If A and B are 2 bit numbers then A&B is a four bit number
with A being more significant.
STAGES OF FINITE STATE MACHINE DESIGN

1. Word description
2. Sample waveforms. This stage is optional but makes you understand the problem
better.
3. State definitions and state/output diagram. At this stage the required number of
flip flops is also determined.
4. State encoding ( state assignment)
5. Next state table ( this table is also called transition table)
6. Decide on the type of flip flop
7. Excitation table
8. Obtain minimized functions for next state logic circuit
9. Output table
10. Obtain minimized functions for output logic circuit
11. Draw the circuit including initialization
 BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
MidTerm Exam II SOLUTION
29-04-2006
Duration 110 minutes

Surname:_______________________________________

Name:_____________________________________

ID-Number:_________________________________________

Signature:________________________________________

There are 5 questions of equal weights. Total weight of the exam is 110
points (10 points bonus). Solve all. Do not detach pages.
Show all your work.

Q1
Q2
Q3
Q4
Q5
TOTAL
Q1. For the circuit below obtain and write excitation table, output table, next state
table, and also the state definitions and diagram. Is this a Moore or Mealy FSM,
why? X is the input and Y1Y0 is the output of this circuit. Explain the function of the
RESET input, and include it in your state diagram.
SOLUTION:

PR
D Q Y1
X

Q
clock CLK
CLR

+5v

+5v

PR Y0
D Q

CLK Q
CLR

RESET

SOLUTION:
 D1 PR Q1
D Q Y1
X

Q
clock CLK
CLR

+5v

+5v

D0 PR Q0 Y0
D Q

CLK Q
CLR

RESET

Excitation Equations: D1 = XQ0 and D0 = Q1’

Excitation table is
Q1 Q0 X(at D1 D0
tick)
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0

Next state table is the same as the excitation table with D1 replaced by Q1* and D0
replaced by Q0*.
Output equations: Y1 = Q1 and Y0 = Q0
Output table
Q1 Q0 Y1 Y0
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

State Encoding
name Q1 Q0
S0 0 0
S1 0 1
S2 1 0
S3 1 1

State diagram

S0
(Y1’Y0’)
1 1

S1 S2
X’ X’ RESET
(Y1’Y0) (Y1Y0’)

X X
S3
(Y1Y0)

Note that I have indicated in the state circles also the outputs, and therefore the above
diagram is in fact a state/ouput diagram.

RESET is an asynchronous input which makes the FSM go to state S2 independent of

the clock.
This FSM is a Moore FSM if do not consider RESET as a proper input.
It is a Mealy FSM if we consider RESET as a proper input as well.

Q2. Write VHDL code for a 3-to-8 generic decoder (with enable), which has all
inputs and and outputs active-high, using structural type programming using
two instances of the following module which is already available in the library.
SOLUTION:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cat is
Port ( E : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(0 to 3));
end cat;

architecture Behavioral of cat is

signal temp:std_logic_vector(0 to 3);
begin
with S select temp <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when "11",
"0000" when others;
Y <= temp when E = '1' else "0000";
end Behavioral;

Solution:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
Port ( EN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
DECOUT : out std_logic_vector(0 to 7));
end top;

architecture Behavioral of top is

component cat is
Port ( E : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(0 to 3));
end component;
signal G0,G1:std_logic_vector(0 to 3);
signal Z0,Z1:std_logic;
signal SS:std_logic_vector(1 downto 0);
begin
SS<= SEL(1)&SEL(0);
Z0<= EN and not SEL(2);
Z1<=EN and SEL(2);
L1: cat port map (Z0,SS,G0);
L2: cat port map (Z1,SS,G1);
DECOUT<=G0&G1;
end Behavioral;

Q3. For the circuit and the clock signal shown below, Q2 = X, Q1 = Y, and Q0 =
‘0’ before time t1. Draw time waveforms for A0,A1,B0,B1,C0, and C1 so that Q2
= Y, and Q1 = X after time t3 (in other words the values of Q2 and Q1 are
switched).

A0 A1

Q2
D Q

CLK Q

B0 B1

Q1
D Q

clock CLK Q

C0 C1

Q0
D Q

CLK Q

clock

t1 t2 t3
SOLUTION:
As announced during the exam we assume if a ff’s input is at high Z then its output is
not changed at a clock tick. (Of course it is possible to include circuitry to guarantee
this assumption but it makes the circuit look very complicated, therefore it was not
drawn).

t1 t2 t3

clock

X X Y Y
Q2

Y Y Y X
Q1

0 X X X
Q0

A0

A1

B0

B1

C0

C1

For your information: One possible way of guaranteeing the above assumption is to
gate the clock. For example (shown only for the first ff) the following circuit does it.
 A0

D Q

clock CLK Q

Q4. The internal circuit of a PAL which has 2 input pins and 3 input-output pins
is drawn below. In this PAL, AND gate inputs are ’1’ if they are not connected.
Implement the function F = A’B’ + BC’ + ABC using this PAL. Do not simplify
or modify the expression. Do not use any external wire or component.
SOLUTION:

I0

I1

IO0

IO1

IO2

To avoid any confusion, the pin diagram (excluding ground and supply connections)
of the above PAL is given below:
 I0 IO0
PAL
I1 IO1

IO2

Solution: Say Y = A’B’ + BC’. Then F = Y + ABC

B
C

A’B’ BC’
C

Y
Q5. We have 2-to-1 multiplexers in stock. These have active-high pins and the
block diagram is as follows:

EN
2-to-1
I0 mux Y

I1
S

a) Design and draw a circuit which implements this 2-to-1 multiplexer, using
NAND and NOT gates.

b) Use 3 of these 2-to-1 multiplexers, a 2-to-4 decoder, and additional minimum

number of simple gates to realize a 6-to-1 multiplexer which has the following
properties: It has three control inputs S2, S1, S0, six data inputs D0, D1, D2, D3,
D4, D5 and two outputs OUT and ERROR. It has the following function table:

Function S2 S1 S0 OUT ERROR

(choose) 0 0 0 D0 0
(choose) 0 0 1 D1 0
(choose) 0 1 0 D2 0
(choose) 0 1 1 D3 0
(choose) 1 0 0 D4 0
(choose) 1 0 1 D5 0
(disable) 1 1 0 0 0
(error) 1 1 1 0 1
SOLUTION:

a)
EN S Y
0 0 0
0 1 0
1 0 I0
1 1 I1

Thus Y = EN.S’.I0 + EN.S.I1

EN

I0

Y
S

I1

b)
 EN
2-to-1
D0 I0 mux Y
D1 I1
S

S0

EN
2-to-1
D2 I0 mux Y OUT
1 EN Y0
D3 I1
S
Y1
S1 SD0
Y2 S0
S2 SD1
Y3

2-to-4 EN
dec 2-to-1
D4 I0 mux Y

D5 I1
S

S0

S0 ERROR
 BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
Midterm Exam-2
SOLUTION
20-12-2006

Duration 120 minutes

Surname: ________________________________

Name: ________________________________

ID-Number: ________________________________

Signature: ________________________________

There are 7 questions. Solve all.

Do not detach pages. Show all your work.

Q1
Q2
Q3
Q4
Q5
Q6
Q7
Total
Q1. (20 points)
Design a Finite State Machine with one input and two outputs that counts the number of
1’s in the input according to mod 4. Note that initially, the number of 1’s is zero.

Show all your design steps including state definition, state diagram, state encoding, next
state table, output table, excitation table and minimization of the combinatorial circuits.
Draw your circuit.

Solution:

State definitions and state encoding:

states definition Q1 Q0
S0 Initial state, number of 1s is 0 0 0
S1 Number of 1s is 1 (mod 4) 0 1
S2 Number of 1s is 2 (mod 4) 1 0
S3 Number of 1s is 3 (mod 4) 1 1

State/output diagram:
Power ON
0 S0
(00)
1
1
0 S1 S3
(01) (11) 0

1 1
S2
(10)

0
Next State and excitation table:
Q1 Q0 X Q1*=D1 Q0*=D0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
Minimization of next state circuit:
D1: D0:
Q1Q0 Q1 Q1Q0 Q1
X X

0 0 1 1 0 1 1 0

0 1 0 1 1 0 0 1

Q0 Q0

D1 = Q1X’ + Q1 Q0’+ Q1’ Q0X D0 = Q0X’+ Q0’X

Output table and output circuit minimization:

Q1 Q0 Y1 Y0
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
Y1=Q1, Y0=Q0

D1 PR Q1
Q1X’ + Q1 Q0’+ Q1’ Q0X D Q Y1

Q
clock CLK Q1’
CLR

P
RESET
IC P

D0 PR
Q0X’+ Q0 X ’ Q0 Y0
D Q

clock CLK Q Q0’

CLR

P
Q2. (15 Points)
Write down the function table (compressed truth table) of the following circuit indicating
what the circuit does for each case of the select inputs S1 and S0. What are IN1 and IN2?

Q0 0
Mux
IN1 1 Y D Q Q0
Q1 2
A 3 S1 S0
CLK Q
S1 S0

Q1 0
Mux
Q0 1 Y D Q Q1
Q2 2
B 3 S1 S0
CLK Q
S1 S0

Q2 0
Mux
Q1 1 Y
Q3 2 D Q Q2
C 3 S1 S0
S1 S0 CLK Q

Q3 0
Mux
Q2 1 Y Q3
D Q
IN2 2
D 3 S1 S0
S1 S0 CLK Q

Clock
Solution:

S1 S0 Clock Q3 Q2 Q1 Q0
0 0 ↑ Q3 Q2 Q1 Q0 Hold
0 1 ↑ Q2 Q1 Q0 IN1 Shift Left
1 0 ↑ IN2 Q3 Q2 Q1 Shift Right
1 1 ↑ D C B A Load
IN1 is shift left input. IN2 is shift right input.
Q3. (10 points)
Find three different minimal sum-of-products (SOP) for the following function by using
the following K-map.

∑ A, B ,C , D
(0, 2, 6, 7,8, 9,13)

AB
CD

Solution:

AB
A
CD
1 0 0 1
F1 = A ' BC + AC ' D + B ' C ' D '+ A ' B ' D '
0 0 1* 1 F2 = A ' BC + AC ' D + B ' C ' D '+ A ' CD '
F3 = A ' BC + AC ' D + A ' B ' D '+ AB ' C '
D
0 1* 0 0

C
1 1 0 0

B
Q4. (10 points)

F=ΣA,B,C,D (0,1,2,5,8,9,10) + d(11)

Find all minimal product-of-sums (POS) expressions for F by using the following K-map.

AB
CD

Solution:

AB
A
CD
1 0* 0 1
F = ( B '+ D)( A '+ B ')(C '+ D ')
1 1 0* 1

D
0* 0 0 d

C
1 0 0 1

B
Q5. (15 points)
Design a counter that counts in the following sequence by using the MSI package
74X163 given the pin diagram as below. (You may use additional simple logic gates.)

Count sequence: 5-6-7-8-5-6-7-8....

Use the below described reset IC to initially load 5 to the output during T.
Is your counter self correcting? Explain why or why not.

RESET
IC P
1

0 time
T

POWER
ON
(T is larger than the clock period)

(LSB)
Solution:

1
P

1
1
1 (lsb)
0
1
0

Above circuit is self correcting. If it goes to 0,1,2,3, or 4 then it counts up and

eventually reaches 5. If it goes to 9,10,11,12,13,14, or 15 then it loads 5.
or;

1
P

1
1
1 (lsb)
0
1
0

Above circuit is self correcting. If it goes to 0 it will load 5. If it goes to 1,2,3, or 4

then it counts up and eventually reaches 5. If it goes to 9,10,11,12,13,14, or 15 then it
counts up until it becomes 0 and then loads 5.
Q6. (15 points)
You are to implement the function F = A’BC’ + ABC + A’C’ + AB’C’ using a simple
PAL which has 5 inputs and 3 outputs with each OR gate having 2 inputs. The inputs of
each OR gate are different from the inputs of the inputs of the other OR gates. Draw the
internal structure of the PAL, show the fuses which are to be left intact, and also show all
the outside connections. Multilevel implementation is acceptable. Do not attempt to
simplify the function. No other gates are allowed.

Solution:

F
Q7. (15 points)
Draw the state/output diagram of the FSM described by the following VHDL code. Is this
a Moore or a Mealy FSM? Why? What does this FSM do? Hint: When does the output
become ‘1’?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_rec is
port(CLK,RESET,X: in std_logic;
Z:out std_logic);
end seq_rec;

architecture Behavioral of seq_rec is

type state_type is(A,B,C,D);
signal state, next_state :state_type;
begin
state_register: process(CLK,RESET)
begin
if (RESET='1') then
state<=A;
elsif (CLK'event and CLK='1') then
state<=next_state;
end if;
end process;
next_state_fuction: process(X,state)
begin
case state is
when A=>
if X='1' then next_state<=B; else next_state<=A; end if;
when B=>
if X='1' then next_state<=C; else next_state<=A; end if;
when C=>
if X='1' then next_state<=C; else next_state<=D; end if;
when D=>
if X='1' then next_state<=B; else next_state<=A; end if;
end case;
end process;
output_function:process(X,state)
begin
case state is
when A=> Z<='0';
when B=> Z<='0';
when C=> Z<='0';
when D=> if X='1' then Z<='1'; else Z<='0'; end if;
end case;
end process;
end Behavioral;
Solution:

Reset (synchronous)
0,0
A
0,0
1,0
0,0
1,1
B D

1,0 0,0

1,0

This is a Mealy FSM because output depends also on the present input.
The output is ‘1’ if the present input is ‘1’ and the last received three inputs are
“110”.

Actually since Reset is synchronous the proper way of drawing the state/output
diagram is as follows: (In the following diagram since we have two inputs R and X,
where R is Reset, in order to avoid to many arrows we have used expressions on the
arrows. On each arrow there are two expressions, first is for the inputs, second is for
the output).
 R,Z’

R+X’,Z’
A
R+X’,Z’
R’X,Z’
R+X’,Z’
R’X,Z
B D

R’X,Z’ R’X’,Z’

R’X,Z’

Some students have drawn a Power ON signal like

Power ON

This is not correct because if this were desired then in the VHDL code we should
have had
signal state : state_type :=A;
signal next_state : state_type;
meaning that the initial (power ON) value of the state is A.
 BILKENT UNIVERSITY
Department of Electrical and Electronics Engineering
EEE102 Introduction to Digital Circuit Design
MidTerm Exam II
SOLUTION
2-5-2005

Q1. (12 points) Implement the function F = AB’ + CD’ using

a) a generic 8-to-1 multiplexer using extra inverters only, if necessary.
b) a generic 4-to-1 multiplexer using extra inverters and one extra AND or OR gate only, if
necessary.
c) two 2-to-4 generic decoders, using one axtra OR gate, if necessary.
In your solutions label all terminals and all internal and external signals.
Solution:
a)
There are other solutions
1

EN
0 I0
D I1
0 I2
I3
1 I4 OUT F
1 I5
0 I6
I7

S2 S1 S0
0
A B C
b)
There are other solutions
1

EN
I0
C I1
OUT F
1 I2
D I3
S1 S0

A B
c)

EN
Y0
Y1
A S1 Y2
B S0 Y3

F
1

EN
Y0
Y1
C S1 Y2
D S0 Y3
Q2. (13 points) Design and draw a 16-to-1 multiplexer using two 8-to-1 multiplexers and one
2-to-4 decoder. The 8-to-1 multiplexers and the 2-to-4 decoder are generic in the sense that
they have one enable each and all of their signals are active high. The 16-to-1 multiplexer that
you will design will also be generic with one enable and active high signals. You can use
minimum number of additional simple gates.
Solution:

EN

X0 I0
X1 I1
X2 I2
X3 I3
X4 I4 OUT
X5 I5
X6 I6
X7 I7

S2 S1 S0
0
B C D
ENABLE EN Y0
Y1
A S0 Y2
F
0 S1 Y3
EN

X8 I0
X9 I1
X10 I2
X11 I3
X12 I4 OUT
X13 I5
X14 I6
X15 I7

S2 S1 S0
0
B C D
Q3. (15 points) Implement the function F = AB+C’D+ABD’ using the PAL shown below (do
not change the function). Show the fuses which are to be left intact, and also show all the
outside connections if any.
Solution:

G = AB+C’D => F = G + ABD’

Q4. (15 points) A synchronous clocked FSM has 3 states called A, B and C. The machine
starts with state A at Power ON. This FSM has an input called HOLD. IF HOLD = ‘1’ at a
clock tick then the machine does not change state. If HOLD = ‘0’ however, with the positive
edge of the clock signal it goes to B if it is in A, goes to C if it is in B, and goes to B if it is in
C. It has 2 outputs Y1 and Y0. Y1Y0 is “00” if the FSM is in state A, is “01” if in state B and is
“10” if in state C. Design and draw this FSM using D ffs. Show all your design steps
including state/output diagram, state encoding, next state table, output table, excitation table
and minimization of the combinatorial circuits. Draw your circuit. Use RESET IC for
initialization. (By proper labeling you need not draw long lines, but draw the gates.)

Solution:

1
POWER ON A
(00)

0 0

B C
(01) (11)

0 1
1

3 states => 2 flip flops. Call their output Q1 and Q0.

State Encoding
Q1 Q0
A 0 0
B 0 1
C 1 0

Next State Table. X is for HOLD

Q1 Q0 X Q1* Q0*
A 0 0 0 0 1
A 0 0 1 0 0
B 0 1 0 1 0
B 0 1 1 0 1
C 1 0 0 0 0
C 1 0 1 1 0
1 1 0 d d
1 1 1 d d

Excitation table is the same with Q1* replaced by D1 and Q0* by D0.
Minimized Next State Logic
D1: D0:
Q1Q0 Q1 Q1Q0 Q1
X X

0 1 d 0 1 0 d 0

0 0 d 1 0 1 d 0

Q0 Q0

D1 = Q0X’+Q1X D0 = Q1’Q0’X’+Q0X

Output Table

Q1 Q0 Y1 Y0
A 0 0 0 0
B 0 1 0 1
C 1 0 1 0
1 1 d d
Therefore
Y1 = Q1 and Y0 = Q0
Circuit including initialization

+5v
X X’
D1 PR Q1
D Q Y1
Q0
X’
Q1 Q1’
X clock CLK
CLR

+5v
Q0’
Q1’ X’ D0 PR Q0
D Q Y0
Q0
X
clock CLK Q0’
+5v CLR

P
RESET
IC P
 Q5. (15 points) A Mealy FSM has the following state/output diagram. This FSM has two
inputs X and Y, and a single output Z. On each arrow there are two expressions separated
by a comma. The first expression is about the inputs and the second expression is about
the output. These expressions are used to express the values of X, Y and Z in compact
form. For example XY means X=1 and Y=1. In other words these are the values of X and
Y which make the expression XY TRUE, that is, 1. Similarly Z’ means the output is 0
because if Z=0 then the expression Z’ is TRUE, that is 1.

Power X’+Y’,Z’
S0
ON

X’+Y’,Z’ XY,Z’

S1

XY,Z

Design and draw this FSM using JK

ffs. Show all your design steps including state encoding, next state table, output table,
excitation table and minimization of the combinatorial circuits. Draw your circuit. Use
RESET IC for initialization. (By proper labeling you need not draw long lines, but draw the
gates.)
Solution:

2 states . 1 ff. Call its output Q.

State Encoding
Q
S0 0
S1 1
Next State and Excitation Table together.
Q X Y Q* J K
S0 0 0 0 0 0 d
S0 0 0 1 0 0 d
S0 0 1 0 0 0 d
S0 0 1 1 1 1 d
S1 1 0 0 0 d 1
S1 1 0 1 0 d 1
S1 1 1 0 0 d 1
S1 1 1 1 1 d 0

Minimized Next state Logic

^
J: K:
QX Q QX Q
Y Y

0 0 d d d d 1 1
1

0 1 d d d d 0 1

X X

J = XY K = X’+Y’

Output Table

Q X Y Z
S0 0 0 0 0
S0 0 0 1 0
S0 0 1 0 0
S0 0 1 1 0
S1 1 0 0 0
S1 1 0 1 0
S1 1 1 0 0
S1 1 1 1 1

Z = QXY
Circuit with initialization:

Y Y’

X X’

+5v

X PR Q Z
J Q
Y
clock
CLK
X’ Q Q’
K
Y’ CLR

+5v

RESET
IC P
Q6. (15 points) The VHDL code for an entity called BRICK is already written and included
in the library. The entity definition for BRICK is as follows.

entity BRICK is
port(A,B:in std_logic;
Y:out std_logic );
end BRICK;

Write VHDL code for the circuit below. Some VHDL language templates are given in the
Appendix.

X0 A
Y
X1 B

A
Y Z

X2 A B
Y
X3 B

Solution:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
Port ( X : in std_logic_vector(3 downto 0);
Z : out std_logic);
end top;

architecture Structural of top is

component BRICK
Port ( A,B: in std_logic;
Y : out std_logic);
end component;
signal U,V:std_logic;
begin
label1:BRICK port map(X(0),X(1),U);
label2:BRICK port map(X(2),X(3),V);
label3:BRICK port map(U,V,Z);
end Structural;
Q7. (15 points) Write VHDL code for a 2-to-4 decoder which has two enables, one active low
and one active high, and active low outputs. Some VHDL language templates are given in the
Appendix.

Solution:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec2to4 is
Port ( EN : in std_logic;
EN_L : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end dec2to4;

architecture Behavioral of dec2to4 is

signal TEMP: std_logic_vector(3 downto 0);
begin
with S select
TEMP<="1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
Y<=TEMP when EN='1' and EN_L='0' else "1111";

end Behavioral;

Another solution:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec2to4_another is
Port ( EN : in std_logic;
EN_L : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end dec2to4_another;

architecture Behavioral of dec2to4_another is

begin
process(EN,EN_L,S)
begin
if EN='1' and EN_L = '0' then
case S is
when "00" => Y<="1110";
when "01" => Y<="1101";
 when "10" => Y<="1011";
when "11" => Y<="0111";
when others => Y<="1111";
end case;
else Y<= "1111";
end if;
end process;
end Behavioral;

Yet another solution:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec2to4_yet_another is
Port ( EN : in std_logic;
EN_L : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end dec2to4_yet_another;

architecture Behavioral of dec2to4_yet_another is

begin
process(EN,EN_L,S)
begin
if EN='1' and EN_L = '0' then
if S="00" then Y<="1110";
elsif S="01" then Y<="1101";
elsif S="10" then Y<="1011";
elsif S="11" then Y<="0111";
else Y<="1111";
end if;
else Y<="1111";
end if;
end process;
end Behavioral;
Appendix: Some VHDL language templates are given below:

COMPONENT DECLARATION
component component_name
port ( signal_names : mode signal type;
signal_names : mode signal type;
…
signal_names : mode signal type);
end component;
COMPONENT INSTANTIATION
label: component_name port map (signal1, signal2, …,signaln);
or
label: component_name port map (port1 =>signal1, port2 =>signal2, …, portn =>signaln);
for-generate LOOP
label: for identifier in range generate
concurrent-statement
end generate;
ENTITY DECLARATION
entity entity_name is
generic ( constant_names : constant type;
constant_names : constant type;
…
constant_names : constant type);
port ( signal_names : mode signal_type;
signal_names : mode signal_type;
…
signal_names : mode signal_type);
end entity_name;
CONCURRENT SIGNAL-ASSIGNMENT STATEMENT
signal_name <= expression;
or
signal_name <= expression when boolean-expression else
expression when boolean-expression else
…
expression when boolean-expression else
expression;
with-select STATEMENT
with expression select
signal_name <= signal_value when choices,
signal_value when choices,
…
signal_value when choices;

process STATEMENT
process(signal_name, signal_name, …, signal_name)
type_declarations
variable declarations
constant declarations
begin
sequential-statement
…
sequential-statement
end process;
if STATEMENTS
if boolean_expression then sequential_statement
end if;

if boolean_expression then sequential_statement

else sequential_statement
end if;

if boolean_expression then sequential_statement

elsif boolean_expression then sequential_statement
…
elsif boolean_expression then sequential_statement
else sequential_statement
end if;
case-when STATEMENT
case expression is
when choices => sequential_statements
…
when choices => sequential_statements
end case;
loop STATEMENT
loop
sequential_statement
…
sequential_statement
end loop;
for-loop STATEMENT
for identifier in range loop
sequential_statement
…
sequential_statement
end loop;
while STATEMENT
while boolean_expression loop
sequential_statement
…
sequential_statement
end loop;