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4 views4 pages

Pipeline Document

Uploaded by

botolminundragon
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Name : Rafael

Student Number : 32215130


Major : Global Software Convergence
Freedays left :0

Overview

The MIPS Pipeline Simulator models the execution of MIPS instructions using a 5-stage
pipeline:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execution (EX)
- Memory Access (MEM)
- Write Back (WB)
The program reads instructions from a binary file and processes them through these stages. It
handles hazards, controls signals, and simulates clock cycles.

Key Data Structures

1. Latches

- if_id_latch: Holds the instruction and program counter (PC) between the IF and ID
stages.
- id_ex_latch: Holds control signals and operands between the ID and EX stages.
- ex_mem_latch: Holds ALU results and control signals between the EX and MEM
stages.
- mem_wb_latch: Holds data to be written back to registers between the MEM and WB
stages.

Hazard Unit
hu: Manages forwarding and stalling signals to handle data hazards.

Instruction Information

- inst_info: Keeps track of the number of different types of instructions executed


(R-type, I-type, J-type, memory instructions, etc.).

Function Descriptions

- Initialization and Utility Functions


- initialize(): Initializes registers and memory.
- multiplexer2(int opnd1, int opnd2, int s): 2-to-1 multiplexer.
- multiplexer3(int opnd1, int opnd2, int opnd3, int s): 3-to-1 multiplexer.
- bit(int number, int numBit, int start): Extracts a specific bit range from a number.
- swap(int a): Swaps byte order (endianness conversion).
- SignExCheck(unsigned int imm, int opcode): Sign-extends an immediate value based
on the opcode.
- *check(int exp, const char msg)**: Checks for errors and handles program
termination.
- OutputDis(): Displays the final state and statistics of the simulation.
- update_clk_t(): Updates the clock cycle time.
- clockCy(): Advances the clock cycle.

Pipeline Stage Functions

- *load_instruction(FILE fd)**: Loads instructions from a file into memory.


- instruction_fetch(int PCBranchD, int PCSrcD)**: Fetches the next instruction from
memory.
- instruction_decode(int ALUOutM, int PCBranchD, int* PCSrcD)**: Decodes the
instruction and prepares operands.
- execution(int ALUOutM, int ResultW)**: Executes the instruction using the ALU.
- *memory_access(int ALUOutM)**: Accesses memory for load/store instructions.
- *write_back(int ResultW)**: Writes results back to the register file.

Hazard Detection and Control

- hazDetect(): Detects and handles hazards.


- stall(): Introduces stalls when hazards are detected.
- flush_E(): Flushes the EX stage when necessary.

ALU and Control Signals

- AluCalc(int opnd1, int opnd2, int E, int control): Performs ALU operations based on
control signals.
- setConSig(int op, int funct): Sets control signals based on the opcode and function
code.

Main Program Flow

The main function sets up the simulation environment and enters an infinite loop to simulate
the pipeline stages:
- File Handling: Opens the binary file containing MIPS instructions. If no file is
specified, it defaults to "input4.bin".
- Load Instructions: Loads instructions from the file into memory using
load_instruction.
- Initialize: Initializes registers and memory using initialize.
- Simulation Loop: Continuously processes instructions through the pipeline stages:
- Write Back: Calls write_back to write results to registers.
- Memory Access: Calls memory_access to handle memory operations.
- Execution: Calls execution to perform ALU operations.
- Instruction Decode: Calls instruction_decode to decode instructions.
- Instruction Fetch: Calls instruction_fetch to fetch the next instruction.
- Clock Cycle Update: Advances the clock cycle and updates timing information.
- Hazard Detection and Stalling: Handles hazards and potential stalls between stages.
- Program Termination: Ends when the program counter reaches the end of the
instruction memory or encounters an error.

Comparison Between Single Cycle and Pipelined

^Single Cycle^
vPipelinedv
Personal Feelings and Experience

Implementing pipelined MIPS is indeed very difficult as there are many objectives
that need to be completed, such as data dependency and branch problems. During the period
that this assignment was open, I had a very hard time completing the assignment. Even
though I can understand most of the stuff that is taught inside the classroom, Implementing it
is way harder than I thought. Therefore, I decided to use ChatGPT for help on some functions
and implementations that are very confusing and things that didn’t come to mind(labelled
inside the code). But since even ChatGPT is confusing at times, I also asked my seniors for
help in bigger parts(labelled in the code). Problems such as hazard detection and stalling
became very confusing as I was writing the code, and they helped me with the understanding
of what it is, and gave me example codes in which I can follow and implement to make my
own version. They also helped me to put loops inside of the code.
Even if the concept of pipelined MIPS is only partly different from a single cycle,
there are so many things that I have to keep in mind to make the program run smoothly. Last
time, before data dependency and branch predictions, my code did not run, and if it did, it
would have problems regarding the registers that are used and it is obvious that there were
many mistakes since these two things were not implemented yet. I started this project earlier
than when I started the single cycle project, and since there were no exams in the middle, I
had more time to do this project and more time to ask around about how I can implement it
and ask for help regarding the project. Therefore, this project feels more relaxed even though
it isn’t.

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