PMS307416A

π PM Tech
2048K Words x 16 Bits x 4 Banks (128-MBIT)

PMS307416A
Synchronous Dynamic RAM

Features Ordering Information
z Clock frequency: 166, 133 MHz Commercial Range: 0°C to 70°C
z Fully synchronous; all signals referenced to a
positive clock edge Frequency Speed Part No. Package
z Four banks operation 166MHz 6ns PMS307416ATR-6CN 400-Mil
z Single 3.3V power supply TSOP II
z LVTTL interface 133MHz 7.5ns PMS307416ATR-75CN Lead-free
z Programmable burst length
-- (1, 2, 4, 8, full page)
z Programmable burst sequence: Pin Assignment
Sequential/Interleave
z 4096 refresh cycles every 64 ms VDD 1 54 VSS
z Random column address every clock cycle DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
z Programmable /CAS latency (2, 3 clocks) DQ1 51 DQ14
4
z Burst read/write and burst read/single write DQ2 5 50 DQ13
operations capability VSSQ 6 49 VDDQ
z Burst termination by burst stop and precharge DQ3 7 48 DQ12
command DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
z Byte controlled by LDQM and UDQM DQ5 10 45 DQ10
z Packages 400-mil 54-pin TSOP-II DQ6 11 44 DQ9
43
z Lead-free package VSSQ 12 VDDQ
DQ7 13 42 DQ8
VDD 14 41 VSS
15 40
Overview LDQM NC
16 39
/WE UDQM
The PMS307416 is a high-speed CMOS 17 38
/CAS CLK
synchronous DRAM containing 134,217,728 bits. It is 18 37
/RAS CKE
organized as 4 Banks of 2048K Words x 16 Bits DRAM 19 36
/CS NC
with a synchronous interface (all signals are registered 20 35
BA0 A11
on the positive edge of the clock signal, CLK). Range of 21 34
BA1 33
A9
operating frequencies, programmable burst length and 22
A10/AP 23 32
A8
programmable latencies allow the same device to be A0 A7
24 31
useful for a variety of high bandwidth, high performance A1 A6
25 30
memory system applications. A2 A5
26 29
A3 27 28 A4
VDD VSS
Pin Descriptions
A0-A11 Address Input /CAS Column Address Strobe Command
A0-A11 Row Address Input /WE Write Enable
BA0, BA1 Bank Select Address LDQM Lower Byte, Input/Output Mask
A0-A8 Column Address Input UDQM Lower Byte, Input/Output Mask
DQ0-DQ15 Data DQ VDD Power
CLK System Clock Input VSS Ground
CKE Clock Enable VDDQ Power Supply for DQ Pin
/CS Chip Select VSSQ Ground for DQ Pin
/RAS Row Address Strobe Command NC No Connection
This document is a general product description and subject to change without notice.
π
PieceMakers Confidential and Proprietary
PM Tech PMS307416ATR
Pin Functions
Symbol Type Function
A0-A11 Input Address Inputs: A0-A11 are used as row address inputs during active
command input and A0-A8 as column address inputs during read or write
command input. A10 is also used to determine the precharge mode during other
commands. If A10 is LOW during precharge command, the bank selected by
A11 is precharged, but if A10 is HIGH, both banks will be precharged. When
A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
BA1, BA0 Input Bank Select: Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
CLK Input Clock: CLK is driven by the system clock. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
CKE Input Clock Enable: The CKE input determines whether the CLK input is enables
within the device. When CKE is HIGH, the next rising edge of the CLK signal will
be valid, and when LOW, invalid. When CKE is LOW< the device will be in either
the power-down mode, the clock suspend mode, or the self refresh mode. The
CKE is an asynchronous input.
/CS Input Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when /CS is sampled HIGH. /CS
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
/RAS Input Row Address Strobe: /RAS in conjunction with /CAS and /WE, forms the
device command. See the “Command Truth Table” item for details on device
commands.
/CAS Input Column Address Strobe: /CAS in conjunction with /RAS and /WE, forms the
device command. See the “Command Truth Table” item for details on device
commands.
/WE Input Write Enable: /WE in conjunction with /RAS and /CAS, forms the device
command. See the “Command Truth Table” item for details on device
commands.
LDQM, Input Data Input/Output Mask: LDQM and UDQM coatrol the lower the upper bytes
UDQM of the DQ buffers. In read mode, LDQM and UDQM coatrol the output buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enables, and
when HIGH, disables. The outputs go to the HIGH impedance state when
LDQM/UDQM is HIGH. In write mode, LDQM and UDQM coatrol the input
buffer. When LDQM or UDQM is LOW the corresponding buffer byte is enables,
and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
DQ0-DQ15 I/O Data I/O: DQ0-15 are data input/output pins. DQ through these pins can be
coatrolled in byte units using the LDQM and UDQM pins.
NC - No Connect: These pins should be left unconnected.
VDDQ Supply DQ Power: VDDQ is the output buffer power supply.
VDD Supply Power Supply: VDD is the device internal power supply.
VSS Supply Ground: VSS is the device internal ground.
VSSQ Supply DQ Ground: VSSQ is the output buffer ground
Rev 0.1 2 February 2010

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Block Diagram

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Absolute Maximum Rating
Symbol Parameters Rating Unit

VIN, VOUT Input, Output Voltage -0.3 ~ VDD+0.3 V
VDD, VDDQ Power Supply Voltage -1.0 ~ +4.6 V
TA Operating Temperature 0 ~ 70 °C
TSTG Storage Temperature - 55 ~ +125 °C
PD Power Dissipation 1 W
IOS Short Circuit Output Current 50 mA
Note: Permanent device damage may occur if Absolute Maximum Rating are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
Recommended DC Operating Conditions (TA = 0~70°C)
Symbol Parameter Min. Typ. Max. Unit Note

VDD, VDDQ Power Supply Voltage, 3.0 3.3 3.6 V
VIH Input High Voltage 2.0 3.0 VDD + 0.3 V 1
VIL Input Low Voltage -0.3 0 0.8 V 2
VOH Output High Voltage 2.4 – – V IOH = -2mA
VOL Output Low Voltage – – 0.4 V IOL = -2mA
IIL Input Leakage Voltage -5 – 5 μA 3
IOL Output Leakage Voltage -5 – 5 μA 4
Note:
1. VIH(max) = VDD + 2.3V AC for pulse width ≤ 3ns acceptable.
2. VIL(min) = VSS - 2.0V AC for pulse width ≤ 3ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD, all other pins are not under test = 0V.
4. VOUT is disabled, 0V ≤ VOUT ≤ VDD
Capacitance (VDD = 3.3V, VREF=1.4+/-200mV, f = 1MHz, Ta = 23°C)
Symbol Parameter Typ. Max. Unit

CIN1 Input Capacitance: CLK 2.5 3.5 pF
Input Capacitance: (CKE, /CS, /RAS, /CAS, /WE, LDQM,
CIN2 2.5 3.8 pF
UDQM)
CIN3 Input Capacitance: Address 2.5 3.8 pF
CI/O Input/Output Capacitance: DQ0-DQ15 4.0 6.0 pF
Note: These parameters are periodically sampled and are not 100% tested.

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DC Characteristics (VDD = 3.3V ± 0.3V, TA = 0~70°C)
Max.
Parameter/Test condition Symbol Unit
-6 -75
Operating Current
tRC ≥ tRC(min), Outputs Open IDD1 120 100
One bank active
Precharge Standby Current in power down mode
IDD2P 5
tCK = tck(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
IDD2PS 2
tCK = ∞, CKE ≤ VIL(max)
Precharge Standby Current in non-power down mode
tCK = tck(min), /CS ≥ VIH(min), CKE ≥ VIH IDD2N 35
Input signals are changed very 2CLKs
Precharge Standby Current in non-power down mode
IDD2NS 20
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
Active Standby Current in power down mode
IDD3P 35
tCK = tck(min), CKE ≤ VIL(max) mA
Active Standby Current in power down mode
IDD3PS 20
tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in non-power down mode
tCK = tck(min), CKE ≥ VIH(min), /CS ≥ VIH(min) IDD3N 60
Input signals are changed very 2clks
Active Standby Current in non-power down mode
IDD3NS 30
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Operating Current (Burst mode)
IDD4 140 125
tCK =tCK(min), Outputs Open, All banks active
Refresh Current
IDD5 150 135
tRC ≥ tRC(min)
Self Refresh Current
IDD6 5
CKE ≤ 0.2V
Note:
1. IDD1, IDD2N, IDD2P, IDD3N, IDD4, and IDD5 depend on the cycle rate and these values are measured by the
cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK.
2. IDD1 and IDD4 depend on the output loading. Specified values are obtained with the output open.

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AC Characteristics (VDD = 3.3V ± 0.3V, TA = 0~70°C)(1,2,3)
-6 -75
Parameter Symbol Unit Note
Min. Max. Min. Max.
CL* = 3 tCK3 6 –- 7.5 –-
Clock Cycle Time 1
CL* = 2 tCK2 10 –- 10 –-
Clock High Time tCH 2.5 –- 2.5 –- 3
Clock Low Time tCL 2.5 –- 2.5 –- 3
Access Time from CLK CL* = 3 tAC3 –- 5 –- 5.4

1,2
(positive edge) CL* = 2 tAC2 –- 6 –- 6
Data Output Hold Time tOH 2.5 –- 2.7 –- 2
Data Output Low Impedance tLZ 0 –- 0 –-
Data Output High Impedance tHZ 3 6 3 7 4
Data/Address/Control Input Setup Time tIS 1.5 –- 1.5 –- 3
Data/Address/Control Input Hold Time tIH 1 –- 1 –- ns 3
Command Period (ACT to ACT) tRC 60 –- 63 –-
Command Period (ACT to PRE) tRAS 42 100K 45 100K
Command period (PRE to ACT) tRP 18 –- 20 –-
Active Command to Read tRCD 18 –- 20 –-
Write Command Delay Time
Command Period (ACT[0] to ACT[1]) tRRD 12 –- 15 –-
Input Data to Precharge Command Delay Time tDPL 12 –- 15 –-
Write Recovery Time tWR 12 –- 15 –-
DQM Write Mask Latency tDQW 0 –- 0 –-
Transition Time tT 0.3 8 0.5 10
Auto Refresh Cycle Time tRFC 60 – 70 –
Last Data into Active Latency tDAL 5 –- 5 –-
CAS to CAS Delay Time tCCD 1 –- 1 –-
CLK
DQM Data Out Disable Latency tDQZ 2 –- 2 –-
Self Refresh Exit Time tSREX 1 –- 1 –-
Refresh Cycle Time (4096) tREF –- 64 –- 64 ms
* CL is CAS# Latency.
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. Referenced to the time at which the output achieves the open circuit condition, not to output voltage
levels.

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AC Operating Test Conditions (VDD = 3.3V ± 0.3V, TA = 0~70°C)
Parameter Value
Input Signal Levels (VIH/VIL) 2.4V / 0.4V
Reference Level of Output Signals 1.4V
Output Load Reference to the Under Output Load (B)
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V
1.4V
3.3V
1.2kΩ 50 Ω
Z0= 50 Ω
Output Output
50pF
30pF
30pF
50pF
870Ω
LVTTL D.C. Output Load (A) LVTTL A.C. Test Load (B)
Input Waveform

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Commands
Mode Register Set Command

(/CS, /RAS, /CAS, /WE = LOW)
The mode register stores the data for coatrolling the various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful
for variety of different applications. The default value of the mode register is not defined, therefore, the mode
register must be written after power up to operate the SDRAM. The mode register is written by asserting
LOW on /CS, /RAS, /CAS, and /WE (The SDRAM should be in active mode should be in active mode with
CKE already high prior to writing the mode register). The state of address pins A0-A11 and BA0–BA1 in the
same cycle as/CA, /RAS, /CAS, and /WE going LOW is the data written in the mode register. Two clock
cycles are required to complete the write in the mode register. The mode register contents can be changed
using the same command and clock cycle requirements during operation as long as all banks are in the idle
state. The mode register is divided into various fields into depending on functionality. The burst length field
use A0-A2, Burst type uses A3, /CAS latency (read latency from column address) use A4-A6, vendor
specific options or test mode use A7-A8, A10/AP-A11 and BA0–BA1. The write burst length is programmed
using A9. A7-A8, A10/AP-A11, and BA0–BA1 must be set to low for normal SDRAM operation. Refer to the
table for specific codes for various burst length, burst type and /CAS latency.
Active Command
(/CS, /RAS = LOW, /CAS, /WE = HIGH)
This SDRAM includes four banks of 4,096 rows each. This command address BA0–BA1 selects one of the
fours banks according and activates the row selected by the pins A0 to A11. This command corresponds to
the fall of the /RAS signal from HIGH to LOW in conventional DRAMs.
Precharge Command
(/CS, /RAS, /WE = LOW, /CAS = HIGH)
This command begins precharge operation of the bank selected by pins A10/AP and BA0–BA1. When A10
is HIGH, all banks are precharged at the same time. When A10 is LOW, the bank selected by BA0–BA1 is
precharged. After executing this command, the next command for the selected bank(s) is executed after
passage of the period tRP, which is the period required for bank precharging. This Command corresponds to
the /RAS signal from LOW to HIGH in conventional DRAMs.
Read Command
(/CS, /CAS = LOW, /RAS, /WE = HIGH)
This command selects the bank specified by the BA0–BA1 pins and begins a burst read operation at the
start address specified by pin A0 to A11. Data is output following /CAS latency. The selected bank must be
activated before executing this command. This Command corresponds to the /RAS signal from LOW to
HIGH in conventional DRAMs. When the A10/AP pin is HIGH, this command functions as a read with Auto
Precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When
A10 pin is LOW, the bank selected by the A12-A13 pins remains in the activated state after the burst read
completes.
Write Command
(/CS, /CAS, /WE = LOW, /RAS = HIGH)
When burst write mode has been selected with the mode register set command, this command selects the
bank specified by the BA0–BA1 pins pin and begins a burst write operation at the start address specified by
pins A0 to A11. This first data must be input to the DQ pins in the cycle with this command. The selected
bank must be activated before executing this command. When A10/AP pin is HIGH, this command functions
as a write with Auto Precharge command. After the burst write completes, the bank selected by pin BA0–
BA1 is precharged. When the A10/AP pin is LOW, the bank selected by the BA0–BA1 pins remains in the
activated state after the burst write completes.

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Auto Refresh Command
(/CS, /RAS, /CAS = LOW, /WE, CKE = HIGH)
This command executes the Auto Refresh operation. The row address and bank to be refreshed are
automatically generated during this operation. All banks must be placed in the idle state before executing
this command. The stipulated period (tRC) is required for a single refresh operation, and no other commands
can be executed during this period. The SDRAM goes to the idle state after the internal refresh operation
completes. This command must be executed at least 4096 times every 64ms. This command corresponds to
CBR Auto Refresh in conventional DRAMs.
Self Refresh Command

(/CS, /RAS, /CAS, CKE = LOW, /WE = HIGH)
This command executes the Self Refresh operation. The row address, the bank, and the refresh interval to
be refreshed are automatically generated internally during this operation. The Self Refresh operation is
started by dropping the CKE pin from HIGH to LOW. The Self Refresh operation continues as long as the
CKE pin remains LOW and there is no need for external coatrol of any other pins. The Self Refresh
operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed
until the SDRAM internal recovery period (tRC) has elapsed. After the Self Refresh, since it is impossible to
determine the address of the last row to be refreshed, an Auto Refresh should immediately be perfomed for
all addresses (4,096 cycles).
Burst Stop Command

(/CS, /WE = LOW, /RAS, /CAS = HIGH)
This command forcibly terminates burst read and write operations. When this command is executed during a
burst read operation, data output stops after the /CAS latency period has elapsed.
No Operation
(/CS = LOW, /RAS, /CAS, /WE = HIGH)
This command has no effect on the SDRAM.
Device Deselect Command

(/CS = HIGH)
This command does not select the SDRAM for an object of operation. In other words, it performs no
operation with respect to the SDRAM.
Power Down Command

(CKE = LOW)
When both banks are in the idle state, or when at least one of the banks is not in the idle state, this
command can be used to suppress device power dissipation by reducing device internal operations to the
absolute minimum. Power Down mode is started by dropping the CKE pin from HIGH to LOW. Power Down
mode continues as long as the CKE pin is held LOW. All pins other than CEK pins are invalid and none of
the other commands can be executed in this mode. The Power Down operation is terminated by raising the
CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tCKA) has
elapsed. Since this command differs from the Self Refresh command described above in that the refresh
operation is not performed automatically internally, the refresh operation must be performed within the
refresh period (tREF). Thus the maximum time that Power Down mode can be held is just under the refresh
cycle time.

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Clock Suspend
(CKE = LOW)
This command can be used to stop the SDRAM internal clock temporarily during a read or write cycle. Clock
Suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as
long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other
commands can be executed in this mode. Also note that the SDRAM internal state is maintained. Clock
Suspend mode is terminated by rising the CKE pin from LOW to HIGH, at which point SDRAM operation
restarts, the next command cannot be executed until the recovery period (tCKA) has elapsed. Since this
command differs from the Self Refresh command described above in that the refresh operation is not
performed automatically internally, the refresh operation must be performed within the refresh period (tREF).
Thus the maximum time that Clock Suspend mode can be held is just under the refresh cycle time.

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Command Truth Table(1,2)
Command Symbol CKEn-1 CKEn /CS /RAS /CAS /WE DQM BA0–BA1 A10 A0-A11 DQ
Mode Register Set(3,4) MRS H X L L L L X OP CODE X
Auto Refresh(5) REF H H L L L H X X X X High-Z
Self Refresh(5,6) SREF H L L L L H X X X X High-Z
Precharge Selected Bank PRE H X L L H L X V L X X
Precharge All Banks PALL H X L L H L X X H X X
Bank Activate(7) ACT H X L L H H X V Row address X
Write WRIT H X L H L L X V L X
Column
Write and Auto address
(18)
WRITA H X L H L L X V H X
Precharge(8)
Read(8) READ H X L H L H X V L Column X
(18)
address
Read and Auto precharge(8) READA H X L H L H X V H X
Burst Stop(9) BST H X L H H L X X X X X
No Operation NOP H X L H H H X X X X X
Device Deselect DESL H X H X X X X X X X X
Clock Suspend Mode SBY L X X X X X X X X X X
Data Write/Output Enable ENB H X X X X X L X X X Active
Data Mask/Output Disable MASK H X X X X X H X X X High-Z
DQM Truth Table(1,2)
Command Symbol CKEn-1 CKEn UDQM LDQM

Data Write/Output Enable ENB H X L L
Data Mask/Output Disable MASK H X H H
Upper Byte Data Write/Output Enable ENBU H X L X
Lower Byte Data Write/Output Enable ENBL H X X L
Upper Byte Data Mask/Output Disable MASKU H X H X
Lower Byte Data Mask/Output Disable MASKL H X X H

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CKE Truth Table(1,2)
Command Symbol Current State CKEn-1 CKEn /CS /RAS /CAS /WE BA0-BA1 A10 A0-A11
Start Clock Suspend
SPND Active H L X X X X X X X
Mode
Clock Suspend — Other States L L X X X X X X X
Terminate Clock Clock
— L H X X X X X X X
Suspend Mode Suspend
Auto Refresh REF Idle H H L L L H X X X
Start Self Refresh Mode SELF Idle H L L L L H X X X
Terminate Self Refresh L H L H H H X X X

SELFX Self Refresh
Mode L H H X X X X X X
H L L H H H X X X
Start Power Down Mode PDWN Idle
H L H X X X X X X
Terminate Power Down
— Power Down L H X X X X X X X
Mode

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Operation Command Table(1,2)
Current State Command Operation /CS /RAS /CAS /WE BA0-BA1 A10 A0-A11
(12)
DESL No Operation or Power Down H X X X X X X
(12)
NOP No Operation or Power Down L H H H X X X
BST Illegal L H H L X X X
(18)
READ/READA Illegal L H L H V V V
(18)
Idle WRIT/WRITA Illegal L H L L V V V
(18)
ACT Row Active L L H H V V V
PRE/PALL No Operation L L H L V V X
REF/SELF Auto Refresh or Self Refresh L L L H X X X
MRS Mode Register Set L L L L OP CODE
DESL No Operation H X X X X X X
NOP No Operation L H H H X X X
(17) (18)
READ/READA Read Start L H L H V V V
(17) (18)
Row Active WRIT/WRITA Write Start L H L L V V V
(10) (18)
ACT Illegal L L H H V V V
(15)
PRE/PALL Precharge L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Burst Read Continues, Row
DESL H X X X X X X
Active When Done
Burst Read Continues, Row
NOP L H H H X X X
Active When Done
Burst Interrupted, Row Active
BST L H H L X X X
After Interrupt
Burst Read Continues to /CAS (18)
READ/READA (16) L H L H V V V
latency, New Read
Read
Burst Interrupted, Write Start (18)
WRIT/WRITA (11,16) L H L L V V V
After Interrupt
(10) (18)
Burst Read Interrupted,
PRE/PALL L L H L V V X
Precharge After Interrupt

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Operation Command Table(1,2) (Cont.)
Burst Write Continues, Write
DESL H X X X X X X
Recovery When Done
NOP L H H H X X X
Recovery When Done
Burst Write Interrupted, Row Active
BST L H H L X X X
After Interrupt
Burst Write Interrupted, Read Restart (18)
READ/READA (16) L H L H V V V
After Interrupt
Write
Burst Write Interrupted, Write Restart (18)
WRIT/WRITA (11,16) L H L L V V V
After Interrupt
(10) (18)
Burst Write Interrupted, Precharge
PRE/PALL L L H L V V X
After Interrupt
Burst Read Continues, Precharge
DESL H X X X X X X
When Done
Burst Read Continues, Precharge
NOP L H H H X X X
When Done
Read With (10) (18)
Auto
(10) (18)
Precharge WRIT/WRITA Illegal L H L L V V V
(10) (18)
(10)
PRE/PALL Illegal L L H L V V X
DESL H X X X X X X
Recovery and Precharge When Done
NOP L H H H X X X
Recovery and Precharge When Done
Write With (10) (18)
Auto
(10) (18)
(10) (18)
(10)

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BA0-
Current State Command Operation /CS /RAS /CAS /WE A10 A0-A11
BA1
No Operation, Idle State After
DESL H X X X X X X
tRP Has Elapsed
No Operation, Idle State After
NOP L H H H X X X
tRP Has Elapsed
(10) (18)
Row READ/READA Illegal L H L H V V V
Precharge (10) (18)
WRIT/WRITA Illegal L H L L V V V
(10) (18)
No Operation, Row Active
DESL H X X X X X X
After tRCD Has Elapsed
NOP L H H H X X X
After tRCD Has Elapsed
Immediately (10) (18)
Following
(10) (18)
Row Active WRIT/WRITA Illegal L H L L V V V
(10,14) (18)
(10)
DESL H X X X X X X
After tDLP Has Elapsed
NOP L H H H X X X
BST L H H L X X X
Write (18)
READ/READA Read Start L H L H V V V
Recovery
(18)
WRIT/WRITA Write Start L H L L V V V
(10) (18)
(10)

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No Operation, Idle State
DESL H X X X X X X
After tDAL Has Elapsed
NOP L H H H X X X
BST L H H L X X X
Write After tDLP Has Elapsed
Recovery (10) (18)
With Auto
(10) (18)
(10) (18)
(10)
DESL H X X X X X X
After tRC Has Elapsed
NOP L H H H X X X
After tRC Has Elapsed
(18)
Refresh
(18)
(18)
DESL No Operation H X X X X X X
NOP No Operation L H H H X X X
Mode (18)
Register Set
(18)
(18)
ACT Band and Row Active L L H H V V V
REF/SELF Refresh L L L H X X X
MRS Most Register Set L L L L OP CODE

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Note for Command Rule Table, DQM Truth Table, CKE Truth Table, Operation Command Table:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input.
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the idle state in advance.
4. The states of the A0 to A11 pins are loaded into the mode register as an OP CODE.
5. The row address is generated automatically internally at this time. The DQ pin and the address pin data
are ignored.
6. During a self refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the idle state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the BA0, BA1 pins.
11. Time to switch internal busses is required.
12. The device can be switched to power down mode by dropping the CKE pin LOW when both banks in the
idle state. Input pins other than CKE are ignored at this time.
13. The device can be switched to self refresh mode by dropping the CKE pin LOW when both banks in the
idle state. Input pins other than CKE are ignored at this time.
14. Possible if tRRD is satisfied.
15. Illegal if tRAS is not satisfied.
16. The conditions for burst interruption must be observed. Also note that the device will enter the
precharged state immediately after the burst operation completes if auto precharge is selected.
17. Command input becomes possible after the period tRCD has elapsed. Also note that the device will enter
the precharge state immediately after the burst operation completes if auto precharge is selected.
18. A8, A9 = don’t care.
CKE Command Truth Table(1)
Current State Operation CKEn-1 CKEn /CS /RAS /CAS /WE BA0-BA1 A10 A0-A11
Undefined H X X X X X X X X
(2)
Self Refresh Recovery L H H X X X X X X
(2)
Self Refresh Recovery L H L H H X X X X
Self Refresh (2)
Illegal L H L H L X X X X
(2)
Illegal L H L L X X X X X
Self Refresh L L X X X X X X X
Idle State After tRC Has Elapsed H H H X X X X X X
Idle State After tRC Has Elapsed H H L H H X X X X
Illegal H H L H L X X X X
Self Refresh Illegal H H L L X X X X X

Recovery Illegal H L H X X X X X X
Illegal H L L H H X X X X
Illegal H L L H L X X X X
Illegal H L L L X X X X X

π
CKE Command Truth Table(1) (Cont.)
BA0-
Current State Operation CKEn-1 CKEn /CS /RAS /CAS /WE A10 A0-A11
BA1
Invalid, CLK(n-1) would exit
H X X X X X X X X
power down
Power Down Exit Power Down L H H X X X X X X

Exit Power Down L H L H H H X X X
Power Down Mode L L X X X X X X X
See Operation Command Table H H H X X X X X X
See Operation Command Table H H L H X X X X X
See Operation Command Table H H L L H X X X X
Auto Refresh H H L L L H X X X
See Operation Command Table H H L L L L OP CODE
Begin Power Down Next Cycle H L H X X X X X X
All Banks Idle
See Operation Command Table H L L H X X X X X
See Operation Command Table H L L L H X X X X
(3)
Self Refresh H L L L L H X X X
See Operation Command Table H L L L L L OP CODE
Exit Power Down Next Cycle L H X X X X X X X
(3)
Power Down Mode L L X X X X X X X
See Operation Command Table H X X X X X X X X
Row Active
Clock Suspend L X X X X X X X X
See Operation Command Table H H X X X X X X X
(4)
Clock Suspend On Next Cycle H L X X X X X X X
Other States Clock Suspend Termination On
L H X X X X X X X
Next Cycle
Maintain Clock Suspend L L X X X X X X X
Note:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input.
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from
LOW to HIGH. The minimum setup time (tCKA) required before all commands other than mode
termination must be satisfied.
3. All banks must be set to the idle state in advance to switch to power down mode or self refresh mode.
4. The input must be command defined in the Operation Command Table.

π
Bank Selection and Precharge Address Allocation
Bank active at read/write are coatrolled by BA0-BA1.
BA0 BA1 Active & Read/Write

0 0 Bank 0
1 0 Bank 1
0 1 Bank 2
1 1 Bank 3
Enable and disable Auto Precharge function are coatrolled by A10/AP and BA0-BA1 in read/write
command
A10/AP BA0 BA1 Operation

0 0 Disable Auto Precharge, leave Bank 0 active at end of burst
1 0 Disable Auto Precharge, leave Bank 1 active at end of burs
0
0 0 Enable Auto Precharge, precharge Bank 0 at end of burst
1
A10/AP and BA0-BA1 coatrol bank precharge when precharge is asserted
A10/AP BA0 BA1 Precharge

0 0 0 Bank 0
0 1 0 Bank 1
0 0 1 Bank 2
0 1 1 Bank 3
1 X X All Banks

π
Simplified State Diagram
Automatic transition after completion of command.

Transition resulting from command input.
Note: After the Auto Refresh operation, Precharge operation is performed automatically and
enter the IDLE state.

π
Function Descriptions
Power-up sequence
1. Apply VDD and VDDQ at the same time. Keep CKE low during power up.
2. Wait for stable power.
3. Start clock and drive CKE high.
Note : Voltage on any input pin must not exceed VDD+0.3V during power up.
Initialization Sequence
4. After stable power and stable clock, wait 200 μs.
5. Issue precharge all command (PALL).
6. After tRP delay, set 2 or more auto refresh commands (REF).
7. Set the mode register set command (MRS) to initialize the mode register.
Note : We recommend keeping DQM and CKE high during Initialization sequence to prevent data contention
on the DQ bus.
Power Up Sequence and Initialization Sequence
Mode Register Settings

The mode register set command sets the mode register. When this command is executed, pins A0 to A9,
A11, A10, and A12-A13 function as data input pins for setting the register, and this data becomes the device
internal OP CODE. This OP CODE has fields as listed in the table below.
Input Pin Field

A9 Write Mode
A6, A5, A4 /CAS Latency
A3 Burst Type
A2, A1, A0 Burst Length
Note that the mode register set command can be executed only when both banks are in the idle state. Wait
at least two cycles after executing a mode register set command before executing the next command.
/CAS Latency
During a read operation, between the execution of the read command and data output is stipulated as the
/CAS latency. This period can be set using the mode register set command. The optimal /CAS latency is
determined by the clock frequency and device speed grade. See the table of Operating Frequency / Latency

π
Relationships for details on the relation ship between the clock frequency and the /CAS latency. See the
table of the Mode Register for details.
Burst Length
When writing or ready, data can be input or output data continuously. In these operations, an address is
input only once and that address is taken as the starting address internally by the SDRAM. The SDRAM
then automatically generates the following address. The burst length field in the mode register stipulates the
number of data items input or output in sequence. In the SDRAM, a burst length of 1, 2, 4, 8, or full page can
be specified. See the table of the Mode Register for details.
Burst Type
The burst data order during a read or write operation is stipulated by the burst type, which can be set by the
mode register set command. The SDRAM supports sequential mode and interleaved mode burst type
settings. See the table of the Mode Register for details. Also see the table of Burst Length and Column
Address Sequence for details on DQ data orders in these modes.

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Mode Register Operation
Address BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function 0 0 0 0 WB 0 0 LT Mode BT BL
Sequentia
A2 A1 A0 Interleaved
l
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
Burst 0 1 1 8 8
Length 1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
A3 Type
Burst 0 Sequential
Type 1 Interleaved
A6 A5 A4 /CAS Latency
0 0 0 Reserved
0 0 1 Reserved
Latency
0 1 0 2
Mode
0 1 1 3
1 X X Reserved
A9 Write Mode
Write 0 Burst Read & Burst Write
Mode 1 Burst Read & Single Write
Note: Other values for these bits are reserved.

π
Burst Length And Column Address Sequence
Column Address Address Sequence
Burst Length
A2 A1 A0 Sequential Interleaved
X X 0 0-1 0-1
2
X X 1 1-0 1-0
X 0 0 0-1-2-3 0-1-2-3
X 0 1 1-2-3-0 1-0-3-2
4
X 1 0 2-3-0-1 2-3-0-1
X 1 1 3-0-1-2 3-2-1-0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
8
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn, Cn+1, Cn+2, Cn+3,
Full Page (256) n n n Cn+4,…… Cn-1(Cn+511), …. None
Cn(Cn+512)……
Note: The burst length in full page mode is 512.

π
Operation of the SDRAM
Read/Write Operations
Bank Active
Before executing a read or write operation, the corresponding bank and the row address must be activated
by the bank active (ACT) command. An interval of tRCD is required between the bank active command input
and the following read/write command input.
Burst Read
The Read cycle is started by executing the read command. The address provided during read command
execution is used as the starting address. First, the data corresponding to this address is output in
synchronization with the clock signal after /CAS latency period. Next, data corresponding to an address
generated automatically by the device is output in synchronization with the clock signal. The output buffers
go to the LOW impedance state /CAS latency minus one cycle after the read command, and go to the HIGH
impedance state automatically after the last data is output. However, the case where the burst length is a full
page is an exception. In this case output buffers must be set to the high impedance state by executing a
burst stop command. Note that upper byte and lower byte output data can be masked in dependently under
coatrol of the signals applied to the U/LQM pins. The delay period (tQMD) is fixed at two, regardless of the
/CAS latency setting, when this function is used. The selected bank must be set to the active state before
executing this command.
Burst Read Operation (Burst Length = 4, /CAS Latency = 2, 3)
Command READ tQMD
out 0 out 2 out 3
out 1 out 2 out 3
Burst Read masked by DQM Operation (Burst Length = 4, /CAS Latency = 2, 3)

π
Burst Write
The Write cycle is started by executing the command. The address provided during write command
execution is used as the starting address, at the same time, data for this address is input in synchronization
with the clock signal. Next, data is input in other in synchronization with the clock signal. During this
operation, data is written to address generated automatically by the device. This cycle terminates
automatically after a number of clock cycles determined by the stipulated burst length. However, the case
where the burst length is a full page is an exception. In this case the write cycle must be terminated by
executing a burst stop command. The latency for DQ pin data input is zero, regardless of the /CAS latency
setting. However, a wait period (write recovery: tDPL) after the last data input is required for the device to
complete the write operation. Note that the upper byte and lower byte input data ca be masked
independently under coatrol of the signal applied to the U/LQM pins. The delay period (tDMD) is fixed at zero,
regardless of the /CAS latency setting, when this function is used. The selected bank must be set to the
active state before executing this command.
Burst Write Operation (Burst Length = 1, 2, 4, 8, /CAS Latency = 2, 3)
Single Write
The single write operation is enabled by setting OP CODE (A11, A10, A9, A8, A7) to (0, 0, 1, 0, 0). In a
single write operation, data is only written to the column address and the bank select address specified by
the write command set cycle without regard to the burst length. (The latency of data input is 0 clock).

π
Auto Precharge Operations
Read With Auto-Precharge
The Read With Auto Precharge command first executes a burst read operation and then puts the selected
bank in the precharge state automatically. After the precharge completes, the bank goes to the idle state.
Thus this command performs a read command and a precharge command in a single operation. During this
operation, the delay period (tPQL) between the last burst data output and the start of the precharge operation
differs depending on the /CAS latency setting. When the /CAS latency setting is two, the precharge
operation starts on one clock cycle before the last burst data is output (tPQL = -1). When the /CAS latency
setting is three, the precharge operation starts on two clock cycles before the last burst data is output (tPQL =
-2). Therefore, the selected bank can be made active after a delay of tRP from the start position of this
precharge operation. The selected bank must be set to the active state before executing this command. The
Auto Precharge function is invalid if the burst length is set to full page.
/CAS Latency 3 2
tPQL -2 -1
tPQL
tRAS
tRP
tPQL
tRP
tRAS
Read With Auto Precharge Operation (Burst Length = 4, /CAS Latency = 2, 3)
Write With Auto-Precharge
The Write With Auto Precharge command first executes a burst write operation and then puts the selected
bank in the precharge state automatically. After the precharge completes, the bank goes to the idle state.
Thus this command performs a write command and a precharge command in a single operation. During this
operation, the delay period (tDAL) between the last burst data output and the completion of the precharge
operation differs depending on the /CAS latency setting. The delay (tDAL) is tRP plus one CLK period. That is,
the precharge operation starts one clock period after the last burst data input. Therefore, the selected bank
can be made active after a delay of tDAL. The selected bank must be set to the active state before executing
this command. The Auto Precharge function is invalid if the burst length is set to full page.
/CAS Latency 3 2
tDAL 1CLK + tRP 1CLK + tRP

π
tRAS
tDAL
Write With Auto Precharge Operation (Burst Length = 4, /CAS Latency = 3)
tRAS
tDAL
Write With Auto Precharge Operation (Single Write, /CAS Latency = 3)
Burst Stop Operations
Burst Stop At Read
The SDRAM can output data continuously from the burst start address (a) to location a + 255 during a read
th
cycle in which the burst length is set to full page. The SDRAM repeats the operation starting at the 256
cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A precharge command must be executed within the
ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tRBD) required
for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go
to the HIGH impedance state. This period tRBD is two clock cycles when the /CAS latency is two and three
clock cycle when the /CAS latency is three.
/CAS Latency 3 2
tRBD 3 2

π
tRBD
tRBD
Burst Stop At Read Operation (Burst Length = Full, /CAS Latency = 2, 3)
Burst Stop At Write
The SDRAM can input data continuously from the burst start address (a) to location a + 255 during a write
th
cycle in which the burst length is set to full page. The SDRAM repeats the operation starting at the 256
cycle with the data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A precharge command must be executed within the
ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tWBD)
required for burst data input to stop following the execution of the burst stop command has elapsed, the write
cycle terminates. This period tWBD is zero clock cycle, regardless of the /CAS latency.
Burst Stop At Write Operation (Burst Length = Full, /CAS Latency = 2, 3)
Command Intervals
Read To Read Interval
A new command can be executed while a read cycle is in progress, i.e. before that cycle completes. When
the second read command is executed, after the /CAS latency has elapsed, data corresponding to the new
read command is output in place of the data due to the previous read command. The interval between two
read commands (tCCD) must be at least one clock cycle. The selected bank must be set to the active state
before executing this command.

π
tCCD
Read To Read Command Interval, Same ROW address in same bank

(Burst Length = 4, /CAS Latency = 3)
tCCD
Read To Read Command Interval, different bank (Burst Length = 4, /CAS Latency = 3)
Write To Write Interval
A new command can be executed while a write cycle is in progress, i.e. before that cycle completes. When
the second read command is executed, data corresponding to the new write command can be input in place
of the data due for the previous write command. The interval between two write commands (tCCD) must be at
least one clock cycle. The selected bank must be set to the active state before executing this command.
tCCD
Write To Write Command Interval, Same ROW address in same bank

(Burst Length = 4, /CAS Latency = 2, 3)

π
tCCD
Write To Write Command Interval, different bank (Burst Length = 4, /CAS Latency = 2, 3)
Read To Write Interval
A read command can be interrupted and a new write command executed while the read cycle is in progress,
i.e. before that cycle completes. Data corresponding to the new write command can be input at the point new
write command is executed. To prevent collision between input and output data at the DQn pins during this
operation, the output data must be masked using the U/LDQM pins. The interval (tCCD) between these
commands must be at least on clock cycle. The selected bank must be set to the active state before
executing this command.
tCCD
Read To Write Command Interval (Burst Length = 4, /CAS Latency = 2)
Write To Read Interval
A new command can be executed while the read a write cycle is in progress, i.e. before that cycle completes.
Data corresponding to the new read command is output after the /CAS latency has elapsed from the point
the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least
one cycle before data is output during this operation. The interval (tCCD) between these commands must be
at least on clock cycle. The selected bank must be set to the active state before executing this command.

π
tCCD
Write To Read Command Interval (Burst Length = 4, /CAS Latency = 2)
Read To Precharge Interval
A read cycle can be interrupted by the execution of the precharge command before that cycle completes.
The delay time (tRQL) from the execution of the precharge command to the completion of the burst output is
the clock cycle /CAS latency.
/CAS Latency 3 2
tRQL 3 2
tRQL
Read To Precharge Command Interval (Burst Length = 4, /CAS Latency = 2)
tRQL
Read To Precharge Command Interval (Burst Length = 4, /CAS Latency = 3)
Write To Precharge Interval

π
A write cycle can be interrupted by the execution of the precharge command before that cycle completes.
The delay time (tWDL) from the precharge command to the point where burst input is invalid, i.e. the point
where input data is no longer written to device internal memory is zero clock cycle regardless of the /CAS
latency. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This
precharge command and burst write command must be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual bank operation. Inversely, to write all the burst data to the
device, the precharge command must be executed after the write data recovery period (tDPL) has elapsed.
Therefore, the precharge command must be executed on one clock cycle that follows the input of the last
burst data item.
/CAS Latency 3 2
tWDL 0 0
tDPL 2 2
Command WRIT
tWDL=0
in A0 in A1 in A2 in A3
Write To Precharge Command Interval masked by DQM (Burst Length = 4, /CAS Latency = 2)
tDPL
Write To Precharge Command Interval (Burst Length = 4, /CAS Latency = 3)
Bank Active Command Interval
The interval between the two bank active commands must be no less than tRC. In the case of different bank
active commands, the interval between the two bank active commands must be no less than tRRD.

π
Bank Active to Bank Active for the same bank
Bank Active to Bank Active for the different bank
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the SDRAM enters clock
suspend mode on the next CLK rising edge. This command reduced the device power dissipated by
stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In
this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the
device internal states are maintained. When the CKE pin goes from LOW to HIGH clock suspend mode is
terminated on the next CLK rising edge and device operation resumes. The next command cannot be
executed until the recovery period (tCKA) has elapsed. Since this command differs from Self Refresh
command described previously in that the refresh operation is no performed automatically internally, the
refresh operation must be performed within in the refresh period (tREF). Thus the maximum time that clock
suspend mode can be held is just under the refresh cycle time.

π
Clock Suspend (Burst Length = 4, /CAS Latency = 2)

π
Timing Waveforms
Power Up Sequence
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
DQ
/WE
DQM

π
Read & Write Cycle at Same Bank @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
CL=2
tRAC tDPL
tAC tHZ
DQ
CL=3
tRAC
tAC tDPL
tHZ
/WE
DQM
Note:
1. Minimum row cycle time is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency -1] number of valid output data is
available after row precharge. Last valid output will be HIGH Z (tHZ) after the clock.
3. Access time from row active command tRAC = tRCD + /CAS latency -1) + tAC.
4. Output will be HIGH Z after the end of burst (1, 2, 4, 8, & Full Page burst).

π
Page Read & Write Cycle at Same Bank @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
tDPL
CL=2
DQ
CL=3
/WE
DQM
Note:
1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tDPL before row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after row precharge cycle will be masked internally.
4. tDAL, last data in to active delay, is 2CLK + tRP.

π
Page Read Cycle at Different Bank @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
CL=2
DQ
CL=3
/WE
DQM
Note:
1. /CS can be Don’t Care when /RAS, /CAS, and /WE are HIGH at the clock going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

π
Page Write Cycle at Different Bank @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
DQ
tDPL
/WE
DQM
Note:
1. To interrupt a burst write by row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt a burst write by row precharge, both the write and the precharge banks must be the same.

π
Read & Write Cycle at Different Bank @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
CL=2
DQ
CL=3
/WE
DQM
Note:
1. tCDL should be met to complete write.

π
Read & Write Cycle with Auto Precharge @ Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
DQ CL=2
CL=3
/WE
DQM
Note:
1. tCDL should be coatrolled to meet minimum tRAS before internal precharge start. (In the case of burst
length = 1 & 2)

π
Clock Suspend & DQM Operation Cycle @ /CAS Latency = 2, Burst Length = 4
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
DQ
tHZ tHZ
/WE
DQM
Note:
1. DQM is needed to prevent bus contention.

π
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Full Page Burst
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
CL=2
DQ
CL=3
/WE
DQM
Note:
1. At full page mode, burst is finished by burst stop or precharge.
2. About the valid DQs after burst stop, it is same as the case of /RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2, on them.
But at burst write, burst stop and /RAS interrupt should be compared carefully.
Refer to the timing diagram of “Full Page Write Burst Stop Cycle”.
3. Burst stop is valid at every burst length.

π
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full Page Burst
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
tDPL
DQ
/WE
DQM
Note:
1. At full page mode, burst is finished by burst stop or precharge.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It
is defined by AC parameter of tDPL. DQM at write interrupted by precharge command is needed to
prevent invalid write. DQM should mask invalid data on precharge command cycle when asserting
precharge before end of burst. Input data after row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.

π
Burst Read Single Bit Write Cycle @ Burst Length = 2
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA1
BA0
A10/AP
CL=2
DQ
CL=3
/WE
DQM
Note:
1. BRSW modes is enabled by setting A9 HIGH at MRS (Mode Register Set). At the BRSE Mode, the burst
length at write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with Auto Precharge is executed, keep it in mind that tRAS should not be
violated. Auto Precharge is executed at the burst end cycle, so in the case of BRSW write commend, the
next cycle starts the precharge.

π
Active/Precharge Power Down Mode @ /CAS Latency = 2, Burst Length = 4
CLK
tIS tIS
CKE tIS
/CS
/RAS
/CAS
ADDR
BA
A10/AP
tHZ
DQ
/WE
DQM
Note:
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tIS prior to row active command.
3. Can not violate minimum refresh specification (64ms).

π
Self Refresh Eatry and Exit Cycle
CLK
CKE
/CS
/RAS
/CAS
ADDR
BA
A10/AP
DQ
/WE
DQM
Note: To Enter Self Refresh Mode

1. /CA, /RAS, /CAS with CKE should be LOW at the same clock cycle.
2. After 1 clock cycle, all of the inputs including the system clock can be “Don’t Care” except for
CKE.
3. The SDRAM remains in Self Refresh mode as long as CKE stays LOW. Once the device
enters Self Refresh mode, minimum tRAS is required before exit from Self Refresh.
Note: To Exit Self Refresh Mode
4. System clock restart and be stable before returning CKE HIGH.
5. /CAS starts from HIGH.
6. Minimum tRC is required after CKE going HIGH to complete Self Refresh exit.
7. 4K cycles of burst auto refresh is required before Self Refresh eatry and after Self Refresh exit
if the system uses burst refresh

π
Mode Register Set Cycle Auto Refresh Cycle
CLK
CKE
/CS
/RAS
/CAS
ADDR
DQ
/WE
DQM
Note:
1. All banks precharge should be completed before Mode Register Set cycle and Auto Refresh cycle.
2. Mode Register Set cycle
(a) /CAS, /RAS, /CAS, & /WE activation at the same clock cycle with address key will set internal
mode register.
(b) Minimum 2 clock cycles should be met before new /RAS activation.
(c) Please refer to Mode Register table.

π
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π PM Tech

2048K Words x 16 Bits x 4 Banks (128-MBIT)

Synchronous Dynamic RAM

Rev 0.1 2 February 2010

Rev 0.1 3 February 2010

Symbol Parameters Rating Unit

Recommended DC Operating Conditions (TA = 0~70°C)

Symbol Parameter Min. Typ. Max. Unit Note

Capacitance (VDD = 3.3V, VREF=1.4+/-200mV, f = 1MHz, Ta = 23°C)

Symbol Parameter Typ. Max. Unit

Rev 0.1 4 February 2010

Rev 0.1 5 February 2010

Access Time from CLK CL* = 3 tAC3 –- 5 –- 5.4

Rev 0.1 6 February 2010

Rev 0.1 7 February 2010

Mode Register Set Command

Rev 0.1 8 February 2010

Self Refresh Command

Burst Stop Command

Device Deselect Command

Power Down Command

Rev 0.1 9 February 2010

Rev 0.1 10 February 2010

DQM Truth Table(1,2)

Command Symbol CKEn-1 CKEn UDQM LDQM

Rev 0.1 11 February 2010

Terminate Self Refresh L H L H H H X X X

Rev 0.1 12 February 2010

Rev 0.1 13 February 2010

Rev 0.1 14 February 2010

Rev 0.1 15 February 2010

Rev 0.1 16 February 2010

CKE Command Truth Table(1)

Self Refresh Illegal H H L L X X X X X

Rev 0.1 17 February 2010

Power Down Exit Power Down L H H X X X X X X

Maintain Clock Suspend L L X X X X X X X

Rev 0.1 18 February 2010

BA0 BA1 Active & Read/Write

A10/AP BA0 BA1 Operation

A10/AP and BA0-BA1 coatrol bank precharge when precharge is asserted

A10/AP BA0 BA1 Precharge

Rev 0.1 19 February 2010

Automatic transition after completion of command.

Rev 0.1 20 February 2010

Power Up Sequence and Initialization Sequence

Mode Register Settings

Input Pin Field

Rev 0.1 21 February 2010

Rev 0.1 22 February 2010

Address BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Note: Other values for these bits are reserved.

Rev 0.1 23 February 2010

Note: The burst length in full page mode is 512.

Rev 0.1 24 February 2010

Burst Read Operation (Burst Length = 4, /CAS Latency = 2, 3)

Command READ tQMD

out 0 out 2 out 3

out 1 out 2 out 3

Burst Read masked by DQM Operation (Burst Length = 4, /CAS Latency = 2, 3)