Module 2: Flip Flops 21EEE135

Module 2, Part 2: Flip Flops

I. Introduction
A sequential network is defined as a two valued network in which the outputs at any instant
are dependent on both present inputs and on past outputs. Hence for sequential circuits it is
necessary to have a memory element. The difference between combinational circuit and
sequential circuit is shown below in the table:
Combinational circuits Sequential Circuits
(1) E.g. Adder, Subtractor, MUX, DEMUX,
(1) E.g. Flip flops, Registers, Counters
Encoder, Decoder, Comparator
(2) In Sequential circuits, the output variables
(2) In combinational circuits, the output dependent not only on the present input variables
variables are at all times dependent on the but they also depend upon the past history of these
combination of input variables input variables. The past history is provided by
feedback from the output back to the input.
(3) Memory unit is required to store the past history
(3) Memory unit is not required
of input variables in the sequential circuits.
(4) Combinational circuits are faster in speed
(4) Sequential circuits are slower than
because the only delay is between input &
Combinational circuits
output due to propagation delay of gates
(5) Easy to design (5) harder to design

There are two types of sequential circuits. A synchronous sequential network is one in which
its behavior is determined by the values of the signals at only discrete instances of time,
provided by clock signal. An asynchronous sequential network the behavior of the network
is immediately affected by the input signal changes. The difference between synchronous and
asynchronous sequential circuit is shown in table below:

Synchronous sequential circuits Asynchronous Sequential circuits

1. Memory elements are flip flops, which are
1. Memory elements are clocked flip-flops
independent of clock signals
2. Input signals & clock signals are synchronized 2. Input signals can affect the memory
to change output states elements at any instant of time
3. Easier to design 3. More difficult to design

Flip flop are simple sequential circuits. It is the building block for sequential circuits. A flip-
flop has two stable conditions, either a ‘1’ or ‘0’.

2. Latches
 Latches are one class of flip-flops. In a latch the output changes are not controlled.
 The output responds immediately to changes on the input lines. It uses a special control
signal called Enable, The differences between latches and flip-flops are given below:

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Module 2: Flip Flops 21EEE135
Flip-Flips Latches
1. Flip-flops are basically synchronous
1. Latches don’t use clocking signals
circuits that use clocking signals.
2. It is a sequential device that normally 2. It is a sequential device that checks all
samples its inputs & changes its output of its inputs continuously and changes its
only at times determined by clocking output at any time independent of a
signal. clocking signal.
3. Enable signal is provided and with
3. No enable signal
enable signal it is called GATED Latch.
4. When enable signal is active, output
changes occur as input changes. But when
-----
enable signal is not activated input changes
do not affect output

3. SR Latch
 Figure Fig 3.2a shows the circuit of SR latch using and logic diagram of SR(Set-
Reset) Latch. The logic diagram is shown in fig 3.2b

Fig 3.2a: SR latch using NOR Fig 3.2b: Logic Diagram

 The working of SR latch is explained below

I. When Q=0,

The truth table for SR-latch is shown below:

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Module 2: Flip Flops 21EEE135
S R Qn+1 or Q+ Qn+1 or Q+ State

0 0 Qn Qn No Change (NC)
0 1 0 0 Reset
1 0 1 1 Set
X
X
[Qn=0 and 𝑄̅ 𝑛 = 0 Invalid/ Forbidden/
1 1 [Qn=0 and 𝑄̅ 𝑛 = 0 which is
which is against Boolean Indeterminate
against Boolean algebra]
algebra]

4. S R latch (S’ R’ latch)

 Figure Fig a shows the circuit of SR latch using NAND. The logic diagram is shown
in fig C

OR

Fig a: Circuit diagram of S’R’ Latch Fig b

Fig C: Symbol of S’R’ Latch

The functional table of S’R’ latch is shown in the table below

S R Qn+1 or Q+ Qn+1 or Q+ State

X
X
[Qn=1 and 𝑄̅ 𝑛 = 1 Invalid/ Forbidden/
0 0 [Qn=1 and 𝑄̅ 𝑛 = 1 which is
which is against Boolean Indeterminate
against Boolean algebra]
algebra]
0 1 1 1 Set
1 0 0 0 Reset
1 1 Qn Qn No Change (NC)

To have consistency in using NAND for SR latch the circuit diagram of fig B is used which
connects the S and R input with an inversion to maintain the same truth table as SR
implementation using NOR gate.

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Module 2: Flip Flops 21EEE135
5. Gated SR-latch
The output of SR / S’R’ latch changes as and when input changes. To avoid such
occurrence ENABLE ( E ) input or control signal ( C ). The circuit with control signal or
enable signal is called GATED SR latch. The circuit diagram and symbol of GATED SR
LATCH is shown in Fig. 3.6

1
3

Fig 3.6: Circuit and

symbol of Gated
2 4 SR latch

Working: When enable signal (E or C) = 0, then one of the input to NAND gate (1) and
(2) is 0. Therefore the output of NAND gate (1) and (2) will be ‘1’, irrespective of the
value of S and R. Then based on value of Q and Q’ the output of Gate 1 and Gate 2 will
remain in the same state without change. i.e.

When enable, E or C = 0, the circuit remains in no-change condition

When enable, E or C = 1, the circuit behaves like a normal SR latch

The functional table of GATED SR LATCH is given below:

E S R Qn+1 State

0 X X Qn NC

1 0 0 Qn NC

1 0 1 0 Reset

1 1 0 1 Set

1 1 1 X Invalid
a. Gated D-latch:
D-latch or Data-latch is used as a binary data storage. The two conditions of SR wherein
the output has a well-defined state is used.
i.e. S=0, R=1 then Q=0
S=1, R=0 then Q=1
i.e. it can be seen that when S & R are complimentary Q follows S.
Therefore the modifications to convert Gated SR latch as Gated D-latch is shown below
in fig 3.7a and the symbol of gated D-latch is shown in fig 3.7b

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Module 2: Flip Flops 21EEE135
Fig 3.7a: Circuit of Gated
D latch

Fig 3.7b: Symbol of

Gated D latch

From the above circuit it can be seen that when circuit is enabled, Q follows value of D
and hence the name D-latch or Data – Latch. The functional table is shown below.

E D Qn+1 State
0 X Qn NC
1 0 0 Reset
1 1 1 Set

b. Preset and Clear inputs for latches and flip flops:

The two signals Preset (Pr) and Clear (Clr) are used to set initial values of latch or flip
flop.
When Pr = 0, the output of latch / flip flop (Q) will be = ‘1’.
When Clr = 0, the output of latch / flip flop (Q) will be = ‘0’.
These two signals are also referred as asynchronous input as the output can be set or
reset irrespective of the input values. These are applicable to any latch or flip flop. The
symbol of D flip flop with asynchronous inputs is shown below:

6. Flip flop and need for flip flop

 State of latch / flip flop is changed by a change in control input (EN or CLK). The
momentary change is called Trigger and the transition it causes is said to trigger
flip flop.
 A latch is triggered every time the pulse is HIGH. As long as PULSE iinput = ‘1’,
any change in data input will cause change in the state of latch.
 We know that in case of sequential circuit, there is a feedback path from output of
flip flop to input of combinational circuit. Consequently, when latches are used for
storage element, the state transition of the latches start as soon as CLK pulse is ‘1’.

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Module 2: Flip Flops 21EEE135
 The new state of latch appears at output while PULSE is still active. The feedback
causes input to change and as CLK pulse is ‘1’, the latch responds to new values
and gets triggered, causing a change in its output.
 This results in unpredictable output as latch may keep changing as long as CLK
pulse stays ‘1’.
 Flip flop is a circuit which is constructed such that, it is triggered only during a
signal transition from 0 1 or 1 0. The former is called Positive edge or Rising
edge. The latter is called Negative edge or Falling edge.
 A latch can be modified as flip flop by two methods:
a) Employ 2 latches in a configuration that isolates output of flip flop and prevents
it from being affected while input of flip flop is changing. This is called Master
Slave Configuration.
b) Produce a flip flop that triggers only during Positive or Negative edge of CLK
signal and is disabled during the rest of CLK period. This is called Edge
triggered flip flop.

7. JK Flip Flop
JK flip flop removes the invalid condition of SR flip flop / latch. It works similar to SR
for the conditions of S=0, R=0 ; S=0, R=1; S=1, R=0. It introduces a new state called
TOOGLE state.

8. T Flip-flop: It is a special case of JK flip flop. It uses the Toggle state of JK flip flop. It
has one input called as T or Toggle. The flip flop is designed to provide toggle state and
hence is called T-flip flop or Toggle flip-flop.
It can be observed that to realize TOGGLE condition the value of J and K has to be ‘1’.
Hence figure 3.18 shows the implementation of T-Flip-flop using JK-Flip flop. The
functional truth table and symbol of T-flip flop is shown in figure below.

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Module 2: Flip Flops 21EEE135

9. Characteristics Equation of flip flops / Latches

It is basically an equation which defines the logical expression for next state output in case of
flip-flops based on the inputs on information lines (D, JK, SR, T) and the present state output.

a) SR Latch / Flip Flop: Consider a SR flip flop shown below in figure below

Fig a SR Flip-flop using NAND gates Fig b Logic diagram of SR Flip-flop

The circuit is similar to SR latch except enable signal is replaced by clock pulse (CP). On the
positive edge of the clock pulse, the circuit responds to the S & R inputs. The expanded functional
truth table for SR latch / Flip-flop is shown below:

CP S R Qn Qn+1 Status
 0 0 0 0 NC
 0 0 1 1 NC
 0 1 0 0 Reset
 0 1 1 0 Reset
 1 0 0 1 Set
 1 0 1 1 Set
 1 1 0 X Invalid
 1 1 1 X Invalid

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Module 2: Flip Flops 21EEE135
K-Map for Qn+1

R Qn R Qn R Qn R Qn

S 1
0 0
0
S 1
1 X x
[

Therefore the characteristics equation for SR is Qn+1 = S + R Qn

b) JK Flip-Flop : Consider a JK flip flop shown in figure below,

Fig a Clocked JK Flip-flop Fig b Logic diagram of clocked JK Flip-flop

The expanded functional truth table for JK latch / Flip-flop is shown below:

CP J K Qn Qn+1 Status
 0 0 0 0 NC
 0 0 1 1 NC
 0 1 0 0 Reset
 0 1 1 0 Reset
 1 0 0 1 Set
 1 0 1 1 Set
 1 1 0 1 Toggle
 1 1 1 0 Toggle
K-map for Qn+1

K Qn K Qn K Qn K Qn
1
J 0 0 0

J 1 1
1 0

̅̅̅̅ + 𝑲
Characteristic equation of a JK Flip-flop is 𝑸𝒏 + 𝟏 = 𝑱𝑸𝒏 ̅ 𝑸𝒏

c) D Flip-flop: Consider a D flip flop and its representation as shown in fig below

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Module 2: Flip Flops 21EEE135

Fig a. D Flip-flop using NAND gates Fig.b. Logic Diagram

D Flip-flop is obtained by connecting an inverter between two inputs of SR flip-flop. The expanded
functional table of D flip flop is shown below:

CP Qn D Qn+1 Status
 0 0 0 Reset
 0 1 1 Qn+1=D
 1 0 0 Reset
 1 1 1 Qn+1=D
K-map for Qn+1 of D Flip-flop

Characteristic equation of D Flip-flop is Qn+1=D

d) T Flip-flop: Consider T flip flop and symbol as shown in figure below:

Fig : Circuit and symbol of T flip flop

T Flip-flop is also known as toggle Flip-flop. The T Flip-flop is a modification of the JK flip-flop.
It is obtained from a JK Flip-flop by shorting both the inputs, J & K together. The expanded
functional truth table is shown below

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Module 2: Flip Flops 21EEE135
CP Qn T Qn+1 Status
 0 0 0 NC
 0 1 1 Toggle
 1 0 1 NC
 1 1 0 Toggle
K-Map for Qn+1

̅̅̅̅ + 𝑻
Characteristic equation of T Flip-flop 𝑸𝒏 + 𝟏 = 𝑻𝑸𝒏 ̅ 𝑸𝒏= TQn

10. Excitation table of Flip-flops and Conversion of Flip-flops

10.1 . Excitation table defines the input to be applied to flip flops to realize transition from a current
state of a flip flop (0 or 1) to a new state (0 or 1). The possible changes of states and the
corresponding inputs for different flip flops is given in the table below:

Current state Next State

D input T input J K
Qn or Q Qn+1 or Q+
0 0 0 0 0 X
0 1 1 1 1 X
1 0 0 1 X 1
1 1 1 0 X 0
10.2.Conversion of flip-flops

Steps to be followed:

1. Identify the required flip flop and the available flip flop as per the problem statement.
2. Write the functional truth table for the required flip flop with clear mention of inputs,
current state (Qn), next state (Qn+1).
3. Consider each row in the functional table written in previous step and identify Qn to Qn+1
requirement.
4. Based on excitation table of available flip flop, identify the input of available flip flops for
the change from Qn to Qn+1.
5. Solve for the excitation value identified with inputs and Qn as input variables and build the
circuit.

a) Convert D flip flop to JK flip flop

Required flip flop - JK, Available flip flop – D

Write the functional truth table of required flip flop JK and for the change in Qn to Qn+1
identify the D input required based on excitation table of D-flip flop

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Module 2: Flip Flops 21EEE135
State J K Qn Qn+1 D input
0 0 0 0 0
NC
0 0 1 1 1
0 1 0 0 0
Reset
0 1 1 0 0
1 0 0 1 1
Set
1 0 1 1 1
1 1 0 1 1
Toggle
1 1 1 0 0
Solve using k-map to find expression for D input with J,K and Qn as input variables

K Qn K Qn K Qn K Qn

J 1
0 0 0
J 1 1
1 0

Therefore we get, D = J Qn + K Qn

Thus the circuit to convert D flip flop to JK is shown in figure below

The functional truth table of JK edge triggered flip flop and its symbol is shown in
Fig a and Fig b

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Module 2: Flip Flops 21EEE135
b) Convert JK flip flop to D flip flop

Required flip flop - D, Available flip flop –JK

Write the functional truth table of required flip flop D and for the change in Qn to Qn+1
identify the JK input required based on excitation table of JK-flip flop

State D Qn Qn+1 J K
0 0 0 0 X
Reset
0 1 0 X 1
1 0 1 1 X
Set
1 1 1 X 0
Solve using k-map to find expression for J and K input with D and Qn as input variables

J Qn Qn
K
Qn Qn

D 0
X D X 1
D 1 X D X 0

Therefore we get, J = D and K= D

Thus the circuit of a positive edge triggered D flip flop is shown in figure below

c) Convert JK flip flop to T flip flop

Required flip flop - T, Available flip flop –JK

Write the functional truth table of required flip flop T and for the change in Qn to Qn+1
identify the JK input required based on excitation table of JK-flip flop

State T Qn Qn+1 J K
0 0 0 0 X
NC
0 1 1 X 0
1 0 1 1 X
Toggle
1 1 0 X 1
Solve using k-map to find expression for J and K input with D and Qn as input variables

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Module 2: Flip Flops 21EEE135

J Qn Qn Qn Qn
K
T 0
X T X 0
T 1 X T X 1

Therefore we get, J = T and K= T

Thus the circuit of a positive edge triggered T flip flop is shown in figure below

d) Convert D flip flop to T flip flop

Required flip flop - T, Available flip flop –D

Write the functional truth table of required flip flop T and for the change in Qn to Qn+1
identify the JK input required based on excitation table of D-flip flop

State T Qn Qn+1 D
0 0 0 0
NC
0 1 1 1
1 0 1 1
Toggle
1 1 0 0

Solve using k-map to find expression for J and K input with D and Qn as input variables

D Qn Qn
1 Therefore from the table we can see that the
T 0
expression for D = T’ Qn + T Qn’ = T Qn
T 1 0

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Module 2: Flip Flops 21EEE135
Thus the circuit of a positive edge triggered T flip flop using D flip flop is shown in figure below

_________________________END of Module 2, Part 2________________

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