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Digital Object Identifier 10.1109/XXXX.2022.1234567

A Small-Area 2nd-order Adder-Less

Continuous-Time ∆Σ Modulator with
Pulse Shaping FIR DAC for Magnetic
Sensing
Manish Srivastava1 , Member, IEEE, Alessandro Ferro1 ,Member, IEEE,
Aleksandr Sidun1 , J.M. de la Rosa2 , Fellow, IEEE, Kilian O’Donoghue1 ,
Padraig Cantillon-Murphy1 , Senior Member, IEEE, Daniel O’Hare1 , Member, IEEE
1
MCCI, Tyndall National Institute (University College Cork), Lee Maltings Complex Dyke Parade, Cork, T12 R5CP, Ireland
2
Instituto de Microelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), 41092 Seville, Spain
Corresponding author: Manish Srivastava (email: [email protected]).
This work was supported in part by the European Union ERC-2020-COG Award 101002225; and in part by the Microelectronic Circuits
Centre Ireland (MCCI) through Enterprise Ireland under Grant TC 2020 0029.

ABSTRACT This work presents a small-area 2nd-order continuous-time ∆Σ Modulator (CT∆ΣM) with a
single low dropout regulator (LDO) serving as both the power supply for the CT∆ΣM and reference voltage
buffer. The CT∆ΣM is used for digitising very low amplitude signals in applications such as magnetic
tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture
implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a
novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop
delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This
enables a single low-dropout (LDO) voltage regulator to generate both power supply and Vref for the
DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and
91-dB DR within a signal bandwidth of 20 kHz and the CT∆ΣM consumes 300 µW of power when
clocked at 10.24 MHz. The CT∆ΣM achieves a state-of-the-art area of 0.07 mm2 .

INDEX TERMS Analog-to-Digital Conversion, continuous-time delta-sigma modulation, excess loop-delay

compensation, FIR DAC, magnetic sensor, sensor interface.

I. INTRODUCTION with the sensor. The overall ambition of this project is

M AGNETIC tracking for image-guided interventions

requires sensors with sub-1-mm dimensions to navi-
gate small anatomical features such as the patient’s airways,
to design an on-chip ADC interface co-located with the
magnetic sensor for use in tracking applications where the
sensor is typically at the tip of a tiny instrument, tool, or
vasculature, neurological or nasal tracts [1], [2]. An analog- catheter.
to-digital converter (ADC) is essential in sensor interface Continuous-time delta-sigma modulators (CT∆ΣM) are
circuits to digitise the analog signals from sensors. For becoming increasingly popular in sensor systems due to their
the intended application, a small-area low-power ADC is low power, low area, and relaxed requirements on their input
required. In addition to the ADC, the peripheral blocks and reference buffers compared to other solutions such as
required by the ADC (reference voltage buffer, power supply SAR ADC or Discrete-Time ∆ΣM.
regulators, references, and clock generators) can consume The employment of a single-bit CT∆ΣM is an attractive
substantial area and power. An ADC topology that enables architecture due to the inherent simplification of the digital-
the whole system to be implemented with low power and to-analog converter (DAC) by eliminating the need for cal-
area is essential to realise a solution that can be co-located ibration or dynamic element matching (DEM) requirements

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 This article has been accepted for publication in IEEE Open Journal of Circuits and Systems. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653

Manish Srivastava et al.:

[3]. Unfortunately, the large DAC least significant bit (LSB) Magnetic sensor with AFE
makes single-bit CT∆ΣM extremely sensitive to clock jitter
and places additional demands on the linearity of the front- Data
end integrator. A finite-impulse response (FIR) feedback Rcoil
Lcoil AFE 1-bit 2nd order
DAC can be used to reduce these problems by averaging Clock
CTΔΣM
or low-pass filtering the jitter of the clock signal which also
reduces the feedback signal’s step size, improving modulator
linearity [4]. The delay introduced by the FIR DAC and other
modulator blocks changes the loop-filter transfer function
FIGURE 1. A Block diagram of an on-chip magnetic tracking system with
and noise transfer function (NTF), making the system po- CT∆ΣM.
tentially unstable. Excess loop delay compensation (ELDC)
is required to compensate for this delay [4]. TABLE 1. The proposed CT∆ΣM specification

A cascade of integrators in feed-forward (CIFF) topology Parameter Specification

is popular for low power CT∆ΣM [5]. The feedforward Technology (NM) 65
paths reduce the output voltage swings at the integrators, Supply (V) 1.2
allowing for the use of low-power single-stage operational Signal Bandwidth (kHz) 20
transconductance amplifiers (OTA) while also improving Sampling Frequency (MHz) 10.24
OTA linearity and reducing slew. This usually requires an OSR 256
adder circuit before the comparator to sum the feedfor-
SNDR (dB) ≥ 75
ward signals or paths and the ELDC path. The additional
adder circuit also requires more area and power, making
it less appealing for use in applications requiring reduced the noise of the input sensor and analog-front-end (AFE).
area, such as this work. Previously published works have To achieve the expected system accuracy for this work (±
proposed alternative loop-filter implementations to address 1 mm), the signal-to-noise-and-distortion ratio (SNDR) of
this limitation. The CT∆ΣM proposed in [5] used a second the CT∆ΣM also needs to be in the range of 75-80 dB and
integrator as an adder while using DEM logic. While these dynamic range in the range of 80-90 dB. The specification
techniques are appropriate for multi-bit quantisers, they are for the proposed CT∆ΣM is defined in Table 1.
not applicable to single-bit CT∆ΣMs. The passive adders Fig. 2 shows a block diagram of the conventional CIFF
were proposed in [6] and [7] which were implemented as 2nd-order CT∆ΣM, inclusive of low-dropout-voltage (LDO)
capacitive and resistive adders, respectively. However, this regulators and a reference voltage buffer. The analog LDO
technique suffers from both reduction of signal swing at the supplies power to the integrators, while the digital LDO
input of the comparator and being susceptible to parasitics caters to the quantiser and digital-to-analog converter (DAC).
and mismatch [8]. The reference voltage buffer serves the purpose of providing
This paper proposes a 2nd-order CT∆ΣM architecture that a reference voltage for the DAC. The inclusion of these
eliminates the need for a dedicated adder circuit and also peripheral blocks contributes to an increase in the overall
proposes a new scheme of continuous-time pulse shaping area of the system.
DAC (CT-PS DAC) for ELDC that reduces distortion at As shown in Fig. 2, the feedback path through g im-
the summing node and relaxes the design of the reference plements the complex noise transfer function (NTF) zeros,
voltage buffer. The proposed DAC allows a single low- reducing the quantisation noise within the signal bandwidth
dropout-voltage (LDO) voltage regulator to generate both [9]. As explained in [9], distributing the zeros of the noise
the power supply and Vref for the modulator, thus reducing transfer function (N T F ) throughout the signal band instead
the overall area of the system. These strategies allow high of concentrating them solely at DC, leads to an enhancement
performance (see Table 4) while achieving the lowest area in the signal-to-quantisation-noise ratio (SQNR) within the
published to the author’s knowledge. bandwidth. An optimisation process was used to minimise
The paper is organised as follows: An overview of the in-band noise by determining the most effective frequency
system design is explained in section II. The circuit imple- for these zeros. The optimal positions for the zeros are 14
mentation is described in section III. Section IV discusses kHz [9].
measured results with a comparison with the state-of-the-art The loop filter L(s) transfer functions of the ideal
and finally, conclusions are drawn in Section V. CT∆ΣM shown in Fig. 2, can be defined as follows:
k2 fs2 + k1 fs s
L(s) = (1)
II. Proposed Modulator Architecture gfs2 + s2
As shown in Fig. 1, this modulator will be used in magnetic where k1 and k2 are the feed-forward coefficients and fs is
sensing for position tracking in image-guided or robotic the sampling frequency. The feedback path and gain g allow
intervention applications, the area of the system is very to place the zeros of NTF in an optimum position in the
crucial. The performance of the whole system is limited by signal bandwidth.

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 This article has been accepted for publication in IEEE Open Journal of Circuits and Systems. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653
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Analog
proposed adder-less CTΔΣM
LDO k1
VDDA
u(t) y(t) y[n]
+
∫ ∫ k2 + ADC v[n]
v(t) g
VDDD fs

DAC
VREF Vref Digital
Buffer LDO

FIGURE 2. A Block diagram of the conventional CT∆ΣM with peripheral

blocks.

k1
u(t) y(t) y[n] FIGURE 4. Performance of the modulator (SNR) with increasing clock
∫ ∫ k2 ADC v[n] jitter.

v(t)−
−
+ +

g
fs
ELD Comp.

DAC
FIR-DAC waveform (represented by v(t) in Fig. 3) are reduced by a
FC(Z) factor of M. Since noise due to clock jitter is proportional
DAC F(z) td to the height of the transitions in the DAC output, it follows
M-taps Time delay that the in-band mean square noise due to jitter is reduced
by 20log10 (M ) dB [4], [15], as illustrated for a 4-tap FIR
filter by the dashed plot in Fig. 4. To achieve our desired
FIGURE 3. A Block diagram of the conventional 2nd-order CT∆ΣM with SNDR of 80 dB, the use of a 4-tap (with equal weights)
FIR DAC and ELD compensation.
FIR DAC proves beneficial, enhancing the SNDR by 12 dB.
Increasing the number of taps would yield minimal benefits,
The dotted plot in Fig. 4 is the signal-to-noise ratio (SNR) while introducing additional complexity. These extra taps
versus clock jitter generated from an ideal Simulink model of in both the FIR and ELDC DACs make it challenging to
the CT∆ΣM in Fig. 2. As depicted in Fig. 4, the CT∆ΣM compensate for the added delay, consequently adding system
exhibits strong susceptibility to clock jitter, resulting in a complexity and area requirements.
degradation of the modulator’s in-band SNR [10], [11]. The
impact of the most severe clock jitter scenario (40 ps) for this
work results in a reduction of the SNDR to 67 dB, as shown A. FIR DAC Compensation
in Fig. 4. To mitigate this issue, switched-capacitor resistor The loop-filter transfer function L(s) changes due to the
(SCR) feedback may be implemented [12]. A disadvantage delays introduced by the FIR DAC and other modulator sub-
of this method is that it causes an increase in the peak-to- blocks, making the modulator unstable and changing the
average ratio of the feedback waveform [10], [13]. NTF [10]. The NTF of the loop filter can be restored by
FIR feedback is an alternative strategy to counteract the modifying the loop-filter coefficients and by adding a direct
CT∆ΣM’s susceptibility to clock jitter, as discussed in [10] path FIR filter around the quantiser.
and [14]. Employing FIR feedback in conjunction with a To restore the loop filter response to the response of the
one-bit modulator effectively reduces the clock jitter sensi- original topology in Fig. 2, open-loop pulse response analysis
tivity and substantially reduces the requirement of the 1st has been carried out as shown in Fig. 5. It should be noted
OTA to respond to large step input signals, thus easing the that the open-loop pulse response does not show the NTF
linearity prerequisites of the loop filter. This benefit is akin as the NTF is a closed-loop response. Rather, y(t) (solid
to the advantages of using a multi-bit quantiser [10]. line) is the open-loop pulse response of the ideal loop filter
Fig. 3 shows a CT∆ΣM with an FIR DAC added to reduce without any delay, while the dotted line shows the response
the susceptibility to clock jitter. The delays added to the loop with FIR DAC added. To restore the response for t/Ts ≥ M ,
by the FIR DAC require an additional fast compensation the coefficients (k1 and k2 ) were modified to k̂1 and k̂2 [16].
DAC. The output sequence of the CT∆ΣM is denoted as M is the number of FIR DAC taps. To restore the response
v[n] in Fig. 3, filtered through an M-tap low-pass FIR non- for t/Ts < M, a M-taps ELD compensation with transfer
return-to-zero (NRZ) DAC with a transfer function F (z). function Fc (Z) was employed. To restore the loop transfer
Due to this, the magnitudes of the steps in the feedback DAC function shown in Fig. 3, the feedforward coefficients k1 and

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TABLE 2. The coefficients of the proposed CT∆ΣM

k1
Coefficient Value
δ(t) DAC + ∫ ∫ k2 + y(t) kˆ1 3.53
g kˆ2 1.67
g 5.44E-04
(a)

FIR-DAC k1 The steps required to correct the open-loop filter step

δ(t) td y2(t) response are illustrated in Fig. 6. The start of the correction
F(z) DAC +
∫ ∫ k2 +

g is the dotted line, and we want to restore the response to the

M-taps ideal response of the solid line. Correcting the coefficients
(b) using (2) and (3) yields the dot-dash line. The value of
taps for excess loop delay (ELD) compensation with transfer
FIR-DAC k1 function Fc (z) can be computed by the difference of pulse
response with and without the FIR DAC (|y(t) − ŷ2 (t)|) as
δ(t) td F(z) DAC + ∫ ∫ k2 +
y3(t)
g shown in Fig. 6. In Fig. 6 the ideal response is shown by
M-taps a solid line, the delayed response as a dotted line, and the
ELD Comp. coefficients for ELDC are shown in a vertical dashed line
FC(z) DAC and were obtained from |y(t) − ŷ2 (t)| the error. The dashed
line shows the restored transfer function.
M-taps
(c) B. Proposed Adder-Less Feedforward Architecture
FIGURE 5. Open-loop pulse response simulation of the loop filter (a) in Modeling
ideal conditions (b) with FIR DAC present (c) with FIR DAC and ELD The proposed modulator design is depicted symbolically in
compensation.
Fig. 7. Without changing the overall loop transfer function,
the modulator structure of Fig. 3 can be adjusted to create the
proposed configuration illustrated in Fig. 7. The final adder
is moved in front of the second integrator. The feedforward
and ELD compensation paths are differentiated by capacitors
before being summed together at the input of the integrator.
The modified loop filter transfer function L(s) is defined
as:
kˆ2 fs2 + kˆ1 fs s
L(s) = (4)
gfs2 + s2
where kˆ1 and kˆ2 are the optimised feed-forward coefficients
as explained in section-II A, fs is the sampling frequency,
the feedback path gain g allows to place the zeros of NTF
in an optimum position, as discussed in section II.
The coefficients of the ELDC FIR DAC need to be re-
calculated for the proposed topology using the methodology
FIGURE 6. Open-loop pulse response of the ideal loop filter (solid), loop
filter with equally weighted 4-taps FIR DAC (dotted), loop filter with FIR
described in Fig. 5 and the coefficients of the modulator
DAC and optimised cofficient (dot-dashed), and ELDC DAC with Fc (z) can be found in Table 2. The circuit implementation of
transfer function (vertical dashed lines). the proposed architecture will be presented in Section III,
focusing on the circuit implementation of the loop filter, FIR
k2 were optimised [4] and can be calculated as : DAC, and ELDC of the proposed adder-less CT∆ΣM.
    
k̂ = k + k td l + k 1 (1 − l) III. Circuit Implementation
1 1 2 2
Ts g (2) Fig. 8 displays the simplified single-ended schematic of the
k̂2 = k2

proposed second-order 1-bit CT∆ΣM. The second integrator
where l is defined in (3) and serves the dual purpose of being both an integrator and
an adder circuit which uses less area in comparison to the
eg − 1 previously published work [5], [17]–[23]. The integrators in
l=M (3)
egM − 1 the CT∆ΣM were realised by using folded cascode OTAs,
where Ts = 1/fs stands for the sampling period. while the feedback FIR DAC is realised as an equal-weighted

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by the gain of the 1st integrator. So, the IRN density of the
LDO with Vref
modulator can be calculated as:
VREF BUFF s
k1 8kT γ
d dt k2 v(n,in) = + 4kT (Rin + RDAC ) (6)
u(t) y(t) y[n] gm
∫ ∫ k2 ADC v[n]
− −
+ +

v(t) g where k is Boltzman’s constant, T is the temperature in

fs
d dt kelvin, gm is the transconductance of OTA used in the

ELD Comp.
Vref integrator, Rin is the input resistor of the integrator, and
DAC RDAC is DAC’s resistor.
FIR-DAC FC(z) So, by using equation 6 and values from Fig. 8, the IRN
DAC F(z) td density of the CT∆ΣM can be computed and was found to
M-taps Time delay be ∼= 33 √nVHz
.

C. Adder Circuit Implementation

FIGURE 7. A Block diagram of the proposed 2nd-order Adder-Less
CT∆ΣM. Fig. 12 (a) shows the implementation of the 2nd integrator
combining the integration (solid line), proportional gain (dot-
TABLE 3. OTA specification used for the integrator ted line), and ELDC DAC (dashed line) paths. The integrator
Parameter Specification has a low-pass characteristic, whereas the proportional path
DC Gain (dB) ≥ 60 (dotted line) and DAC path (dashed line) are AC coupled and
UGB (MHz) ≥ 30 have band-pass characteristics, as depicted in Fig. 12 (b). The
PM (Degree) ≥50 absence of the proportional signal at low frequencies doesn’t
Slew Rate (V/µS) 16
cause errors in the modulator response because its magnitude
Supply (V) 1.2
is small in comparison to the large integrated signal (solid
line).
In the proportional gain path, the coefficient kˆ1 is imple-
four-taps resistive DAC. The specification for the OTA can mented as a proportional gain Ckˆ1 /Ckˆ2 . The ELDC has been
be found in Table 3. realised by a continuous-time capacitor DAC (CDAC). The
implementation of the ELDC can be explained as follows;
A. Implementation of Zeros The modulator output Dout [n] is applied to the n DAC
As stated in section II, the NTF was designed to create a capacitor values (CDn ) where n represents the number of
quantisation noise null at 14 kHz. This required a feedback FIR DAC taps used in ELDC. The capacitors act as differ-
resistor Rf b to implement the g term. The Rf b was cal- entiators to produce currents which are then added together
culated to be 77 MΩ. As shown in Fig. 9, the Rf b was and integrated by Ckˆ2 . The differentiation and integration
implemented as a duty-cycled resistor to save area. Duty- operations effectively cancel each other out and the resulting
cycled resistors are preferable to pseudo-resistors as they signals at the comparator input are the DAC signals gained
have much less variation [24]. The switching frequency (fd ) by CDn /Ckˆ2 .
for the Rf b is a division of fs , to avoid aliasing out-of-band
(OOB) shaped quantisation noise [24]. D. Proposed Continuous-Time Pulse Shaping DAC
The loop filter transfer function for Fig. 8 can be written As shown in Fig. 13 (a), the reference voltage, Vref is
as: applied to the ELDC’s capacitor (CDn ) which acts as a
dV
Rf b (Ckˆ1 R1 s + 1) differentiator, generating a current Ivref ( = CDn dtref ) that
L(s) = (5) is then integrated by Ck2 ˆ . Due to the reference buffer’s
Rin (Cin Ckˆ2 R1 Rf b s2 − Ckˆ1 R1 s + 1)
limited current sourcing capabilities, errors are introduced in
This equation has a s term in the denominator, unlike the current pulse Ivref causing distortion. The finite current
(4). This term reduces the quality factor of the loop filter. sourcing of the second integrator OTA causes slewing and
However, plotting the frequency response of (5) against the large voltages at node Vg which can disturb the gain and
ideal transfer function, as shown in Fig. 10, shows only a integration modes.
minor degradation (the difference in location of the zero from Possible solutions to address this issue are: (a) reducing
(4) to (5), was less than 100 Hz). the output impedance of the reference buffer which will
attenuate glitches at the cost of increased power consumption
B. Noise Analysis of the CT∆ΣM or (b) using a large decoupling capacitor (>100 pF) at the
A block diagram of the CT∆ΣM is shown in Fig. 11 (a). Vref buffer can provide the switching currents required by
The input-referred-noise (IRN) density of the modulator will the CDAC during transitions. Many state-of-the-art ADCs
be dominated by the 1st integrator and DAC. The noise from use off-chip decoupling capacitors to maintain a clean refer-
the 2nd integrator, as shown in Fig. 11 (b), will be shaped ence voltage [4], [5], [19]. As this modulator will be used in

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Manish Srivastava et al.:

Duty-cycled resistor(Rfb)

Cin Ck1 Ck2

Rin
R1
Vin Dout
vo1
vo2
R-DAC

CT-PS
FIR DAC

ELDC
-1 -1 -1
D Z Z Z DAC fs
4 4
F(z) CD1 CD2 CD3 CD4 Fc(z)
Z-0.5
Rin = 30 kΩ R1 = 390 kΩ Cin = 17.5 pF Ck2 = 200 fF
CD1 = 145 fF CD2 = 130.5 fF CD3 = 101.5 fF CD4 = 58 fF

FIGURE 8. Simplified single-ended implementation of the proposed CT∆ΣM.

195 ns Cin
128 Rin Quantizer
10.24 MHz 80 kHz
fs fd 12.5 μs Vin H(s) Dout
T = 195 ns
R-DAC

R = 1.2 MΩ on Rest of loop-filter

Duty cycle (D)=0.0152
fd Rfb = R/D= 78 MΩ

(a)
FIGURE 9. Implementation of the duty-cycled resistor. Cin
Ck2
Rin
Vin R1
vo1 vo2
RDAC
Dout (b)

FIGURE 11. (a) A Block diagram of the CT∆ΣM with active RC integrator
(b) Main Noise Contributor (active RC integrators and DAC) of the
CT∆ΣM.

proposed. A pulse-shaping resistor (Rps ) is added to CDAC

before the node Vg , as shown in Fig. 13(b), which limits the
peak Ivref :
Vref − t
Ivref = [e (Rsw +Rps )CDn ] (7)
Rsw + Rps
FIGURE 10. Comparing the frequency responses of the ideal loop filter as
given by equation (4) and the schematic loop filter as given by (5).
where Rsw is the switch resistance, Rps is pulse shaping re-
sistor, and CDn is the ELDC path capacitor where n=1,2,3,4.

applications (in-vivo magnetic tracking) where the area and Fig. 14(a) shows the current flowing from CDn to Ckˆ2 ,
additional pin for an external capacitor are undesirable, a the solid line waveform represents peak current at the Vg
continuous-time pulse shaping DAC (CT-PS DAC) circuit is node without the pulse shaping resistor Rps , while the dotted

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(a)

(a)

(b) (b)

FIGURE 12. (a) Adder circuit implementation. (b) Magnitude response of FIGURE 14. (a) Ivref with and without Rps (b) Charge Qps (area under
the integration, proportional gain, and ELDC signal paths. current pulse) with increasing pulse shaping resistor (Rps ).

Ck2 integrator OTA, thus reducing distortion. The shaped pulse

(dotted line ) introduces no error provided the area of its
Switch CDn Vg pulse integrated in the sampling time Ts is equal to that
Vref of the integrated pulse without resistor Rps (the solid line).
Rsw Ivref vo2 To meet this requirement, the maximum value of Rps was
Ref. Buf. chosen to maintain the same charge Qps (i.e. matching the
(a) Ck2 area of the current (Ivref ) pulse integrated in time Ts ). The
trade-off of area (charge Qps ) versus resistance is shown
Switch CDn Vg in Fig. 14 (b). As depicted in Fig. 14 (b), the area of the
Vref integrated pulse will decrease as the resistance exceeds 40
Rsw Rps vo2 kΩ, leading to the aforementioned error.
Ref. Buf. Ivref It is important to differentiate this work from the previ-
(b) ously published work by Ortmanns et al., [12], In their work
a switched capacitor resistor (SCR) DAC was introduced,
generating a decaying pulse waveform that exhibited insen-
FIGURE 13. (a) Conventional design (b) The proposed pulse-shaped DAC
with resistor Rps . sitivity to jitter. In this work, a continuous-time capacitive
DAC (CT-CDAC) approach is introduced. Ortmanns’ con-
tribution entailed generating a current pulse proportional to
line waveform represents the shaped pulse. The magnitude the DAC signal, which was then subjected to integration.
of the peak sourced current has been reduced from 417 µA In this work, the current pulse is the differential of the
to 21.7 µA, a reduction by a factor of 20. The reduction applied voltage step. This differentiated pulse then undergoes
in Ivref peak also reduces the slew requirement of the 2nd integration, effectively nullifying the differentiation process

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BMVR
Vbmvr
(408μ/400n)
CCC 1-bit 2nd Order
Vref CTDSM

CL
R3= 10kΩ, CCC = 3.6pF, CL = 15pF R3
(a)
Vbias
(24μ/4.5μ) (24μ/4.5μ)
(48μ/4.5μ)
R1 Vbias FIGURE 16. The die photograph shows the overall IC designed for the
Vbias

65-nm process node.

Vbmvr
(20μ/7.5μ)
(10μ/400n)
(40μ/7.5μ)
(1μ/5.5μ) LDO with
R2 ref. voltage buffer Logic analyzer
(4μ/2μ) Vbmvr Power supply
CTΔΣM Data
R1= 250kΩ, R2= 11kΩ
(b) Clock
Signal generator
On-chip blocks
FIGURE 15. (a) LDO/VREF-buffer circuit (b) Beta multiplier voltage
reference circuit (BMVR)
Matlab processing
Clock generator unit
and resulting in an output signal that is a gained/scaled
version of the DAC voltage.
FIGURE 17. The CT∆ΣM test setup includes an external clock generator
A low-power and low-area dynamic comparator architec- and logic analyser.
ture was used for this work. The design of the comparator
was referenced from [25].
IV. Measured Results
E. Voltage Regulator/Buffer Circuit Implementation The proposed CT∆ΣM is fabricated in a 65-nm CMOS
Fig. 15 presents the schematic of the low-dropout- process. As shown in Fig. 16, the CT∆ΣM occupies an
voltage/reference-voltage-buffer (LDO/VREF-buffer) config- active area of 0.07 mm2 and the LDO/VREF-buffer with
uration, providing the supply voltage VDD and reference decoupling cap occupies an area of 0.02 mm2 . Fig. 17
voltage (Vref ) for the CT∆ΣM. This configuration em- shows the measurement setup. A signal generator (Keysight
ploys a beta multiplier voltage reference (BMVR) design 33500b) is used to apply a fully differential input sine wave.
to generate a 1.2 V reference for the LDO. To reduce The single-bit digital output data was read out using a Dig-
potential switching noise perturbations on the CT∆ΣM’s ilent Digital Discovery portable logic analyser and further
power supply, a capacitor (CL ) of 15 pF is used at the output off-chip post-processing was carried out using MATLAB. A
of the regulator. This mitigates transient disturbances and 6.17-kHz sine wave input signal with an amplitude of −2.4
noise artifacts and minimises any SNDR reduction of the dBFS (full scale of 1.2 V) is applied to the input of CT∆ΣM
CT∆ΣM due to power supply disturbance. The LDO/VREF- while the sampling clock frequency is set to 10.24 MHz. The
buffer with CL occupies an active area of 0.02 mm2 and output spectrum of the modulator, acquired by an average of
consumes 47 µA from a 1.5 V power supply. eight 130K point FFTs using a Hanning window, is shown in
The CT-PS DAC proposed in this study led to a notewor- Fig. 18. The modulator achieves 81.5 dB SNDR, with HD3
thy decrease in the switching current drawn from the input and HD5 of -98.98 dB and -98.0 dB, respectively. Fig. 19
buffer in the CT∆ΣM. This not only improves the DAC’s shows the SNDR for a 6.17 kHz tone versus the input signal
performance but also enables the use of a single LDO for amplitude level in 20 kHz bandwidth. Sweeping the input
both the CT∆ΣM power supply and the Vref supply for the signal from -100 dBFS to 0 dBFS demonstrates a dynamic
DAC. This approach simplifies the system design, reduces range of 91 dB. It is worth noting that in this application,
the overall area significantly, and lowers the overall power the dynamic range is more important than SNDR, as the
consumption, especially important for applications requiring induced voltage in the magnetic sensor ranges from a few
very small readout circuits. hundred nV to an expected max of 100 µV. Fig. 20 compares

8 VOLUME ,

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 This article has been accepted for publication in IEEE Open Journal of Circuits and Systems. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653
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FIGURE 20. Peak SNDR with increasing input signal frequency with
amplitude -2.4 dBFS.

FIGURE 18. Power Spectrum Density of CT∆ΣM.

LDO/VREF-Buffer
23%
1st Integrator
29%

Digital Circuit
3% Total Power 380 µW

ELDC+ Ref.
8%
FIR DAC
6%
Comparator 2nd Integrator
2% 29%

FIGURE 19. SNDR over increasing input signal amplitude at 6.17-kHz.

FIGURE 21. Power breakdown for various CT∆ΣM blocks including the
LDO/VREF-buffer.
the measured SNDR in the signal band for four different
chips for a range of input signal frequencies; the lowest peak
SNDR across four chips occurred at 81.5 dB when evaluated insensitivity of the CT∆ΣM performance to clock jitter,
against the input frequency. The improvements in SNDR highlighting instead the prominence of thermal noise as the
with frequency are due to the 2nd and 3rd harmonics going dominant noise source of the CT∆ΣM.
outside the signal bandwidth. These measured results show As mentioned previously, the CT∆ΣM will be used in
only minor part-to-part variations. The proposed CT∆ΣM applications such as magnetic sensing for position track-
with the LDO/VREF-buffer design operates on a power ing in Image-Guided or robotic surgery. To demonstrate
supply of 1.5 V, with a total power consumption of 380 the CT∆ΣM performance for the electromagnetic tracking
µW. Fig. 21 illustrates the breakdown of power usage, (EMT) of an on-chip sensor, full EMT system measure-
encompassing both the LDO/VREF buffer and the individual ments were carried out using the open-hardware ANSER
modulator blocks. EMT system [28]. The EMT system uses eight signal tones
To demonstrate the sensitivity of the CT∆ΣM to the jitter for tracking the instrument during image-guided or robotic
on the sampling clock of the modulator, it was tested with interventions [28]. The test setup is shown in Fig. 23. The
two sources: SMA100B from Rohde-Schwarz [26] and True test setup shows an on-chip sensor coil along with AFE, the
waveform generator from Keysight [27]. The SMA100B has CT∆ΣM and LDO. The signal generator generates 8 tones
the jitter of <1 ps (in a solid line), and the true waveform (20–34 kHz). This induces voltages in the on-chip sensor
generator has <40 ps (in a dotted line). As shown in Fig. 22, coil, which will be processed through the analog-front-end
the marginal 2 dB performance reduction underscores the (AFE) and then digitised by the CT∆ΣM using the 2nd

VOLUME , 9

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Manish Srivastava et al.:

a feed-forward architecture. The adder is moved to the input

of the second integrator, serving both as an integrator and
an adder. This enables the CT∆ΣM to achieve a state-of-
the-art area of 0.07 mm2 . Furthermore, a novel continuous-
time pulse-shaping digital-to-analog converter (CT-PS DAC)
is proposed to address excess loop delay (ELD). The CT-
PS DAC results in a significant reduction in the switching
current drawn from the reference buffer in the DAC. This
improvement enables the use of a single LDO for both the
CT∆ΣM power supply and the Vref supply for the DAC,
minimising overall area, and reducing power consumption.
The proposed CT∆ΣM is a good solution for magnetic
sensing applications, particularly in contexts such as mag-
netic tracking for image-guided and robotic interventions. Its
design considerations, emphasising low area and pin count,
render it well-suited for in-vivo scenarios. Furthermore, the
FIGURE 22. Clock jitter sensitivity to CT∆ΣM with FIR DAC.
CT∆ΣM presents significant advantages in reducing periph-
eral components and enabling sensor miniaturisation. This
Nyquist window (20-40 kHz) to process the signal. The on- not only enhances efficiency but also lays the foundation for
chip sensor achieves digitisation of the eight signal tones integrating diverse compact sensing systems, applicable in
within the frequency range of 20–34 kHz and transmits the biosensors and IoT (Internet of Things).
desired output off-chip for further processing to calculate the The proposed CT∆ΣM achieves signal-to-noise and dy-
position of the instrument [28]. Fig. 24 shows the resulting namic range values of 81.5 dB and 91 dB, respectively. The
output spectrum of the CT∆ΣM for the input obtained from overall system (CT∆ΣM and LDO/VREF-buffer) consumes
an on-chip sensor. The spectrum has a high-frequency tone 380 µW and occupies an area of 0.09 mm2 . The novel circuit
as the chopping was applied to an analog-front-end (AFE) techniques proposed in this paper allow to achieve cutting-
capacitively coupled instrument amplifier (CCIA) which was edge performance while getting the most efficient design in
filtered out off-chip. The spectrum was analysed by aver- terms of area occupancy which is a critical factor in sensor
aging eight 130K-point Fast-Fourier transforms. The eight interfaces for in-vivo applications such as those targeted in
tones exhibit varying signal strengths due to the dependence this work.
of the induced voltage on the magnetic sensor coil’s distance
from the eight transmitter coils. The CT∆ΣM’s output data REFERENCES
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10 VOLUME ,

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 This article has been accepted for publication in IEEE Open Journal of Circuits and Systems. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653
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Power supply

Field Magnetic sensor with AFE LDO with

generator coil ref. voltage buffer Logic analyzer
Rcoil Data
Lcoil AFE CTΔΣM
Clock

On-chip blocks
8-tones (20-34 kHz)
signal generator Clock generator Matlab processing unit
FIGURE 23. Test setup for testing the CT∆ΣM and on-chip magnetic sensor. The 8-tone input is the representation of the typical input signal in a
frequency-domain magnetic tracking application.

TABLE 4. Comparison with the state-of-the-art

Metric This Work [29] [17] [18] [5] [19] [20] [21] [22] [23]
Architecture CT CT CT CT CT CT CT Zoom DT Zoom Zoom DT
Tech [nm] 65 180 65 180 160 180 160 160 160 65
Area [mm2 ] 0.07/ 0.09a - 0.25 1 0.21 0.64 0.27 0.27 0.16 0.256
FIR DAC Y Y Y Y N Y N N N N
Supply [V] 1.5b 1.5 1.2 1.8 1.6 1.8 1.8 1.8 1.8 1.2
BW [kHz] 20 100 24 24 20 24 20 20 20 25
fs [MHz] 10.24 25.6 7.2 6.144 3 6.144 5.12 3.5 11.29 6.4
On-chip Ref. Buf with LDO Y N N N N N N N N N
Power [µW ] 300c /380d 222 232 280 390 265 618 440 1120 800
DR [dB] 91 79.8 104.8 103.6 103.1 104 108.5 109.8 109 103
SNDR [dB] 82 73.4 101 98.5 91.3 100 106.4 106.5 103 95.2
FOMe DR w/o buffer / with buffer [dB] 169.2/168.2 166 184.9 182.9 180 183 183.6 186.4 181.5 177.9
a area with LDO/VREF-buffer, b LDO/VREF-buffer input supply, cV power is included, d LDO/VREF-buffer power is included,
ref
e FOM
DR = DR + 10*log( PBW
ower
).

FIGURE 25. DFT of the output from the CT∆ΣM for the representative 8
FIGURE 24. Magnitude plot showing the performance of the CT∆ΣM with magnetic field tones (20-34 kHz). This is a typical frequency range for
magnetic sensor with the time-varying 8-tone (20-34 kHz) magnetic field. frequency-domain magnetic tracking [28].

on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3675– 3687, Nov. 2018.

VOLUME , 11

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content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653

Manish Srivastava et al.:

[9] R. Schreier, S. Pavan, and G. C. Temes, Understanding Delta-Sigma [29] D. Basak, D. Li, and K.-P. Pun, “A Gm-C Delta-Sigma Modulator
Data Converters, 1st ed. Wiley, Apr. 2017. With a Merged Input-Feedback Gm Circuit for Nonlinearity Can-
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DR 24kHz-BW CT ∆ΣM with Chopped AC-Coupled OTA-Stacking Manish Srivastava is a Ph.D. student in the
and FIR DACs,” in 2021 IEEE International Solid- State Circuits School of Electrical and Electronic Engineering
Conference (ISSCC). San Francisco, CA, USA: IEEE, Feb. 2021, at the University College Cork. Prior to this, he
pp. 166–168. worked as an Analog circuit design engineer at
[18] S. Billa, A. Sukumaran, and S. Pavan, “Analysis and Design of Synopsys INC from 2018 to 2019, and for Qual-
Continuous-Time Delta–Sigma Converters Incorporating Chopping,” comm from 2016 to 2018. He has five issued
IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2350–2361, patents and six pending patents. Manish’s current
Sep. 2017. research focuses on the development of electro-
[19] S. Billa, S. Dixit, and S. Pavan, “Analysis and Design of an Audio magnetic sensors and low noise sensor interface
Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator,” IEEE electronics circuits (such as the Low Noise CCIA
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2020. navigation applications such as bronchoscopy, electrophysiology mapping,
[20] B. Gönen, S. Karmakar, R. v. Veldhoven, and K. Makinwa, “A low and biopsies, among others.
power continuous-time zoom adc for audio applications,” in 2019
Symposium on VLSI Circuits, 2019, pp. C224–C225.
[21] E. Eland, S. Karmakar, B. Gönen, R. van Veldhoven, and K. Makinwa, Alessandro Ferro graduated with a Bachelor’s
“A 440w, 109.8db dr, 106.5db sndr discrete-time zoom adc with a Degree in Information Engineering from the Uni-
20khz bw,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. versity of Padua, Italy, in 2018. He is pursuing
1–2. a Master of Engineering Science (MEngSc) in
[22] B. Gönen, F. Sebastiano, R. Quan, R. van Veldhoven, and K. A. A. Electrical and Electronic Engineering at University
Makinwa, “A dynamic zoom adc with 109-db dr for audio applica- College Cork (UCC), Ireland. Since 2021, he has
tions,” IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1542– been a member of the Microelectronic Circuits
1550, 2017. Centre Ireland (MCCI) at the Tyndall National In-
[23] Y. H. Leow, H. Tang, Z. C. Sun, and L. Siek, “A 1 v 103 db 3rd- stitute, where he is contributing to the development
order audio continuous-time δσ adc with enhanced noise shaping in of an in-vivo sensor system that uses magnetic
65 nm cmos,” IEEE Journal of Solid-State Circuits, vol. 51, no. 11, signals to track surgical instruments for the Anser
pp. 2625–2638, 2016. EMT project. He is an active member of the IEEE Cork student branch,
[24] H. Chandrakumar and D. Marković, “A 15.2-enob 5-khz bw 4.5- µ focusing his research interests on integrating technology in medical devices
w Chopped ∆Σ -ADC for Artifact-Tolerant Neural Recording Front to enhance surgical procedures.
Ends,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3470–
3483, 2018.
[25] S. Chevella, D. O’Hare, and I. O’Connell, “A low-power 1-v supply Aleksandr Sidun (BSc’18 MSc’20) received the
dynamic comparator,” IEEE Solid-State Circuits Letters, vol. 3, pp. BSc degree in Electronic Engineering from Saint-
154–157, 2020. Petersburg Polytechnic University, Russia, in 2018
[26] Sma100b data sheet. [Online]. Available: https: and completed his MSc at Saint-Petersburg Poly-
//scdn.rohde-schwarz.com/ur/pws/dl downloads/pdm/cl brochures technic University in 2020. He joined the De-
and datasheets/specifications/5215 1018 22/SMA100B dat-sw en partment of Electronic Engineering at Polytechnic
5215-1018-22 v0703.pdf University in 2018 designing analog front-ends
[27] True waveform generator (5992-2572) data sheet. [Online]. Avail- for MEMS sensors. From 2020 to 2021 he was
able: https://www.keysight.com/us/en/assets/7018-05928/data-sheets/ with Digital Solutions, Moscow where he designed
5992-2572.pdf high-speed ADCs and power management circuits.
[28] H. A. Jaeger, A. M. Franz, K. O’Donoghue, A. Seitel, F. Trauzettel, In 2021 he joined the Microelectronic Circuits
L. Maier-Hein, and P. Cantillon-Murphy, “Anser EMT: the first open- Centre Ireland (MCCI) based at the Tyndall National Institute, University
source electromagnetic tracking platform for image-guided interven- College Cork designing power management circuits for electromagnetic
tions,” International Journal of Computer Assisted Radiology and tracking systems. He is currently an Analog Design Engineer at Analog
Surgery, vol. 12, no. 6, pp. 1059–1067, Jun. 2017. Devices International in Limerick designing DC-DC converter circuits.

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content may change prior to final publication. Citation information: DOI 10.1109/OJCAS.2024.3378653
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José M. de la Rosa (Fellow, IEEE) received research interests include electromagnetic tracking and navigation in image-
the M.S. degree in Physics in 1993 and the Ph.D. guided interventions, and surgical robotics. His teaching interests include
degree in Microelectronics in 2000, both from the electronic circuits, electromagnetics, and biomedical design. He is a former
University of Seville, Spain. Since 1993 he has Marie Curie fellow (2010-2014), a former MIT Whitaker fellow (2007-08),
been working at the Institute of Microelectronics a senior member of the IEEE, and an ERC awardee (2020). He has co-
of Seville (IMSE), which is in turn part of the founded two start-up companies.
Spanish Microelectronics Center (CNM) of the
Spanish National Research Council (CSIC). He is
also a Full Professor at the Dpt. of Electronics Daniel O’Hare (S’13 M’07) received the BE
and Electromagnetism of the University of Seville. degree in Electronic Engineering from University
His main research interests are in the field of College Dublin, Ireland, in 2000 and completed
analog and mixed-signal integrated circuits, especially high-performance his PhD at the University of Limerick in 2017.
data converters. In these topics, Dr. de la Rosa has participated in a He joined Motorola Semiconductor 2000 and from
number of Spanish and European research and industrial projects, and 2004 to 2008 he was with Freescale Semicon-
has co-authored over 270 international publications, including journal and ductor designing ADCs and DACs for Cellular
conference papers, 10 book chapters and 6 books, the latter one entitled transceivers. From 2008 to 2012 he was with M4S
CMOS Sigma-Delta Converters: Practical Design Guide (Wiley-IEEE Press, NV a spinout of IMEC and from 2013 to 2017
2013, 2nd Edition, 2018). He is in the World Top 2% Scientists List from he was an ADC researcher in the Circuits and
Stanford University (editions 2019, 2020, and 2022). Dr. de la Rosa is an Systems group at the University of Limerick. He
IEEE Fellow and member of the IEEE Circuits and Systems Society (CASS) is currently a Principal Researcher in the Microelectronic Circuits Centre
and the IEEE Solid-State Circuits Society (SSCS). He is a Member-at-Large Ireland (MCCI) based at the Tyndall National Institute, University College
of the IEEE-CASS Board of Governors (BoG) for the 2023-2025 term. He Cork. His research is in low-noise sensor interface circuits and integrated
served as a Distinguished Lecturer of IEEE-CASS (term 2017-2018), and circuits to enable medical systems. This includes the design of low voltage,
as Chair of the Spain Chapter of IEEE-CASS during the term 2016-2017. low noise, data-converters and analog signal conditioning circuits. Dr.
He was at the front of the Editorial Board of IEEE Transactions on Circuits O’Hare was co-recipient of the 2021 NEWCAS best student paper. Daniel
and Systems II: Express Briefs, where he served as Deputy Editor-in-Chief was the recipient of the 2023 Tyndall Mentor of the Year award. He has
since 2016 to 2019, and as Editor-in-Chief in the term 2020-2021. He is more than 15 published papers and two granted patents.
a member of the TechRxiv Editorial Advisory Board since 2022. He also
served as Associate Editor for IEEE Transactions on Circuits and Systems
I: Regular Papers, where he received the 2012-2013 Best Associate Editor
Award and was Guest Editor for the Special Issue on the Custom Integrated
Circuits Conference (CICC) in 2013 and 2014. He served as Guest Editor of
the Special Issue of the IEEE J. on Emerging and Selected Topics in Circuits
and Systems on Next-Generation Delta-Sigma Converters. He is a member
of the Analog Signal Processing Technical Committee of IEEE-CASS and
of the Steering Committee of IEEE MWSCAS. He has also been involved in
the organizing and technical committees of diverse international conferences,
among others IEEE ISCAS, IEEE MWSCAS, IEEE ICECS, IEEE LASCAS,
IFIP/IEEE VLSI-SoC, DATE and ESSCIRC. He served as TPC chair of
IEEE MWSCAS 2012, IEEE ICECS 2012, IEEE LASCAS 2015 and IEEE
ISICAS (2018, 2019). He has been a member of the Executive Committee
of the IEEE Spain Section (terms 2014-2015 and 2016-2017), where he
served as Membership Development Officer during the term 2016-2017. He
has been recently appointed as Editor-in-Chief of IEEE TCAS-I for the term
2024-2025.

Kilian O’Donoghue received B.E. and PhD de-

grees in electrical and electronic engineering from
University College Cork, Cork, Ireland, in 2011
and 2015 respectively. He has over ten years’
of experience in medical electronic design and
has worked in multiple start-up and early-stage
medical device companies in Ireland and Canada,
developing core technologies in robotics, sens-
ing, navigation, and medical imaging systems. His
research interests include EM tracking systems,
circuit design, magnetic field modeling, and min-
imally invasive surgeries.

Pádraig Cantillon-Murphy is a Professor of

Biomedical Engineering at University College
Cork, Ireland, academic member of Tyndall Na-
tional Institute at University College Cork, and an
honorary faculty at l’Institut de Chirurgie Guidée
par l’Image in Strasbourg. He graduated with a
first-class honours B.E. degree (2003) in Electrical
and Electronic Engineering from University Col-
lege Cork, Ireland before completing his Master
of Science (2005) and Ph.D. (2008) degrees at the
Department of Electrical Engineering and Com-
puter Science at Massachusetts Institute of Technology (MIT). His current

VOLUME , 13

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